exec_context.hh revision 13610:5d5404ac6288 
1/*
2 * Copyright (c) 2014, 2016-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2015 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 *          Andreas Sandberg
43 */
44
45#ifndef __CPU_EXEC_CONTEXT_HH__
46#define __CPU_EXEC_CONTEXT_HH__
47
48#include "arch/registers.hh"
49#include "base/types.hh"
50#include "config/the_isa.hh"
51#include "cpu/base.hh"
52#include "cpu/reg_class.hh"
53#include "cpu/static_inst_fwd.hh"
54#include "cpu/translation.hh"
55#include "mem/request.hh"
56
57/**
58 * The ExecContext is an abstract base class the provides the
59 * interface used by the ISA to manipulate the state of the CPU model.
60 *
61 * Register accessor methods in this class typically provide the index
62 * of the instruction's operand (e.g., 0 or 1), not the architectural
63 * register index, to simplify the implementation of register
64 * renaming.  The architectural register index can be found by
65 * indexing into the instruction's own operand index table.
66 *
67 * @note The methods in this class typically take a raw pointer to the
68 * StaticInst is provided instead of a ref-counted StaticInstPtr to
69 * reduce overhead as an argument. This is fine as long as the
70 * implementation doesn't copy the pointer into any long-term storage
71 * (which is pretty hard to imagine they would have reason to do).
72 */
73class ExecContext {
74  public:
75    typedef TheISA::PCState PCState;
76
77    typedef TheISA::CCReg CCReg;
78    using VecRegContainer = TheISA::VecRegContainer;
79    using VecElem = TheISA::VecElem;
80    using VecPredRegContainer = TheISA::VecPredRegContainer;
81
82  public:
83    /**
84     * @{
85     * @name Integer Register Interfaces
86     *
87     */
88
89    /** Reads an integer register. */
90    virtual RegVal readIntRegOperand(const StaticInst *si, int idx) = 0;
91
92    /** Sets an integer register to a value. */
93    virtual void setIntRegOperand(const StaticInst *si,
94                                  int idx, RegVal val) = 0;
95
96    /** @} */
97
98
99    /**
100     * @{
101     * @name Floating Point Register Interfaces
102     */
103
104    /** Reads a floating point register in its binary format, instead
105     * of by value. */
106    virtual RegVal readFloatRegOperandBits(const StaticInst *si, int idx) = 0;
107
108    /** Sets the bits of a floating point register of single width
109     * to a binary value. */
110    virtual void setFloatRegOperandBits(const StaticInst *si,
111                                        int idx, RegVal val) = 0;
112
113    /** @} */
114
115    /** Vector Register Interfaces. */
116    /** @{ */
117    /** Reads source vector register operand. */
118    virtual const VecRegContainer&
119    readVecRegOperand(const StaticInst *si, int idx) const = 0;
120
121    /** Gets destination vector register operand for modification. */
122    virtual VecRegContainer&
123    getWritableVecRegOperand(const StaticInst *si, int idx) = 0;
124
125    /** Sets a destination vector register operand to a value. */
126    virtual void
127    setVecRegOperand(const StaticInst *si, int idx,
128                     const VecRegContainer& val) = 0;
129    /** @} */
130
131    /** Vector Register Lane Interfaces. */
132    /** @{ */
133    /** Reads source vector 8bit operand. */
134    virtual ConstVecLane8
135    readVec8BitLaneOperand(const StaticInst *si, int idx) const = 0;
136
137    /** Reads source vector 16bit operand. */
138    virtual ConstVecLane16
139    readVec16BitLaneOperand(const StaticInst *si, int idx) const = 0;
140
141    /** Reads source vector 32bit operand. */
142    virtual ConstVecLane32
143    readVec32BitLaneOperand(const StaticInst *si, int idx) const = 0;
144
145    /** Reads source vector 64bit operand. */
146    virtual ConstVecLane64
147    readVec64BitLaneOperand(const StaticInst *si, int idx) const = 0;
148
149    /** Write a lane of the destination vector operand. */
150    /** @{ */
151    virtual void setVecLaneOperand(const StaticInst *si, int idx,
152            const LaneData<LaneSize::Byte>& val) = 0;
153    virtual void setVecLaneOperand(const StaticInst *si, int idx,
154            const LaneData<LaneSize::TwoByte>& val) = 0;
155    virtual void setVecLaneOperand(const StaticInst *si, int idx,
156            const LaneData<LaneSize::FourByte>& val) = 0;
157    virtual void setVecLaneOperand(const StaticInst *si, int idx,
158            const LaneData<LaneSize::EightByte>& val) = 0;
159    /** @} */
160
161    /** Vector Elem Interfaces. */
162    /** @{ */
163    /** Reads an element of a vector register. */
164    virtual VecElem readVecElemOperand(const StaticInst *si,
165                                        int idx) const = 0;
166
167    /** Sets a vector register to a value. */
168    virtual void setVecElemOperand(const StaticInst *si, int idx,
169                                   const VecElem val) = 0;
170    /** @} */
171
172    /** Predicate registers interface. */
173    /** @{ */
174    /** Reads source predicate register operand. */
175    virtual const VecPredRegContainer&
176    readVecPredRegOperand(const StaticInst *si, int idx) const = 0;
177
178    /** Gets destination predicate register operand for modification. */
179    virtual VecPredRegContainer&
180    getWritableVecPredRegOperand(const StaticInst *si, int idx) = 0;
181
182    /** Sets a destination predicate register operand to a value. */
183    virtual void
184    setVecPredRegOperand(const StaticInst *si, int idx,
185                         const VecPredRegContainer& val) = 0;
186    /** @} */
187
188    /**
189     * @{
190     * @name Condition Code Registers
191     */
192    virtual CCReg readCCRegOperand(const StaticInst *si, int idx) = 0;
193    virtual void setCCRegOperand(const StaticInst *si, int idx, CCReg val) = 0;
194    /** @} */
195
196    /**
197     * @{
198     * @name Misc Register Interfaces
199     */
200    virtual RegVal readMiscRegOperand(const StaticInst *si, int idx) = 0;
201    virtual void setMiscRegOperand(const StaticInst *si,
202                                   int idx, RegVal val) = 0;
203
204    /**
205     * Reads a miscellaneous register, handling any architectural
206     * side effects due to reading that register.
207     */
208    virtual RegVal readMiscReg(int misc_reg) = 0;
209
210    /**
211     * Sets a miscellaneous register, handling any architectural
212     * side effects due to writing that register.
213     */
214    virtual void setMiscReg(int misc_reg, RegVal val) = 0;
215
216    /** @} */
217
218    /**
219     * @{
220     * @name PC Control
221     */
222    virtual PCState pcState() const = 0;
223    virtual void pcState(const PCState &val) = 0;
224    /** @} */
225
226    /**
227     * @{
228     * @name Memory Interface
229     */
230    /**
231     * Perform an atomic memory read operation.  Must be overridden
232     * for exec contexts that support atomic memory mode.  Not pure
233     * virtual since exec contexts that only support timing memory
234     * mode need not override (though in that case this function
235     * should never be called).
236     */
237    virtual Fault readMem(Addr addr, uint8_t *data, unsigned int size,
238                          Request::Flags flags)
239    {
240        panic("ExecContext::readMem() should be overridden\n");
241    }
242
243    /**
244     * Initiate a timing memory read operation.  Must be overridden
245     * for exec contexts that support timing memory mode.  Not pure
246     * virtual since exec contexts that only support atomic memory
247     * mode need not override (though in that case this function
248     * should never be called).
249     */
250    virtual Fault initiateMemRead(Addr addr, unsigned int size,
251                                  Request::Flags flags)
252    {
253        panic("ExecContext::initiateMemRead() should be overridden\n");
254    }
255
256    /**
257     * For atomic-mode contexts, perform an atomic memory write operation.
258     * For timing-mode contexts, initiate a timing memory write operation.
259     */
260    virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr,
261                           Request::Flags flags, uint64_t *res) = 0;
262
263    /**
264     * Sets the number of consecutive store conditional failures.
265     */
266    virtual void setStCondFailures(unsigned int sc_failures) = 0;
267
268    /**
269     * Returns the number of consecutive store conditional failures.
270     */
271    virtual unsigned int readStCondFailures() const = 0;
272
273    /** @} */
274
275    /**
276     * @{
277     * @name SysCall Emulation Interfaces
278     */
279
280    /**
281     * Executes a syscall specified by the callnum.
282     */
283    virtual void syscall(int64_t callnum, Fault *fault) = 0;
284
285    /** @} */
286
287    /** Returns a pointer to the ThreadContext. */
288    virtual ThreadContext *tcBase() = 0;
289
290    /**
291     * @{
292     * @name Alpha-Specific Interfaces
293     */
294
295    /**
296     * Somewhat Alpha-specific function that handles returning from an
297     * error or interrupt.
298     */
299    virtual Fault hwrei() = 0;
300
301    /**
302     * Check for special simulator handling of specific PAL calls.  If
303     * return value is false, actual PAL call will be suppressed.
304     */
305    virtual bool simPalCheck(int palFunc) = 0;
306
307    /** @} */
308
309    /**
310     * @{
311     * @name ARM-Specific Interfaces
312     */
313
314    virtual bool readPredicate() const = 0;
315    virtual void setPredicate(bool val) = 0;
316
317    /** @} */
318
319    /**
320     * @{
321     * @name X86-Specific Interfaces
322     */
323
324    /**
325     * Invalidate a page in the DTLB <i>and</i> ITLB.
326     */
327    virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
328    virtual void armMonitor(Addr address) = 0;
329    virtual bool mwait(PacketPtr pkt) = 0;
330    virtual void mwaitAtomic(ThreadContext *tc) = 0;
331    virtual AddressMonitor *getAddrMonitor() = 0;
332
333    /** @} */
334
335    /**
336     * @{
337     * @name MIPS-Specific Interfaces
338     */
339
340#if THE_ISA == MIPS_ISA
341    virtual RegVal readRegOtherThread(const RegId &reg,
342                                       ThreadID tid=InvalidThreadID) = 0;
343    virtual void setRegOtherThread(const RegId& reg, RegVal val,
344                                   ThreadID tid=InvalidThreadID) = 0;
345#endif
346
347    /** @} */
348};
349
350#endif // __CPU_EXEC_CONTEXT_HH__
351