exec_context.hh revision 12106:7784fac1b159 
1/*
2 * Copyright (c) 2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2015 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 *          Andreas Sandberg
43 */
44
45#ifndef __CPU_EXEC_CONTEXT_HH__
46#define __CPU_EXEC_CONTEXT_HH__
47
48#include "arch/registers.hh"
49#include "base/types.hh"
50#include "config/the_isa.hh"
51#include "cpu/base.hh"
52#include "cpu/reg_class.hh"
53#include "cpu/static_inst_fwd.hh"
54#include "cpu/translation.hh"
55#include "mem/request.hh"
56
57/**
58 * The ExecContext is an abstract base class the provides the
59 * interface used by the ISA to manipulate the state of the CPU model.
60 *
61 * Register accessor methods in this class typically provide the index
62 * of the instruction's operand (e.g., 0 or 1), not the architectural
63 * register index, to simplify the implementation of register
64 * renaming.  The architectural register index can be found by
65 * indexing into the instruction's own operand index table.
66 *
67 * @note The methods in this class typically take a raw pointer to the
68 * StaticInst is provided instead of a ref-counted StaticInstPtr to
69 * reduce overhead as an argument. This is fine as long as the
70 * implementation doesn't copy the pointer into any long-term storage
71 * (which is pretty hard to imagine they would have reason to do).
72 */
73class ExecContext {
74  public:
75    typedef TheISA::IntReg IntReg;
76    typedef TheISA::PCState PCState;
77    typedef TheISA::FloatReg FloatReg;
78    typedef TheISA::FloatRegBits FloatRegBits;
79    typedef TheISA::MiscReg MiscReg;
80
81    typedef TheISA::CCReg CCReg;
82
83  public:
84    /**
85     * @{
86     * @name Integer Register Interfaces
87     *
88     */
89
90    /** Reads an integer register. */
91    virtual IntReg readIntRegOperand(const StaticInst *si, int idx) = 0;
92
93    /** Sets an integer register to a value. */
94    virtual void setIntRegOperand(const StaticInst *si,
95                                  int idx, IntReg val) = 0;
96
97    /** @} */
98
99
100    /**
101     * @{
102     * @name Floating Point Register Interfaces
103     */
104
105    /** Reads a floating point register of single register width. */
106    virtual FloatReg readFloatRegOperand(const StaticInst *si, int idx) = 0;
107
108    /** Reads a floating point register in its binary format, instead
109     * of by value. */
110    virtual FloatRegBits readFloatRegOperandBits(const StaticInst *si,
111                                                 int idx) = 0;
112
113    /** Sets a floating point register of single width to a value. */
114    virtual void setFloatRegOperand(const StaticInst *si,
115                                    int idx, FloatReg val) = 0;
116
117    /** Sets the bits of a floating point register of single width
118     * to a binary value. */
119    virtual void setFloatRegOperandBits(const StaticInst *si,
120                                        int idx, FloatRegBits val) = 0;
121
122    /** @} */
123
124    /**
125     * @{
126     * @name Condition Code Registers
127     */
128    virtual CCReg readCCRegOperand(const StaticInst *si, int idx) = 0;
129    virtual void setCCRegOperand(const StaticInst *si, int idx, CCReg val) = 0;
130    /** @} */
131
132    /**
133     * @{
134     * @name Misc Register Interfaces
135     */
136    virtual MiscReg readMiscRegOperand(const StaticInst *si, int idx) = 0;
137    virtual void setMiscRegOperand(const StaticInst *si,
138                                   int idx, const MiscReg &val) = 0;
139
140    /**
141     * Reads a miscellaneous register, handling any architectural
142     * side effects due to reading that register.
143     */
144    virtual MiscReg readMiscReg(int misc_reg) = 0;
145
146    /**
147     * Sets a miscellaneous register, handling any architectural
148     * side effects due to writing that register.
149     */
150    virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
151
152    /** @} */
153
154    /**
155     * @{
156     * @name PC Control
157     */
158    virtual PCState pcState() const = 0;
159    virtual void pcState(const PCState &val) = 0;
160    /** @} */
161
162    /**
163     * @{
164     * @name Memory Interface
165     */
166    /**
167     * Record the effective address of the instruction.
168     *
169     * @note Only valid for memory ops.
170     */
171    virtual void setEA(Addr EA) = 0;
172    /**
173     * Get the effective address of the instruction.
174     *
175     * @note Only valid for memory ops.
176     */
177    virtual Addr getEA() const = 0;
178
179    /**
180     * Perform an atomic memory read operation.  Must be overridden
181     * for exec contexts that support atomic memory mode.  Not pure
182     * virtual since exec contexts that only support timing memory
183     * mode need not override (though in that case this function
184     * should never be called).
185     */
186    virtual Fault readMem(Addr addr, uint8_t *data, unsigned int size,
187                          Request::Flags flags)
188    {
189        panic("ExecContext::readMem() should be overridden\n");
190    }
191
192    /**
193     * Initiate a timing memory read operation.  Must be overridden
194     * for exec contexts that support timing memory mode.  Not pure
195     * virtual since exec contexts that only support atomic memory
196     * mode need not override (though in that case this function
197     * should never be called).
198     */
199    virtual Fault initiateMemRead(Addr addr, unsigned int size,
200                                  Request::Flags flags)
201    {
202        panic("ExecContext::initiateMemRead() should be overridden\n");
203    }
204
205    /**
206     * For atomic-mode contexts, perform an atomic memory write operation.
207     * For timing-mode contexts, initiate a timing memory write operation.
208     */
209    virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr,
210                           Request::Flags flags, uint64_t *res) = 0;
211
212    /**
213     * Sets the number of consecutive store conditional failures.
214     */
215    virtual void setStCondFailures(unsigned int sc_failures) = 0;
216
217    /**
218     * Returns the number of consecutive store conditional failures.
219     */
220    virtual unsigned int readStCondFailures() const = 0;
221
222    /** @} */
223
224    /**
225     * @{
226     * @name SysCall Emulation Interfaces
227     */
228
229    /**
230     * Executes a syscall specified by the callnum.
231     */
232    virtual void syscall(int64_t callnum, Fault *fault) = 0;
233
234    /** @} */
235
236    /** Returns a pointer to the ThreadContext. */
237    virtual ThreadContext *tcBase() = 0;
238
239    /**
240     * @{
241     * @name Alpha-Specific Interfaces
242     */
243
244    /**
245     * Somewhat Alpha-specific function that handles returning from an
246     * error or interrupt.
247     */
248    virtual Fault hwrei() = 0;
249
250    /**
251     * Check for special simulator handling of specific PAL calls.  If
252     * return value is false, actual PAL call will be suppressed.
253     */
254    virtual bool simPalCheck(int palFunc) = 0;
255
256    /** @} */
257
258    /**
259     * @{
260     * @name ARM-Specific Interfaces
261     */
262
263    virtual bool readPredicate() = 0;
264    virtual void setPredicate(bool val) = 0;
265
266    /** @} */
267
268    /**
269     * @{
270     * @name X86-Specific Interfaces
271     */
272
273    /**
274     * Invalidate a page in the DTLB <i>and</i> ITLB.
275     */
276    virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
277    virtual void armMonitor(Addr address) = 0;
278    virtual bool mwait(PacketPtr pkt) = 0;
279    virtual void mwaitAtomic(ThreadContext *tc) = 0;
280    virtual AddressMonitor *getAddrMonitor() = 0;
281
282    /** @} */
283
284    /**
285     * @{
286     * @name MIPS-Specific Interfaces
287     */
288
289#if THE_ISA == MIPS_ISA
290    virtual MiscReg readRegOtherThread(const RegId& reg,
291                                       ThreadID tid = InvalidThreadID) = 0;
292    virtual void setRegOtherThread(const RegId& reg, MiscReg val,
293                                   ThreadID tid = InvalidThreadID) = 0;
294#endif
295
296    /** @} */
297};
298
299#endif // __CPU_EXEC_CONTEXT_HH__
300