exec_context.hh revision 11303:f694764d656d 
1/*
2 * Copyright (c) 2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2015 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 *          Andreas Sandberg
43 */
44
45#ifndef __CPU_EXEC_CONTEXT_HH__
46#define __CPU_EXEC_CONTEXT_HH__
47
48#include "arch/registers.hh"
49#include "base/types.hh"
50#include "config/the_isa.hh"
51#include "cpu/base.hh"
52#include "cpu/static_inst_fwd.hh"
53#include "cpu/translation.hh"
54
55/**
56 * The ExecContext is an abstract base class the provides the
57 * interface used by the ISA to manipulate the state of the CPU model.
58 *
59 * Register accessor methods in this class typically provide the index
60 * of the instruction's operand (e.g., 0 or 1), not the architectural
61 * register index, to simplify the implementation of register
62 * renaming.  The architectural register index can be found by
63 * indexing into the instruction's own operand index table.
64 *
65 * @note The methods in this class typically take a raw pointer to the
66 * StaticInst is provided instead of a ref-counted StaticInstPtr to
67 * reduce overhead as an argument. This is fine as long as the
68 * implementation doesn't copy the pointer into any long-term storage
69 * (which is pretty hard to imagine they would have reason to do).
70 */
71class ExecContext {
72  public:
73    typedef TheISA::IntReg IntReg;
74    typedef TheISA::PCState PCState;
75    typedef TheISA::FloatReg FloatReg;
76    typedef TheISA::FloatRegBits FloatRegBits;
77    typedef TheISA::MiscReg MiscReg;
78
79    typedef TheISA::CCReg CCReg;
80
81  public:
82    /**
83     * @{
84     * @name Integer Register Interfaces
85     *
86     */
87
88    /** Reads an integer register. */
89    virtual IntReg readIntRegOperand(const StaticInst *si, int idx) = 0;
90
91    /** Sets an integer register to a value. */
92    virtual void setIntRegOperand(const StaticInst *si,
93                                  int idx, IntReg val) = 0;
94
95    /** @} */
96
97
98    /**
99     * @{
100     * @name Floating Point Register Interfaces
101     */
102
103    /** Reads a floating point register of single register width. */
104    virtual FloatReg readFloatRegOperand(const StaticInst *si, int idx) = 0;
105
106    /** Reads a floating point register in its binary format, instead
107     * of by value. */
108    virtual FloatRegBits readFloatRegOperandBits(const StaticInst *si,
109                                                 int idx) = 0;
110
111    /** Sets a floating point register of single width to a value. */
112    virtual void setFloatRegOperand(const StaticInst *si,
113                                    int idx, FloatReg val) = 0;
114
115    /** Sets the bits of a floating point register of single width
116     * to a binary value. */
117    virtual void setFloatRegOperandBits(const StaticInst *si,
118                                        int idx, FloatRegBits val) = 0;
119
120    /** @} */
121
122    /**
123     * @{
124     * @name Condition Code Registers
125     */
126    virtual CCReg readCCRegOperand(const StaticInst *si, int idx) = 0;
127    virtual void setCCRegOperand(const StaticInst *si, int idx, CCReg val) = 0;
128    /** @} */
129
130    /**
131     * @{
132     * @name Misc Register Interfaces
133     */
134    virtual MiscReg readMiscRegOperand(const StaticInst *si, int idx) = 0;
135    virtual void setMiscRegOperand(const StaticInst *si,
136                                   int idx, const MiscReg &val) = 0;
137
138    /**
139     * Reads a miscellaneous register, handling any architectural
140     * side effects due to reading that register.
141     */
142    virtual MiscReg readMiscReg(int misc_reg) = 0;
143
144    /**
145     * Sets a miscellaneous register, handling any architectural
146     * side effects due to writing that register.
147     */
148    virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
149
150    /** @} */
151
152    /**
153     * @{
154     * @name PC Control
155     */
156    virtual PCState pcState() const = 0;
157    virtual void pcState(const PCState &val) = 0;
158    /** @} */
159
160    /**
161     * @{
162     * @name Memory Interface
163     */
164    /**
165     * Record the effective address of the instruction.
166     *
167     * @note Only valid for memory ops.
168     */
169    virtual void setEA(Addr EA) = 0;
170    /**
171     * Get the effective address of the instruction.
172     *
173     * @note Only valid for memory ops.
174     */
175    virtual Addr getEA() const = 0;
176
177    /**
178     * Perform an atomic memory read operation.  Must be overridden
179     * for exec contexts that support atomic memory mode.  Not pure
180     * virtual since exec contexts that only support timing memory
181     * mode need not override (though in that case this function
182     * should never be called).
183     */
184    virtual Fault readMem(Addr addr, uint8_t *data, unsigned int size,
185                          unsigned int flags)
186    {
187        panic("ExecContext::readMem() should be overridden\n");
188    }
189
190    /**
191     * Initiate a timing memory read operation.  Must be overridden
192     * for exec contexts that support timing memory mode.  Not pure
193     * virtual since exec contexts that only support atomic memory
194     * mode need not override (though in that case this function
195     * should never be called).
196     */
197    virtual Fault initiateMemRead(Addr addr, unsigned int size,
198                                  unsigned int flags)
199    {
200        panic("ExecContext::initiateMemRead() should be overridden\n");
201    }
202
203    /**
204     * For atomic-mode contexts, perform an atomic memory write operation.
205     * For timing-mode contexts, initiate a timing memory write operation.
206     */
207    virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr,
208                           unsigned int flags, uint64_t *res) = 0;
209
210    /**
211     * Sets the number of consecutive store conditional failures.
212     */
213    virtual void setStCondFailures(unsigned int sc_failures) = 0;
214
215    /**
216     * Returns the number of consecutive store conditional failures.
217     */
218    virtual unsigned int readStCondFailures() const = 0;
219
220    /** @} */
221
222    /**
223     * @{
224     * @name SysCall Emulation Interfaces
225     */
226
227    /**
228     * Executes a syscall specified by the callnum.
229     */
230    virtual void syscall(int64_t callnum) = 0;
231
232    /** @} */
233
234    /** Returns a pointer to the ThreadContext. */
235    virtual ThreadContext *tcBase() = 0;
236
237    /**
238     * @{
239     * @name Alpha-Specific Interfaces
240     */
241
242    /**
243     * Somewhat Alpha-specific function that handles returning from an
244     * error or interrupt.
245     */
246    virtual Fault hwrei() = 0;
247
248    /**
249     * Check for special simulator handling of specific PAL calls.  If
250     * return value is false, actual PAL call will be suppressed.
251     */
252    virtual bool simPalCheck(int palFunc) = 0;
253
254    /** @} */
255
256    /**
257     * @{
258     * @name ARM-Specific Interfaces
259     */
260
261    virtual bool readPredicate() = 0;
262    virtual void setPredicate(bool val) = 0;
263
264    /** @} */
265
266    /**
267     * @{
268     * @name X86-Specific Interfaces
269     */
270
271    /**
272     * Invalidate a page in the DTLB <i>and</i> ITLB.
273     */
274    virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
275    virtual void armMonitor(Addr address) = 0;
276    virtual bool mwait(PacketPtr pkt) = 0;
277    virtual void mwaitAtomic(ThreadContext *tc) = 0;
278    virtual AddressMonitor *getAddrMonitor() = 0;
279
280    /** @} */
281
282    /**
283     * @{
284     * @name MIPS-Specific Interfaces
285     */
286
287#if THE_ISA == MIPS_ISA
288    virtual MiscReg readRegOtherThread(int regIdx,
289                                       ThreadID tid = InvalidThreadID) = 0;
290    virtual void setRegOtherThread(int regIdx, MiscReg val,
291                                   ThreadID tid = InvalidThreadID) = 0;
292#endif
293
294    /** @} */
295};
296
297#endif // __CPU_EXEC_CONTEXT_HH__
298