exec_context.hh revision 10934:5af8f40d8f2c 
1/*
2 * Copyright (c) 2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 *          Andreas Sandberg
42 */
43
44#ifndef __CPU_EXEC_CONTEXT_HH__
45#define __CPU_EXEC_CONTEXT_HH__
46
47#include "arch/registers.hh"
48#include "base/types.hh"
49#include "config/the_isa.hh"
50#include "cpu/base.hh"
51#include "cpu/static_inst_fwd.hh"
52#include "cpu/translation.hh"
53
54/**
55 * The ExecContext is an abstract base class the provides the
56 * interface used by the ISA to manipulate the state of the CPU model.
57 *
58 * Register accessor methods in this class typically provide the index
59 * of the instruction's operand (e.g., 0 or 1), not the architectural
60 * register index, to simplify the implementation of register
61 * renaming.  The architectural register index can be found by
62 * indexing into the instruction's own operand index table.
63 *
64 * @note The methods in this class typically take a raw pointer to the
65 * StaticInst is provided instead of a ref-counted StaticInstPtr to
66 * reduce overhead as an argument. This is fine as long as the
67 * implementation doesn't copy the pointer into any long-term storage
68 * (which is pretty hard to imagine they would have reason to do).
69 */
70class ExecContext {
71  public:
72    typedef TheISA::IntReg IntReg;
73    typedef TheISA::PCState PCState;
74    typedef TheISA::FloatReg FloatReg;
75    typedef TheISA::FloatRegBits FloatRegBits;
76    typedef TheISA::MiscReg MiscReg;
77
78    typedef TheISA::CCReg CCReg;
79    typedef TheISA::VectorReg VectorReg;
80
81  public:
82    /**
83     * @{
84     * @name Integer Register Interfaces
85     *
86     */
87
88    /** Reads an integer register. */
89    virtual IntReg readIntRegOperand(const StaticInst *si, int idx) = 0;
90
91    /** Sets an integer register to a value. */
92    virtual void setIntRegOperand(const StaticInst *si,
93                                  int idx, IntReg val) = 0;
94
95    /** @} */
96
97
98    /**
99     * @{
100     * @name Floating Point Register Interfaces
101     */
102
103    /** Reads a floating point register of single register width. */
104    virtual FloatReg readFloatRegOperand(const StaticInst *si, int idx) = 0;
105
106    /** Reads a floating point register in its binary format, instead
107     * of by value. */
108    virtual FloatRegBits readFloatRegOperandBits(const StaticInst *si,
109                                                 int idx) = 0;
110
111    /** Sets a floating point register of single width to a value. */
112    virtual void setFloatRegOperand(const StaticInst *si,
113                                    int idx, FloatReg val) = 0;
114
115    /** Sets the bits of a floating point register of single width
116     * to a binary value. */
117    virtual void setFloatRegOperandBits(const StaticInst *si,
118                                        int idx, FloatRegBits val) = 0;
119
120    /** @} */
121
122    /**
123     * @{
124     * @name Condition Code Registers
125     */
126    virtual CCReg readCCRegOperand(const StaticInst *si, int idx) = 0;
127    virtual void setCCRegOperand(const StaticInst *si, int idx, CCReg val) = 0;
128    /** @} */
129
130    /**
131     * @{
132     * @name Vector Register Interfaces
133     *
134     */
135
136    /** Reads a vector register. */
137    virtual const VectorReg &readVectorRegOperand (const StaticInst *si,
138                                                   int idx) = 0;
139
140    /** Sets a vector register to a value. */
141    virtual void setVectorRegOperand(const StaticInst *si,
142                                     int idx, const VectorReg &val) = 0;
143
144    /** @} */
145
146    /**
147     * @{
148     * @name Misc Register Interfaces
149     */
150    virtual MiscReg readMiscRegOperand(const StaticInst *si, int idx) = 0;
151    virtual void setMiscRegOperand(const StaticInst *si,
152                                   int idx, const MiscReg &val) = 0;
153
154    /**
155     * Reads a miscellaneous register, handling any architectural
156     * side effects due to reading that register.
157     */
158    virtual MiscReg readMiscReg(int misc_reg) = 0;
159
160    /**
161     * Sets a miscellaneous register, handling any architectural
162     * side effects due to writing that register.
163     */
164    virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
165
166    /** @} */
167
168    /**
169     * @{
170     * @name PC Control
171     */
172    virtual PCState pcState() const = 0;
173    virtual void pcState(const PCState &val) = 0;
174    /** @} */
175
176    /**
177     * @{
178     * @name Memory Interface
179     */
180    /**
181     * Record the effective address of the instruction.
182     *
183     * @note Only valid for memory ops.
184     */
185    virtual void setEA(Addr EA) = 0;
186    /**
187     * Get the effective address of the instruction.
188     *
189     * @note Only valid for memory ops.
190     */
191    virtual Addr getEA() const = 0;
192
193    virtual Fault readMem(Addr addr, uint8_t *data, unsigned int size,
194                          unsigned int flags) = 0;
195
196    virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr,
197                           unsigned int flags, uint64_t *res) = 0;
198
199    /**
200     * Sets the number of consecutive store conditional failures.
201     */
202    virtual void setStCondFailures(unsigned int sc_failures) = 0;
203
204    /**
205     * Returns the number of consecutive store conditional failures.
206     */
207    virtual unsigned int readStCondFailures() const = 0;
208
209    /** @} */
210
211    /**
212     * @{
213     * @name SysCall Emulation Interfaces
214     */
215
216    /**
217     * Executes a syscall specified by the callnum.
218     */
219    virtual void syscall(int64_t callnum) = 0;
220
221    /** @} */
222
223    /** Returns a pointer to the ThreadContext. */
224    virtual ThreadContext *tcBase() = 0;
225
226    /**
227     * @{
228     * @name Alpha-Specific Interfaces
229     */
230
231    /**
232     * Somewhat Alpha-specific function that handles returning from an
233     * error or interrupt.
234     */
235    virtual Fault hwrei() = 0;
236
237    /**
238     * Check for special simulator handling of specific PAL calls.  If
239     * return value is false, actual PAL call will be suppressed.
240     */
241    virtual bool simPalCheck(int palFunc) = 0;
242
243    /** @} */
244
245    /**
246     * @{
247     * @name ARM-Specific Interfaces
248     */
249
250    virtual bool readPredicate() = 0;
251    virtual void setPredicate(bool val) = 0;
252
253    /** @} */
254
255    /**
256     * @{
257     * @name X86-Specific Interfaces
258     */
259
260    /**
261     * Invalidate a page in the DTLB <i>and</i> ITLB.
262     */
263    virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
264    virtual void armMonitor(Addr address) = 0;
265    virtual bool mwait(PacketPtr pkt) = 0;
266    virtual void mwaitAtomic(ThreadContext *tc) = 0;
267    virtual AddressMonitor *getAddrMonitor() = 0;
268
269    /** @} */
270
271    /**
272     * @{
273     * @name MIPS-Specific Interfaces
274     */
275
276#if THE_ISA == MIPS_ISA
277    virtual MiscReg readRegOtherThread(int regIdx,
278                                       ThreadID tid = InvalidThreadID) = 0;
279    virtual void setRegOtherThread(int regIdx, MiscReg val,
280                                   ThreadID tid = InvalidThreadID) = 0;
281#endif
282
283    /** @} */
284};
285
286#endif // __CPU_EXEC_CONTEXT_HH__
287