exec_context.hh revision 10474:799c8ee4ecba 
1/*
2 * Copyright (c) 2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 *          Andreas Sandberg
42 */
43
44#ifndef __CPU_EXEC_CONTEXT_HH__
45#define __CPU_EXEC_CONTEXT_HH__
46
47#include "arch/registers.hh"
48#include "base/types.hh"
49#include "config/the_isa.hh"
50#include "cpu/static_inst_fwd.hh"
51#include "cpu/translation.hh"
52
53/**
54 * The ExecContext is an abstract base class the provides the
55 * interface used by the ISA to manipulate the state of the CPU model.
56 *
57 * Register accessor methods in this class typically provide the index
58 * of the instruction's operand (e.g., 0 or 1), not the architectural
59 * register index, to simplify the implementation of register
60 * renaming.  The architectural register index can be found by
61 * indexing into the instruction's own operand index table.
62 *
63 * @note The methods in this class typically take a raw pointer to the
64 * StaticInst is provided instead of a ref-counted StaticInstPtr to
65 * reduce overhead as an argument. This is fine as long as the
66 * implementation doesn't copy the pointer into any long-term storage
67 * (which is pretty hard to imagine they would have reason to do).
68 */
69class ExecContext {
70  public:
71    typedef TheISA::IntReg IntReg;
72    typedef TheISA::PCState PCState;
73    typedef TheISA::FloatReg FloatReg;
74    typedef TheISA::FloatRegBits FloatRegBits;
75    typedef TheISA::MiscReg MiscReg;
76
77    typedef TheISA::CCReg CCReg;
78
79  public:
80    /**
81     * @{
82     * @name Integer Register Interfaces
83     *
84     */
85
86    /** Reads an integer register. */
87    virtual IntReg readIntRegOperand(const StaticInst *si, int idx) = 0;
88
89    /** Sets an integer register to a value. */
90    virtual void setIntRegOperand(const StaticInst *si,
91                                  int idx, IntReg val) = 0;
92
93    /** @} */
94
95
96    /**
97     * @{
98     * @name Floating Point Register Interfaces
99     */
100
101    /** Reads a floating point register of single register width. */
102    virtual FloatReg readFloatRegOperand(const StaticInst *si, int idx) = 0;
103
104    /** Reads a floating point register in its binary format, instead
105     * of by value. */
106    virtual FloatRegBits readFloatRegOperandBits(const StaticInst *si,
107                                                 int idx) = 0;
108
109    /** Sets a floating point register of single width to a value. */
110    virtual void setFloatRegOperand(const StaticInst *si,
111                                    int idx, FloatReg val) = 0;
112
113    /** Sets the bits of a floating point register of single width
114     * to a binary value. */
115    virtual void setFloatRegOperandBits(const StaticInst *si,
116                                        int idx, FloatRegBits val) = 0;
117
118    /** @} */
119
120    /**
121     * @{
122     * @name Condition Code Registers
123     */
124    virtual CCReg readCCRegOperand(const StaticInst *si, int idx) = 0;
125    virtual void setCCRegOperand(const StaticInst *si, int idx, CCReg val) = 0;
126    /** @} */
127
128    /**
129     * @{
130     * @name Misc Register Interfaces
131     */
132    virtual MiscReg readMiscRegOperand(const StaticInst *si, int idx) = 0;
133    virtual void setMiscRegOperand(const StaticInst *si,
134                                   int idx, const MiscReg &val) = 0;
135
136    /**
137     * Reads a miscellaneous register, handling any architectural
138     * side effects due to reading that register.
139     */
140    virtual MiscReg readMiscReg(int misc_reg) = 0;
141
142    /**
143     * Sets a miscellaneous register, handling any architectural
144     * side effects due to writing that register.
145     */
146    virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
147
148    /** @} */
149
150    /**
151     * @{
152     * @name PC Control
153     */
154    virtual PCState pcState() const = 0;
155    virtual void pcState(const PCState &val) = 0;
156    /** @} */
157
158    /**
159     * @{
160     * @name Memory Interface
161     */
162    /**
163     * Record the effective address of the instruction.
164     *
165     * @note Only valid for memory ops.
166     */
167    virtual void setEA(Addr EA) = 0;
168    /**
169     * Get the effective address of the instruction.
170     *
171     * @note Only valid for memory ops.
172     */
173    virtual Addr getEA() const = 0;
174
175    virtual Fault readMem(Addr addr, uint8_t *data, unsigned int size,
176                          unsigned int flags) = 0;
177
178    virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr,
179                           unsigned int flags, uint64_t *res) = 0;
180
181    /**
182     * Sets the number of consecutive store conditional failures.
183     */
184    virtual void setStCondFailures(unsigned int sc_failures) = 0;
185
186    /**
187     * Returns the number of consecutive store conditional failures.
188     */
189    virtual unsigned int readStCondFailures() const = 0;
190
191    /** @} */
192
193    /**
194     * @{
195     * @name SysCall Emulation Interfaces
196     */
197
198    /**
199     * Executes a syscall specified by the callnum.
200     */
201    virtual void syscall(int64_t callnum) = 0;
202
203    /** @} */
204
205    /** Returns a pointer to the ThreadContext. */
206    virtual ThreadContext *tcBase() = 0;
207
208    /**
209     * @{
210     * @name Alpha-Specific Interfaces
211     */
212
213    /**
214     * Somewhat Alpha-specific function that handles returning from an
215     * error or interrupt.
216     */
217    virtual Fault hwrei() = 0;
218
219    /**
220     * Check for special simulator handling of specific PAL calls.  If
221     * return value is false, actual PAL call will be suppressed.
222     */
223    virtual bool simPalCheck(int palFunc) = 0;
224
225    /** @} */
226
227    /**
228     * @{
229     * @name ARM-Specific Interfaces
230     */
231
232    virtual bool readPredicate() = 0;
233    virtual void setPredicate(bool val) = 0;
234
235    /** @} */
236
237    /**
238     * @{
239     * @name X86-Specific Interfaces
240     */
241
242    /**
243     * Invalidate a page in the DTLB <i>and</i> ITLB.
244     */
245    virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
246
247    /** @} */
248
249    /**
250     * @{
251     * @name MIPS-Specific Interfaces
252     */
253
254#if THE_ISA == MIPS_ISA
255    virtual MiscReg readRegOtherThread(int regIdx,
256                                       ThreadID tid = InvalidThreadID) = 0;
257    virtual void setRegOtherThread(int regIdx, MiscReg val,
258                                   ThreadID tid = InvalidThreadID) = 0;
259#endif
260
261    /** @} */
262};
263
264#endif // __CPU_EXEC_CONTEXT_HH__
265