exec_context.hh revision 10529
12SN/A/* 21762SN/A * Copyright (c) 2014 ARM Limited 32SN/A * All rights reserved 42SN/A * 52SN/A * The license below extends only to copyright in the software and shall 62SN/A * not be construed as granting a license to any other intellectual 72SN/A * property including but not limited to intellectual property relating 82SN/A * to a hardware implementation of the functionality of the software 92SN/A * licensed hereunder. You may use the software subject to the license 102SN/A * terms below provided that you ensure that this notice is replicated 112SN/A * unmodified and in its entirety in all distributions of the software, 122SN/A * modified or unmodified, in source code or in binary form. 132SN/A * 142SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 152SN/A * All rights reserved. 162SN/A * 172SN/A * Redistribution and use in source and binary forms, with or without 182SN/A * modification, are permitted provided that the following conditions are 192SN/A * met: redistributions of source code must retain the above copyright 202SN/A * notice, this list of conditions and the following disclaimer; 212SN/A * redistributions in binary form must reproduce the above copyright 222SN/A * notice, this list of conditions and the following disclaimer in the 232SN/A * documentation and/or other materials provided with the distribution; 242SN/A * neither the name of the copyright holders nor the names of its 252SN/A * contributors may be used to endorse or promote products derived from 262SN/A * this software without specific prior written permission. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312439SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322984Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33146SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34146SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35146SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36146SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37146SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38146SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 391717SN/A * 40146SN/A * Authors: Kevin Lim 411717SN/A * Andreas Sandberg 42146SN/A */ 431977SN/A 442623SN/A#ifndef __CPU_EXEC_CONTEXT_HH__ 452683Sktlim@umich.edu#define __CPU_EXEC_CONTEXT_HH__ 461717SN/A 47146SN/A#include "arch/registers.hh" 482683Sktlim@umich.edu#include "base/types.hh" 491917SN/A#include "config/the_isa.hh" 503348Sbinkertn@umich.edu#include "cpu/base.hh" 512683Sktlim@umich.edu#include "cpu/static_inst_fwd.hh" 522036SN/A#include "cpu/translation.hh" 53146SN/A 5456SN/A/** 5556SN/A * The ExecContext is an abstract base class the provides the 5656SN/A * interface used by the ISA to manipulate the state of the CPU model. 57695SN/A * 582901Ssaidi@eecs.umich.edu * Register accessor methods in this class typically provide the index 592SN/A * of the instruction's operand (e.g., 0 or 1), not the architectural 601858SN/A * register index, to simplify the implementation of register 6156SN/A * renaming. The architectural register index can be found by 622171SN/A * indexing into the instruction's own operand index table. 632170SN/A * 642170SN/A * @note The methods in this class typically take a raw pointer to the 65146SN/A * StaticInst is provided instead of a ref-counted StaticInstPtr to 662462SN/A * reduce overhead as an argument. This is fine as long as the 67146SN/A * implementation doesn't copy the pointer into any long-term storage 682SN/A * (which is pretty hard to imagine they would have reason to do). 692SN/A */ 702449SN/Aclass ExecContext { 711355SN/A public: 722623SN/A typedef TheISA::IntReg IntReg; 732683Sktlim@umich.edu typedef TheISA::PCState PCState; 74224SN/A typedef TheISA::FloatReg FloatReg; 751858SN/A typedef TheISA::FloatRegBits FloatRegBits; 762683Sktlim@umich.edu typedef TheISA::MiscReg MiscReg; 772420SN/A 782683Sktlim@umich.edu typedef TheISA::CCReg CCReg; 792520SN/A 802420SN/A public: 812SN/A /** 822683Sktlim@umich.edu * @{ 832672Sktlim@umich.edu * @name Integer Register Interfaces 842683Sktlim@umich.edu * 852SN/A */ 862SN/A 87334SN/A /** Reads an integer register. */ 88140SN/A virtual IntReg readIntRegOperand(const StaticInst *si, int idx) = 0; 89334SN/A 902SN/A /** Sets an integer register to a value. */ 912SN/A virtual void setIntRegOperand(const StaticInst *si, 922SN/A int idx, IntReg val) = 0; 932680Sktlim@umich.edu 942SN/A /** @} */ 952SN/A 962623SN/A 972SN/A /** 982SN/A * @{ 992SN/A * @name Floating Point Register Interfaces 100180SN/A */ 1012623SN/A 102393SN/A /** Reads a floating point register of single register width. */ 103393SN/A virtual FloatReg readFloatRegOperand(const StaticInst *si, int idx) = 0; 104393SN/A 105393SN/A /** Reads a floating point register in its binary format, instead 106384SN/A * of by value. */ 107384SN/A virtual FloatRegBits readFloatRegOperandBits(const StaticInst *si, 108393SN/A int idx) = 0; 1092623SN/A 110393SN/A /** Sets a floating point register of single width to a value. */ 111393SN/A virtual void setFloatRegOperand(const StaticInst *si, 112393SN/A int idx, FloatReg val) = 0; 113393SN/A 114384SN/A /** Sets the bits of a floating point register of single width 115189SN/A * to a binary value. */ 116189SN/A virtual void setFloatRegOperandBits(const StaticInst *si, 1172623SN/A int idx, FloatRegBits val) = 0; 1182SN/A 119729SN/A /** @} */ 120334SN/A 1212SN/A /** 1222SN/A * @{ 1232SN/A * @name Condition Code Registers 1242SN/A */ 1252SN/A virtual CCReg readCCRegOperand(const StaticInst *si, int idx) = 0; 1262SN/A virtual void setCCRegOperand(const StaticInst *si, int idx, CCReg val) = 0; 1272SN/A /** @} */ 1282SN/A 1292SN/A /** 1302SN/A * @{ 1312SN/A * @name Misc Register Interfaces 1322SN/A */ 1331001SN/A virtual MiscReg readMiscRegOperand(const StaticInst *si, int idx) = 0; 1341001SN/A virtual void setMiscRegOperand(const StaticInst *si, 1351001SN/A int idx, const MiscReg &val) = 0; 1361001SN/A 1371001SN/A /** 1382SN/A * Reads a miscellaneous register, handling any architectural 1392SN/A * side effects due to reading that register. 1402SN/A */ 1412SN/A virtual MiscReg readMiscReg(int misc_reg) = 0; 1422SN/A 1432SN/A /** 1442SN/A * Sets a miscellaneous register, handling any architectural 1452SN/A * side effects due to writing that register. 1462SN/A */ 1472SN/A virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 1482SN/A 1492SN/A /** @} */ 1502SN/A 1512SN/A /** 1522SN/A * @{ 1532SN/A * @name PC Control 1542SN/A */ 1552390SN/A virtual PCState pcState() const = 0; 1562390SN/A virtual void pcState(const PCState &val) = 0; 1572390SN/A /** @} */ 1582390SN/A 1592390SN/A /** 1602390SN/A * @{ 1612390SN/A * @name Memory Interface 1622390SN/A */ 1632390SN/A /** 1642390SN/A * Record the effective address of the instruction. 1652390SN/A * 1662390SN/A * @note Only valid for memory ops. 167385SN/A */ 1682SN/A virtual void setEA(Addr EA) = 0; 1692SN/A /** 1702SN/A * Get the effective address of the instruction. 1712623SN/A * 172334SN/A * @note Only valid for memory ops. 1732361SN/A */ 1742623SN/A virtual Addr getEA() const = 0; 175334SN/A 176334SN/A virtual Fault readMem(Addr addr, uint8_t *data, unsigned int size, 177334SN/A unsigned int flags) = 0; 1782623SN/A 1792SN/A virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr, 180921SN/A unsigned int flags, uint64_t *res) = 0; 1812915Sktlim@umich.edu 1822915Sktlim@umich.edu /** 1832683Sktlim@umich.edu * Sets the number of consecutive store conditional failures. 1842SN/A */ 1852SN/A virtual void setStCondFailures(unsigned int sc_failures) = 0; 1862SN/A 1872623SN/A /** 1882SN/A * Returns the number of consecutive store conditional failures. 189921SN/A */ 1902915Sktlim@umich.edu virtual unsigned int readStCondFailures() const = 0; 1912915Sktlim@umich.edu 1922SN/A /** @} */ 1932SN/A 1942SN/A /** 1952SN/A * @{ 1962SN/A * @name SysCall Emulation Interfaces 1972SN/A */ 1982SN/A 199595SN/A /** 2002623SN/A * Executes a syscall specified by the callnum. 201595SN/A */ 2022390SN/A virtual void syscall(int64_t callnum) = 0; 2031080SN/A 2041080SN/A /** @} */ 2051080SN/A 2061080SN/A /** Returns a pointer to the ThreadContext. */ 2071080SN/A virtual ThreadContext *tcBase() = 0; 2081080SN/A 2091080SN/A /** 2101121SN/A * @{ 2112107SN/A * @name Alpha-Specific Interfaces 2121089SN/A */ 2131089SN/A 2141080SN/A /** 2151080SN/A * Somewhat Alpha-specific function that handles returning from an 2161080SN/A * error or interrupt. 2171080SN/A */ 218595SN/A virtual Fault hwrei() = 0; 2192623SN/A 2202683Sktlim@umich.edu /** 221595SN/A * Check for special simulator handling of specific PAL calls. If 2222090SN/A * return value is false, actual PAL call will be suppressed. 2232683Sktlim@umich.edu */ 2242683Sktlim@umich.edu virtual bool simPalCheck(int palFunc) = 0; 225595SN/A 2262205SN/A /** @} */ 2272205SN/A 2282683Sktlim@umich.edu /** 2292683Sktlim@umich.edu * @{ 230595SN/A * @name ARM-Specific Interfaces 231595SN/A */ 2322390SN/A 2332423SN/A virtual bool readPredicate() = 0; 2342390SN/A virtual void setPredicate(bool val) = 0; 235595SN/A 236595SN/A /** @} */ 237595SN/A 2382623SN/A /** 239595SN/A * @{ 2402390SN/A * @name X86-Specific Interfaces 2411080SN/A */ 242595SN/A 2431080SN/A /** 2441080SN/A * Invalidate a page in the DTLB <i>and</i> ITLB. 245595SN/A */ 2462683Sktlim@umich.edu virtual void demapPage(Addr vaddr, uint64_t asn) = 0; 2471080SN/A virtual void armMonitor(Addr address) = 0; 2481080SN/A virtual bool mwait(PacketPtr pkt) = 0; 2491080SN/A virtual void mwaitAtomic(ThreadContext *tc) = 0; 2501121SN/A virtual AddressMonitor *getAddrMonitor() = 0; 2512107SN/A 2521089SN/A /** @} */ 2531080SN/A 2541089SN/A /** 2551080SN/A * @{ 2561080SN/A * @name MIPS-Specific Interfaces 2571080SN/A */ 258595SN/A 2592683Sktlim@umich.edu#if THE_ISA == MIPS_ISA 2601080SN/A virtual MiscReg readRegOtherThread(int regIdx, 2612090SN/A ThreadID tid = InvalidThreadID) = 0; 2621080SN/A virtual void setRegOtherThread(int regIdx, MiscReg val, 263595SN/A ThreadID tid = InvalidThreadID) = 0; 2642683Sktlim@umich.edu#endif 2652683Sktlim@umich.edu 266595SN/A /** @} */ 2672683Sktlim@umich.edu}; 2681098SN/A 2691098SN/A#endif // __CPU_EXEC_CONTEXT_HH__ 2701098SN/A