cpu_impl.hh revision 8949
1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 * Geoffrey Blake 42 */ 43 44#include <list> 45#include <string> 46 47#include "arch/isa_traits.hh" 48#include "arch/vtophys.hh" 49#include "base/refcnt.hh" 50#include "config/the_isa.hh" 51#include "cpu/base_dyn_inst.hh" 52#include "cpu/exetrace.hh" 53#include "cpu/simple_thread.hh" 54#include "cpu/static_inst.hh" 55#include "cpu/thread_context.hh" 56#include "cpu/checker/cpu.hh" 57#include "debug/Checker.hh" 58#include "sim/full_system.hh" 59#include "sim/sim_object.hh" 60#include "sim/stats.hh" 61 62using namespace std; 63using namespace TheISA; 64 65template <class Impl> 66void 67Checker<Impl>::advancePC(Fault fault) 68{ 69 if (fault != NoFault) { 70 curMacroStaticInst = StaticInst::nullStaticInstPtr; 71 fault->invoke(tc, curStaticInst); 72 predecoder.reset(); 73 } else { 74 if (curStaticInst) { 75 if (curStaticInst->isLastMicroop()) 76 curMacroStaticInst = StaticInst::nullStaticInstPtr; 77 TheISA::PCState pcState = thread->pcState(); 78 TheISA::advancePC(pcState, curStaticInst); 79 thread->pcState(pcState); 80 DPRINTF(Checker, "Advancing PC to %s.\n", thread->pcState()); 81 } 82 } 83} 84////////////////////////////////////////////////// 85 86template <class Impl> 87void 88Checker<Impl>::handlePendingInt() 89{ 90 DPRINTF(Checker, "IRQ detected at PC: %s with %d insts in buffer\n", 91 thread->pcState(), instList.size()); 92 DynInstPtr boundaryInst = NULL; 93 if (!instList.empty()) { 94 // Set the instructions as completed and verify as much as possible. 95 DynInstPtr inst; 96 typename std::list<DynInstPtr>::iterator itr; 97 98 for (itr = instList.begin(); itr != instList.end(); itr++) { 99 (*itr)->setCompleted(); 100 } 101 102 inst = instList.front(); 103 boundaryInst = instList.back(); 104 verify(inst); // verify the instructions 105 inst = NULL; 106 } 107 if ((!boundaryInst && curMacroStaticInst && 108 curStaticInst->isDelayedCommit() && 109 !curStaticInst->isLastMicroop()) || 110 (boundaryInst && boundaryInst->isDelayedCommit() && 111 !boundaryInst->isLastMicroop())) { 112 panic("%lli: Trying to take an interrupt in middle of " 113 "a non-interuptable instruction!", curTick()); 114 } 115 boundaryInst = NULL; 116 predecoder.reset(); 117 curMacroStaticInst = StaticInst::nullStaticInstPtr; 118} 119 120template <class Impl> 121void 122Checker<Impl>::verify(DynInstPtr &completed_inst) 123{ 124 DynInstPtr inst; 125 126 // Make sure serializing instructions are actually 127 // seen as serializing to commit. instList should be 128 // empty in these cases. 129 if ((completed_inst->isSerializing() || 130 completed_inst->isSerializeBefore()) && 131 (!instList.empty() ? 132 (instList.front()->seqNum != completed_inst->seqNum) : 0)) { 133 panic("%lli: Instruction sn:%lli at PC %s is serializing before but is" 134 " entering instList with other instructions\n", curTick(), 135 completed_inst->seqNum, completed_inst->pcState()); 136 } 137 138 // Either check this instruction, or add it to a list of 139 // instructions waiting to be checked. Instructions must be 140 // checked in program order, so if a store has committed yet not 141 // completed, there may be some instructions that are waiting 142 // behind it that have completed and must be checked. 143 if (!instList.empty()) { 144 if (youngestSN < completed_inst->seqNum) { 145 DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%s to list\n", 146 completed_inst->seqNum, completed_inst->pcState()); 147 instList.push_back(completed_inst); 148 youngestSN = completed_inst->seqNum; 149 } 150 151 if (!instList.front()->isCompleted()) { 152 return; 153 } else { 154 inst = instList.front(); 155 instList.pop_front(); 156 } 157 } else { 158 if (!completed_inst->isCompleted()) { 159 if (youngestSN < completed_inst->seqNum) { 160 DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%s to list\n", 161 completed_inst->seqNum, completed_inst->pcState()); 162 instList.push_back(completed_inst); 163 youngestSN = completed_inst->seqNum; 164 } 165 return; 166 } else { 167 if (youngestSN < completed_inst->seqNum) { 168 inst = completed_inst; 169 youngestSN = completed_inst->seqNum; 170 } else { 171 return; 172 } 173 } 174 } 175 176 // Make sure a serializing instruction is actually seen as 177 // serializing. instList should be empty here 178 if (inst->isSerializeAfter() && !instList.empty()) { 179 panic("%lli: Instruction sn:%lli at PC %s is serializing after but is" 180 " exiting instList with other instructions\n", curTick(), 181 completed_inst->seqNum, completed_inst->pcState()); 182 } 183 unverifiedInst = inst; 184 inst = NULL; 185 186 // Try to check all instructions that are completed, ending if we 187 // run out of instructions to check or if an instruction is not 188 // yet completed. 189 while (1) { 190 DPRINTF(Checker, "Processing instruction [sn:%lli] PC:%s.\n", 191 unverifiedInst->seqNum, unverifiedInst->pcState()); 192 unverifiedReq = NULL; 193 unverifiedReq = unverifiedInst->reqToVerify; 194 unverifiedMemData = unverifiedInst->memData; 195 // Make sure results queue is empty 196 while (!result.empty()) { 197 result.pop(); 198 } 199 numCycles++; 200 201 Fault fault = NoFault; 202 203 // maintain $r0 semantics 204 thread->setIntReg(ZeroReg, 0); 205#if THE_ISA == ALPHA_ISA 206 thread->setFloatReg(ZeroReg, 0.0); 207#endif 208 209 // Check if any recent PC changes match up with anything we 210 // expect to happen. This is mostly to check if traps or 211 // PC-based events have occurred in both the checker and CPU. 212 if (changedPC) { 213 DPRINTF(Checker, "Changed PC recently to %s\n", 214 thread->pcState()); 215 if (willChangePC) { 216 if (newPCState == thread->pcState()) { 217 DPRINTF(Checker, "Changed PC matches expected PC\n"); 218 } else { 219 warn("%lli: Changed PC does not match expected PC, " 220 "changed: %s, expected: %s", 221 curTick(), thread->pcState(), newPCState); 222 CheckerCPU::handleError(); 223 } 224 willChangePC = false; 225 } 226 changedPC = false; 227 } 228 if (changedNextPC) { 229 DPRINTF(Checker, "Changed NextPC recently to %#x\n", 230 thread->nextInstAddr()); 231 changedNextPC = false; 232 } 233 234 // Try to fetch the instruction 235 uint64_t fetchOffset = 0; 236 bool fetchDone = false; 237 238 while (!fetchDone) { 239 Addr fetch_PC = thread->instAddr(); 240 fetch_PC = (fetch_PC & PCMask) + fetchOffset; 241 242 // If not in the middle of a macro instruction 243 if (!curMacroStaticInst) { 244 // set up memory request for instruction fetch 245 memReq = new Request(unverifiedInst->threadNumber, fetch_PC, 246 sizeof(MachInst), 247 0, 248 masterId, 249 fetch_PC, thread->contextId(), 250 unverifiedInst->threadNumber); 251 memReq->setVirt(0, fetch_PC, sizeof(MachInst), 252 Request::INST_FETCH, masterId, thread->instAddr()); 253 254 255 fault = itb->translateFunctional(memReq, tc, BaseTLB::Execute); 256 257 if (fault != NoFault) { 258 if (unverifiedInst->getFault() == NoFault) { 259 // In this case the instruction was not a dummy 260 // instruction carrying an ITB fault. In the single 261 // threaded case the ITB should still be able to 262 // translate this instruction; in the SMT case it's 263 // possible that its ITB entry was kicked out. 264 warn("%lli: Instruction PC %s was not found in the " 265 "ITB!", curTick(), thread->pcState()); 266 handleError(unverifiedInst); 267 268 // go to the next instruction 269 advancePC(NoFault); 270 271 // Give up on an ITB fault.. 272 delete memReq; 273 unverifiedInst = NULL; 274 return; 275 } else { 276 // The instruction is carrying an ITB fault. Handle 277 // the fault and see if our results match the CPU on 278 // the next tick(). 279 fault = unverifiedInst->getFault(); 280 delete memReq; 281 break; 282 } 283 } else { 284 PacketPtr pkt = new Packet(memReq, MemCmd::ReadReq); 285 286 pkt->dataStatic(&machInst); 287 icachePort->sendFunctional(pkt); 288 machInst = gtoh(machInst); 289 290 delete memReq; 291 delete pkt; 292 } 293 } 294 295 if (fault == NoFault) { 296 TheISA::PCState pcState = thread->pcState(); 297 298 if (isRomMicroPC(pcState.microPC())) { 299 fetchDone = true; 300 curStaticInst = 301 microcodeRom.fetchMicroop(pcState.microPC(), NULL); 302 } else if (!curMacroStaticInst) { 303 //We're not in the middle of a macro instruction 304 StaticInstPtr instPtr = NULL; 305 306 //Predecode, ie bundle up an ExtMachInst 307 predecoder.setTC(thread->getTC()); 308 //If more fetch data is needed, pass it in. 309 Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset; 310 predecoder.moreBytes(pcState, fetchPC, machInst); 311 312 //If an instruction is ready, decode it. 313 //Otherwise, we'll have to fetch beyond the 314 //MachInst at the current pc. 315 if (predecoder.extMachInstReady()) { 316 fetchDone = true; 317 ExtMachInst newMachInst = 318 predecoder.getExtMachInst(pcState); 319 thread->pcState(pcState); 320 instPtr = thread->decoder.decode(newMachInst, 321 pcState.instAddr()); 322#if THE_ISA != X86_ISA 323 machInst = newMachInst; 324#endif 325 } else { 326 fetchDone = false; 327 fetchOffset += sizeof(TheISA::MachInst); 328 } 329 330 //If we decoded an instruction and it's microcoded, 331 //start pulling out micro ops 332 if (instPtr && instPtr->isMacroop()) { 333 curMacroStaticInst = instPtr; 334 curStaticInst = 335 instPtr->fetchMicroop(pcState.microPC()); 336 } else { 337 curStaticInst = instPtr; 338 } 339 } else { 340 // Read the next micro op from the macro-op 341 curStaticInst = 342 curMacroStaticInst->fetchMicroop(pcState.microPC()); 343 fetchDone = true; 344 } 345 } 346 } 347 // reset predecoder on Checker 348 predecoder.reset(); 349 350 // Check Checker and CPU get same instruction, and record 351 // any faults the CPU may have had. 352 Fault unverifiedFault; 353 if (fault == NoFault) { 354 unverifiedFault = unverifiedInst->getFault(); 355 356 // Checks that the instruction matches what we expected it to be. 357 // Checks both the machine instruction and the PC. 358 validateInst(unverifiedInst); 359 } 360 361 // keep an instruction count 362 numInst++; 363 364 365 // Either the instruction was a fault and we should process the fault, 366 // or we should just go ahead execute the instruction. This assumes 367 // that the instruction is properly marked as a fault. 368 if (fault == NoFault) { 369 // Execute Checker instruction and trace 370 if (!unverifiedInst->isUnverifiable()) { 371 Trace::InstRecord *traceData = tracer->getInstRecord(curTick(), 372 tc, 373 curStaticInst, 374 pcState(), 375 curMacroStaticInst); 376 fault = curStaticInst->execute(this, traceData); 377 if (traceData) { 378 traceData->dump(); 379 delete traceData; 380 } 381 } 382 383 if (fault == NoFault && unverifiedFault == NoFault) { 384 thread->funcExeInst++; 385 // Checks to make sure instrution results are correct. 386 validateExecution(unverifiedInst); 387 388 if (curStaticInst->isLoad()) { 389 ++numLoad; 390 } 391 } else if (fault != NoFault && unverifiedFault == NoFault) { 392 panic("%lli: sn: %lli at PC: %s took a fault in checker " 393 "but not in driver CPU\n", curTick(), 394 unverifiedInst->seqNum, unverifiedInst->pcState()); 395 } else if (fault == NoFault && unverifiedFault != NoFault) { 396 panic("%lli: sn: %lli at PC: %s took a fault in driver " 397 "CPU but not in checker\n", curTick(), 398 unverifiedInst->seqNum, unverifiedInst->pcState()); 399 } 400 } 401 402 // Take any faults here 403 if (fault != NoFault) { 404 if (FullSystem) { 405 fault->invoke(tc, curStaticInst); 406 willChangePC = true; 407 newPCState = thread->pcState(); 408 DPRINTF(Checker, "Fault, PC is now %s\n", newPCState); 409 curMacroStaticInst = StaticInst::nullStaticInstPtr; 410 } 411 } else { 412 advancePC(fault); 413 } 414 415 if (FullSystem) { 416 // @todo: Determine if these should happen only if the 417 // instruction hasn't faulted. In the SimpleCPU case this may 418 // not be true, but in the O3 or Ozone case this may be true. 419 Addr oldpc; 420 int count = 0; 421 do { 422 oldpc = thread->instAddr(); 423 system->pcEventQueue.service(tc); 424 count++; 425 } while (oldpc != thread->instAddr()); 426 if (count > 1) { 427 willChangePC = true; 428 newPCState = thread->pcState(); 429 DPRINTF(Checker, "PC Event, PC is now %s\n", newPCState); 430 } 431 } 432 433 // @todo: Optionally can check all registers. (Or just those 434 // that have been modified). 435 validateState(); 436 437 // Continue verifying instructions if there's another completed 438 // instruction waiting to be verified. 439 if (instList.empty()) { 440 break; 441 } else if (instList.front()->isCompleted()) { 442 unverifiedInst = NULL; 443 unverifiedInst = instList.front(); 444 instList.pop_front(); 445 } else { 446 break; 447 } 448 } 449 unverifiedInst = NULL; 450} 451 452template <class Impl> 453void 454Checker<Impl>::switchOut() 455{ 456 instList.clear(); 457} 458 459template <class Impl> 460void 461Checker<Impl>::takeOverFrom(BaseCPU *oldCPU) 462{ 463} 464 465template <class Impl> 466void 467Checker<Impl>::validateInst(DynInstPtr &inst) 468{ 469 if (inst->instAddr() != thread->instAddr()) { 470 warn("%lli: PCs do not match! Inst: %s, checker: %s", 471 curTick(), inst->pcState(), thread->pcState()); 472 if (changedPC) { 473 warn("%lli: Changed PCs recently, may not be an error", 474 curTick()); 475 } else { 476 handleError(inst); 477 } 478 } 479 480 481 MachInst mi; 482#if THE_ISA != X86_ISA 483 mi = static_cast<MachInst>(inst->staticInst->machInst); 484#endif 485 486 if (mi != machInst) { 487 panic("%lli: Binary instructions do not match! Inst: %#x, " 488 "checker: %#x", 489 curTick(), mi, machInst); 490 handleError(inst); 491 } 492} 493 494template <class Impl> 495void 496Checker<Impl>::validateExecution(DynInstPtr &inst) 497{ 498 uint64_t checker_val; 499 uint64_t inst_val; 500 int idx = -1; 501 bool result_mismatch = false; 502 503 if (inst->isUnverifiable()) { 504 // Unverifiable instructions assume they were executed 505 // properly by the CPU. Grab the result from the 506 // instruction and write it to the register. 507 copyResult(inst, 0, idx); 508 } else if (inst->numDestRegs() > 0 && !result.empty()) { 509 DPRINTF(Checker, "Dest regs %d, number of checker dest regs %d\n", 510 inst->numDestRegs(), result.size()); 511 for (int i = 0; i < inst->numDestRegs() && !result.empty(); i++) { 512 result.front().get(checker_val); 513 result.pop(); 514 inst_val = 0; 515 inst->template popResult<uint64_t>(inst_val); 516 if (checker_val != inst_val) { 517 result_mismatch = true; 518 idx = i; 519 break; 520 } 521 } 522 } // Checker CPU checks all the saved results in the dyninst passed by 523 // the cpu model being checked against the saved results present in 524 // the static inst executed in the Checker. Sometimes the number 525 // of saved results differs between the dyninst and static inst, but 526 // this is ok and not a bug. May be worthwhile to try and correct this. 527 528 if (result_mismatch) { 529 warn("%lli: Instruction results do not match! (Values may not " 530 "actually be integers) Inst: %#x, checker: %#x", 531 curTick(), inst_val, checker_val); 532 533 // It's useful to verify load values from memory, but in MP 534 // systems the value obtained at execute may be different than 535 // the value obtained at completion. Similarly DMA can 536 // present the same problem on even UP systems. Thus there is 537 // the option to only warn on loads having a result error. 538 // The load/store queue in Detailed CPU can also cause problems 539 // if load/store forwarding is allowed. 540 if (inst->isLoad() && warnOnlyOnLoadError) { 541 copyResult(inst, inst_val, idx); 542 } else { 543 handleError(inst); 544 } 545 } 546 547 if (inst->nextInstAddr() != thread->nextInstAddr()) { 548 warn("%lli: Instruction next PCs do not match! Inst: %#x, " 549 "checker: %#x", 550 curTick(), inst->nextInstAddr(), thread->nextInstAddr()); 551 handleError(inst); 552 } 553 554 // Checking side effect registers can be difficult if they are not 555 // checked simultaneously with the execution of the instruction. 556 // This is because other valid instructions may have modified 557 // these registers in the meantime, and their values are not 558 // stored within the DynInst. 559 while (!miscRegIdxs.empty()) { 560 int misc_reg_idx = miscRegIdxs.front(); 561 miscRegIdxs.pop(); 562 563 if (inst->tcBase()->readMiscRegNoEffect(misc_reg_idx) != 564 thread->readMiscRegNoEffect(misc_reg_idx)) { 565 warn("%lli: Misc reg idx %i (side effect) does not match! " 566 "Inst: %#x, checker: %#x", 567 curTick(), misc_reg_idx, 568 inst->tcBase()->readMiscRegNoEffect(misc_reg_idx), 569 thread->readMiscRegNoEffect(misc_reg_idx)); 570 handleError(inst); 571 } 572 } 573} 574 575 576// This function is weird, if it is called it means the Checker and 577// O3 have diverged, so panic is called for now. It may be useful 578// to resynch states and continue if the divergence is a false positive 579template <class Impl> 580void 581Checker<Impl>::validateState() 582{ 583 if (updateThisCycle) { 584 // Change this back to warn if divergences end up being false positives 585 panic("%lli: Instruction PC %#x results didn't match up, copying all " 586 "registers from main CPU", curTick(), unverifiedInst->instAddr()); 587 588 // Terribly convoluted way to make sure O3 model does not implode 589 bool inSyscall = unverifiedInst->thread->inSyscall; 590 unverifiedInst->thread->inSyscall = true; 591 592 // Heavy-weight copying of all registers 593 thread->copyArchRegs(unverifiedInst->tcBase()); 594 unverifiedInst->thread->inSyscall = inSyscall; 595 596 // Set curStaticInst to unverifiedInst->staticInst 597 curStaticInst = unverifiedInst->staticInst; 598 // Also advance the PC. Hopefully no PC-based events happened. 599 advancePC(NoFault); 600 updateThisCycle = false; 601 } 602} 603 604template <class Impl> 605void 606Checker<Impl>::copyResult(DynInstPtr &inst, uint64_t mismatch_val, 607 int start_idx) 608{ 609 // We've already popped one dest off the queue, 610 // so do the fix-up then start with the next dest reg; 611 if (start_idx >= 0) { 612 RegIndex idx = inst->destRegIdx(start_idx); 613 if (idx < TheISA::FP_Base_DepTag) { 614 thread->setIntReg(idx, mismatch_val); 615 } else if (idx < TheISA::Ctrl_Base_DepTag) { 616 thread->setFloatRegBits(idx, mismatch_val); 617 } else if (idx < TheISA::Max_DepTag) { 618 thread->setMiscReg(idx - TheISA::Ctrl_Base_DepTag, 619 mismatch_val); 620 } 621 } 622 start_idx++; 623 uint64_t res = 0; 624 for (int i = start_idx; i < inst->numDestRegs(); i++) { 625 RegIndex idx = inst->destRegIdx(i); 626 inst->template popResult<uint64_t>(res); 627 if (idx < TheISA::FP_Base_DepTag) { 628 thread->setIntReg(idx, res); 629 } else if (idx < TheISA::Ctrl_Base_DepTag) { 630 thread->setFloatRegBits(idx, res); 631 } else if (idx < TheISA::Max_DepTag) { 632 // Try to get the proper misc register index for ARM here... 633 thread->setMiscReg(idx - TheISA::Ctrl_Base_DepTag, res); 634 } // else Register is out of range... 635 } 636} 637 638template <class Impl> 639void 640Checker<Impl>::dumpAndExit(DynInstPtr &inst) 641{ 642 cprintf("Error detected, instruction information:\n"); 643 cprintf("PC:%s, nextPC:%#x\n[sn:%lli]\n[tid:%i]\n" 644 "Completed:%i\n", 645 inst->pcState(), 646 inst->nextInstAddr(), 647 inst->seqNum, 648 inst->threadNumber, 649 inst->isCompleted()); 650 inst->dump(); 651 CheckerCPU::dumpAndExit(); 652} 653 654template <class Impl> 655void 656Checker<Impl>::dumpInsts() 657{ 658 int num = 0; 659 660 InstListIt inst_list_it = --(instList.end()); 661 662 cprintf("Inst list size: %i\n", instList.size()); 663 664 while (inst_list_it != instList.end()) 665 { 666 cprintf("Instruction:%i\n", 667 num); 668 669 cprintf("PC:%s\n[sn:%lli]\n[tid:%i]\n" 670 "Completed:%i\n", 671 (*inst_list_it)->pcState(), 672 (*inst_list_it)->seqNum, 673 (*inst_list_it)->threadNumber, 674 (*inst_list_it)->isCompleted()); 675 676 cprintf("\n"); 677 678 inst_list_it--; 679 ++num; 680 } 681 682} 683