cpu_impl.hh revision 2838
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include <list>
32#include <string>
33
34#include "base/refcnt.hh"
35#include "cpu/base_dyn_inst.hh"
36#include "cpu/checker/cpu.hh"
37#include "cpu/simple_thread.hh"
38#include "cpu/thread_context.hh"
39#include "cpu/static_inst.hh"
40#include "mem/packet_impl.hh"
41#include "sim/byteswap.hh"
42#include "sim/sim_object.hh"
43#include "sim/stats.hh"
44
45#if FULL_SYSTEM
46#include "arch/vtophys.hh"
47#endif // FULL_SYSTEM
48
49using namespace std;
50//The CheckerCPU does alpha only
51using namespace AlphaISA;
52
53template <class DynInstPtr>
54void
55Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
56{
57    DynInstPtr inst;
58
59    // Either check this instruction, or add it to a list of
60    // instructions waiting to be checked.  Instructions must be
61    // checked in program order, so if a store has committed yet not
62    // completed, there may be some instructions that are waiting
63    // behind it that have completed and must be checked.
64    if (!instList.empty()) {
65        if (youngestSN < completed_inst->seqNum) {
66            DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%#x to list.\n",
67                    completed_inst->seqNum, completed_inst->readPC());
68            instList.push_back(completed_inst);
69            youngestSN = completed_inst->seqNum;
70        }
71
72        if (!instList.front()->isCompleted()) {
73            return;
74        } else {
75            inst = instList.front();
76            instList.pop_front();
77        }
78    } else {
79        if (!completed_inst->isCompleted()) {
80            if (youngestSN < completed_inst->seqNum) {
81                DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%#x to list.\n",
82                        completed_inst->seqNum, completed_inst->readPC());
83                instList.push_back(completed_inst);
84                youngestSN = completed_inst->seqNum;
85            }
86            return;
87        } else {
88            if (youngestSN < completed_inst->seqNum) {
89                inst = completed_inst;
90                youngestSN = completed_inst->seqNum;
91            } else {
92                return;
93            }
94        }
95    }
96
97    // Try to check all instructions that are completed, ending if we
98    // run out of instructions to check or if an instruction is not
99    // yet completed.
100    while (1) {
101        DPRINTF(Checker, "Processing instruction [sn:%lli] PC:%#x.\n",
102                inst->seqNum, inst->readPC());
103        unverifiedResult.integer = inst->readIntResult();
104        unverifiedReq = inst->req;
105        unverifiedMemData = inst->memData;
106        numCycles++;
107
108        Fault fault = NoFault;
109
110        // maintain $r0 semantics
111        thread->setIntReg(ZeroReg, 0);
112#ifdef TARGET_ALPHA
113        thread->setFloatRegDouble(ZeroReg, 0.0);
114#endif // TARGET_ALPHA
115
116        // Check if any recent PC changes match up with anything we
117        // expect to happen.  This is mostly to check if traps or
118        // PC-based events have occurred in both the checker and CPU.
119        if (changedPC) {
120            DPRINTF(Checker, "Changed PC recently to %#x\n",
121                    thread->readPC());
122            if (willChangePC) {
123                if (newPC == thread->readPC()) {
124                    DPRINTF(Checker, "Changed PC matches expected PC\n");
125                } else {
126                    warn("%lli: Changed PC does not match expected PC, "
127                         "changed: %#x, expected: %#x",
128                         curTick, thread->readPC(), newPC);
129                    CheckerCPU::handleError();
130                }
131                willChangePC = false;
132            }
133            changedPC = false;
134        }
135        if (changedNextPC) {
136            DPRINTF(Checker, "Changed NextPC recently to %#x\n",
137                    thread->readNextPC());
138            changedNextPC = false;
139        }
140
141        // Try to fetch the instruction
142
143#if FULL_SYSTEM
144#define IFETCH_FLAGS(pc)	((pc) & 1) ? PHYSICAL : 0
145#else
146#define IFETCH_FLAGS(pc)	0
147#endif
148
149        uint64_t fetch_PC = thread->readPC() & ~3;
150
151        // set up memory request for instruction fetch
152        memReq = new Request(inst->threadNumber, fetch_PC,
153                             sizeof(uint32_t),
154                             IFETCH_FLAGS(thread->readPC()),
155                             fetch_PC, thread->readCpuId(), inst->threadNumber);
156
157        bool succeeded = translateInstReq(memReq);
158
159        if (!succeeded) {
160            if (inst->getFault() == NoFault) {
161                // In this case the instruction was not a dummy
162                // instruction carrying an ITB fault.  In the single
163                // threaded case the ITB should still be able to
164                // translate this instruction; in the SMT case it's
165                // possible that its ITB entry was kicked out.
166                warn("%lli: Instruction PC %#x was not found in the ITB!",
167                     curTick, thread->readPC());
168                handleError(inst);
169
170                // go to the next instruction
171                thread->setPC(thread->readNextPC());
172                thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
173
174                return;
175            } else {
176                // The instruction is carrying an ITB fault.  Handle
177                // the fault and see if our results match the CPU on
178                // the next tick().
179                fault = inst->getFault();
180            }
181        }
182
183        if (fault == NoFault) {
184            Packet *pkt = new Packet(memReq, Packet::ReadReq,
185                                     Packet::Broadcast);
186
187            pkt->dataStatic(&machInst);
188
189            icachePort->sendFunctional(pkt);
190
191            delete pkt;
192
193            // keep an instruction count
194            numInst++;
195
196            // decode the instruction
197            machInst = gtoh(machInst);
198            // Checks that the instruction matches what we expected it to be.
199            // Checks both the machine instruction and the PC.
200            validateInst(inst);
201
202            curStaticInst = StaticInst::decode(makeExtMI(machInst,
203                                                         thread->readPC()));
204
205#if FULL_SYSTEM
206            thread->setInst(machInst);
207#endif // FULL_SYSTEM
208
209            fault = inst->getFault();
210        }
211
212        // Discard fetch's memReq.
213        delete memReq;
214        memReq = NULL;
215
216        // Either the instruction was a fault and we should process the fault,
217        // or we should just go ahead execute the instruction.  This assumes
218        // that the instruction is properly marked as a fault.
219        if (fault == NoFault) {
220
221            thread->funcExeInst++;
222
223            fault = curStaticInst->execute(this, NULL);
224
225            // Checks to make sure instrution results are correct.
226            validateExecution(inst);
227
228            if (curStaticInst->isLoad()) {
229                ++numLoad;
230            }
231        }
232
233        if (fault != NoFault) {
234#if FULL_SYSTEM
235            fault->invoke(tc);
236            willChangePC = true;
237            newPC = thread->readPC();
238            DPRINTF(Checker, "Fault, PC is now %#x\n", newPC);
239#endif
240        } else {
241#if THE_ISA != MIPS_ISA
242            // go to the next instruction
243            thread->setPC(thread->readNextPC());
244            thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
245#else
246            // go to the next instruction
247            thread->setPC(thread->readNextPC());
248            thread->setNextPC(thread->readNextNPC());
249            thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
250#endif
251
252        }
253
254#if FULL_SYSTEM
255        // @todo: Determine if these should happen only if the
256        // instruction hasn't faulted.  In the SimpleCPU case this may
257        // not be true, but in the O3 or Ozone case this may be true.
258        Addr oldpc;
259        int count = 0;
260        do {
261            oldpc = thread->readPC();
262            system->pcEventQueue.service(tc);
263            count++;
264        } while (oldpc != thread->readPC());
265        if (count > 1) {
266            willChangePC = true;
267            newPC = thread->readPC();
268            DPRINTF(Checker, "PC Event, PC is now %#x\n", newPC);
269        }
270#endif
271
272        // @todo:  Optionally can check all registers. (Or just those
273        // that have been modified).
274        validateState();
275
276        if (memReq) {
277            delete memReq;
278            memReq = NULL;
279        }
280
281        // Continue verifying instructions if there's another completed
282        // instruction waiting to be verified.
283        if (instList.empty()) {
284            break;
285        } else if (instList.front()->isCompleted()) {
286            inst = instList.front();
287            instList.pop_front();
288        } else {
289            break;
290        }
291    }
292}
293
294template <class DynInstPtr>
295void
296Checker<DynInstPtr>::switchOut(Sampler *s)
297{
298    instList.clear();
299}
300
301template <class DynInstPtr>
302void
303Checker<DynInstPtr>::takeOverFrom(BaseCPU *oldCPU)
304{
305}
306
307template <class DynInstPtr>
308void
309Checker<DynInstPtr>::validateInst(DynInstPtr &inst)
310{
311    if (inst->readPC() != thread->readPC()) {
312        warn("%lli: PCs do not match! Inst: %#x, checker: %#x",
313             curTick, inst->readPC(), thread->readPC());
314        if (changedPC) {
315            warn("%lli: Changed PCs recently, may not be an error",
316                 curTick);
317        } else {
318            handleError(inst);
319        }
320    }
321
322    MachInst mi = static_cast<MachInst>(inst->staticInst->machInst);
323
324    if (mi != machInst) {
325        warn("%lli: Binary instructions do not match! Inst: %#x, "
326             "checker: %#x",
327             curTick, mi, machInst);
328        handleError(inst);
329    }
330}
331
332template <class DynInstPtr>
333void
334Checker<DynInstPtr>::validateExecution(DynInstPtr &inst)
335{
336    bool result_mismatch = false;
337    if (inst->numDestRegs()) {
338        // @todo: Support more destination registers.
339        if (inst->isUnverifiable()) {
340            // Unverifiable instructions assume they were executed
341            // properly by the CPU. Grab the result from the
342            // instruction and write it to the register.
343            copyResult(inst);
344        } else if (result.integer != inst->readIntResult()) {
345            result_mismatch = true;
346        }
347    }
348
349    if (result_mismatch) {
350        warn("%lli: Instruction results do not match! (Values may not "
351             "actually be integers) Inst: %#x, checker: %#x",
352             curTick, inst->readIntResult(), result.integer);
353
354        // It's useful to verify load values from memory, but in MP
355        // systems the value obtained at execute may be different than
356        // the value obtained at completion.  Similarly DMA can
357        // present the same problem on even UP systems.  Thus there is
358        // the option to only warn on loads having a result error.
359        if (inst->isLoad() && warnOnlyOnLoadError) {
360            copyResult(inst);
361        } else {
362            handleError(inst);
363        }
364    }
365
366    if (inst->readNextPC() != thread->readNextPC()) {
367        warn("%lli: Instruction next PCs do not match! Inst: %#x, "
368             "checker: %#x",
369             curTick, inst->readNextPC(), thread->readNextPC());
370        handleError(inst);
371    }
372
373    // Checking side effect registers can be difficult if they are not
374    // checked simultaneously with the execution of the instruction.
375    // This is because other valid instructions may have modified
376    // these registers in the meantime, and their values are not
377    // stored within the DynInst.
378    while (!miscRegIdxs.empty()) {
379        int misc_reg_idx = miscRegIdxs.front();
380        miscRegIdxs.pop();
381
382        if (inst->tcBase()->readMiscReg(misc_reg_idx) !=
383            thread->readMiscReg(misc_reg_idx)) {
384            warn("%lli: Misc reg idx %i (side effect) does not match! "
385                 "Inst: %#x, checker: %#x",
386                 curTick, misc_reg_idx,
387                 inst->tcBase()->readMiscReg(misc_reg_idx),
388                 thread->readMiscReg(misc_reg_idx));
389            handleError(inst);
390        }
391    }
392}
393
394template <class DynInstPtr>
395void
396Checker<DynInstPtr>::validateState()
397{
398}
399
400template <class DynInstPtr>
401void
402Checker<DynInstPtr>::copyResult(DynInstPtr &inst)
403{
404    RegIndex idx = inst->destRegIdx(0);
405    if (idx < TheISA::FP_Base_DepTag) {
406        thread->setIntReg(idx, inst->readIntResult());
407    } else if (idx < TheISA::Fpcr_DepTag) {
408        thread->setFloatRegBits(idx, inst->readIntResult());
409    } else {
410        thread->setMiscReg(idx, inst->readIntResult());
411    }
412}
413
414template <class DynInstPtr>
415void
416Checker<DynInstPtr>::dumpAndExit(DynInstPtr &inst)
417{
418    cprintf("Error detected, instruction information:\n");
419    cprintf("PC:%#x, nextPC:%#x\n[sn:%lli]\n[tid:%i]\n"
420            "Completed:%i\n",
421            inst->readPC(),
422            inst->readNextPC(),
423            inst->seqNum,
424            inst->threadNumber,
425            inst->isCompleted());
426    inst->dump();
427    CheckerCPU::dumpAndExit();
428}
429
430template <class DynInstPtr>
431void
432Checker<DynInstPtr>::dumpInsts()
433{
434    int num = 0;
435
436    InstListIt inst_list_it = --(instList.end());
437
438    cprintf("Inst list size: %i\n", instList.size());
439
440    while (inst_list_it != instList.end())
441    {
442        cprintf("Instruction:%i\n",
443                num);
444
445        cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
446                "Completed:%i\n",
447                (*inst_list_it)->readPC(),
448                (*inst_list_it)->seqNum,
449                (*inst_list_it)->threadNumber,
450                (*inst_list_it)->isCompleted());
451
452        cprintf("\n");
453
454        inst_list_it--;
455        ++num;
456    }
457
458}
459