cpu_impl.hh revision 4172
12315SN/A/* 22332SN/A * Copyright (c) 2006 The Regents of The University of Michigan 32315SN/A * All rights reserved. 42315SN/A * 52315SN/A * Redistribution and use in source and binary forms, with or without 62315SN/A * modification, are permitted provided that the following conditions are 72315SN/A * met: redistributions of source code must retain the above copyright 82315SN/A * notice, this list of conditions and the following disclaimer; 92315SN/A * redistributions in binary form must reproduce the above copyright 102315SN/A * notice, this list of conditions and the following disclaimer in the 112315SN/A * documentation and/or other materials provided with the distribution; 122315SN/A * neither the name of the copyright holders nor the names of its 132315SN/A * contributors may be used to endorse or promote products derived from 142315SN/A * this software without specific prior written permission. 152315SN/A * 162315SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172315SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182315SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192315SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202315SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212315SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222315SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232315SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242315SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252315SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262315SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272689SN/A * 282689SN/A * Authors: Kevin Lim 292315SN/A */ 302315SN/A 312315SN/A#include <list> 322315SN/A#include <string> 332315SN/A 342315SN/A#include "base/refcnt.hh" 352315SN/A#include "cpu/base_dyn_inst.hh" 362315SN/A#include "cpu/checker/cpu.hh" 372683SN/A#include "cpu/simple_thread.hh" 382680SN/A#include "cpu/thread_context.hh" 392315SN/A#include "cpu/static_inst.hh" 402315SN/A#include "sim/sim_object.hh" 412315SN/A#include "sim/stats.hh" 422315SN/A 432315SN/A#if FULL_SYSTEM 442315SN/A#include "arch/vtophys.hh" 452315SN/A#endif // FULL_SYSTEM 462315SN/A 472315SN/Ausing namespace std; 482315SN/A//The CheckerCPU does alpha only 492315SN/Ausing namespace AlphaISA; 502315SN/A 512315SN/Atemplate <class DynInstPtr> 522315SN/Avoid 532732SN/AChecker<DynInstPtr>::verify(DynInstPtr &completed_inst) 542315SN/A{ 552315SN/A DynInstPtr inst; 562315SN/A 572332SN/A // Either check this instruction, or add it to a list of 582332SN/A // instructions waiting to be checked. Instructions must be 592332SN/A // checked in program order, so if a store has committed yet not 602332SN/A // completed, there may be some instructions that are waiting 612332SN/A // behind it that have completed and must be checked. 622315SN/A if (!instList.empty()) { 632315SN/A if (youngestSN < completed_inst->seqNum) { 642315SN/A DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%#x to list.\n", 652315SN/A completed_inst->seqNum, completed_inst->readPC()); 662315SN/A instList.push_back(completed_inst); 672315SN/A youngestSN = completed_inst->seqNum; 682315SN/A } 692315SN/A 702315SN/A if (!instList.front()->isCompleted()) { 712315SN/A return; 722315SN/A } else { 732315SN/A inst = instList.front(); 742315SN/A instList.pop_front(); 752315SN/A } 762315SN/A } else { 772315SN/A if (!completed_inst->isCompleted()) { 782315SN/A if (youngestSN < completed_inst->seqNum) { 792315SN/A DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%#x to list.\n", 802315SN/A completed_inst->seqNum, completed_inst->readPC()); 812315SN/A instList.push_back(completed_inst); 822315SN/A youngestSN = completed_inst->seqNum; 832315SN/A } 842315SN/A return; 852315SN/A } else { 862315SN/A if (youngestSN < completed_inst->seqNum) { 872315SN/A inst = completed_inst; 882315SN/A youngestSN = completed_inst->seqNum; 892315SN/A } else { 902315SN/A return; 912315SN/A } 922315SN/A } 932315SN/A } 942315SN/A 952354SN/A unverifiedInst = inst; 962354SN/A 972332SN/A // Try to check all instructions that are completed, ending if we 982332SN/A // run out of instructions to check or if an instruction is not 992332SN/A // yet completed. 1002315SN/A while (1) { 1012315SN/A DPRINTF(Checker, "Processing instruction [sn:%lli] PC:%#x.\n", 1022315SN/A inst->seqNum, inst->readPC()); 1032315SN/A unverifiedResult.integer = inst->readIntResult(); 1042315SN/A unverifiedReq = inst->req; 1052679SN/A unverifiedMemData = inst->memData; 1062315SN/A numCycles++; 1072315SN/A 1082315SN/A Fault fault = NoFault; 1092315SN/A 1102315SN/A // maintain $r0 semantics 1112683SN/A thread->setIntReg(ZeroReg, 0); 1122315SN/A#ifdef TARGET_ALPHA 1132683SN/A thread->setFloatRegDouble(ZeroReg, 0.0); 1142315SN/A#endif // TARGET_ALPHA 1152315SN/A 1162332SN/A // Check if any recent PC changes match up with anything we 1172332SN/A // expect to happen. This is mostly to check if traps or 1182332SN/A // PC-based events have occurred in both the checker and CPU. 1192315SN/A if (changedPC) { 1202315SN/A DPRINTF(Checker, "Changed PC recently to %#x\n", 1212683SN/A thread->readPC()); 1222315SN/A if (willChangePC) { 1232683SN/A if (newPC == thread->readPC()) { 1242315SN/A DPRINTF(Checker, "Changed PC matches expected PC\n"); 1252315SN/A } else { 1262332SN/A warn("%lli: Changed PC does not match expected PC, " 1272332SN/A "changed: %#x, expected: %#x", 1282683SN/A curTick, thread->readPC(), newPC); 1292732SN/A CheckerCPU::handleError(); 1302315SN/A } 1312315SN/A willChangePC = false; 1322315SN/A } 1332315SN/A changedPC = false; 1342315SN/A } 1352315SN/A if (changedNextPC) { 1362315SN/A DPRINTF(Checker, "Changed NextPC recently to %#x\n", 1372683SN/A thread->readNextPC()); 1382315SN/A changedNextPC = false; 1392315SN/A } 1402315SN/A 1412332SN/A // Try to fetch the instruction 1422332SN/A 1432332SN/A#if FULL_SYSTEM 1442332SN/A#define IFETCH_FLAGS(pc) ((pc) & 1) ? PHYSICAL : 0 1452332SN/A#else 1462332SN/A#define IFETCH_FLAGS(pc) 0 1472332SN/A#endif 1482332SN/A 1492683SN/A uint64_t fetch_PC = thread->readPC() & ~3; 1502679SN/A 1512332SN/A // set up memory request for instruction fetch 1522679SN/A memReq = new Request(inst->threadNumber, fetch_PC, 1532679SN/A sizeof(uint32_t), 1542683SN/A IFETCH_FLAGS(thread->readPC()), 1552683SN/A fetch_PC, thread->readCpuId(), inst->threadNumber); 1562315SN/A 1572315SN/A bool succeeded = translateInstReq(memReq); 1582315SN/A 1592315SN/A if (!succeeded) { 1602323SN/A if (inst->getFault() == NoFault) { 1612332SN/A // In this case the instruction was not a dummy 1622332SN/A // instruction carrying an ITB fault. In the single 1632332SN/A // threaded case the ITB should still be able to 1642332SN/A // translate this instruction; in the SMT case it's 1652332SN/A // possible that its ITB entry was kicked out. 1662332SN/A warn("%lli: Instruction PC %#x was not found in the ITB!", 1672683SN/A curTick, thread->readPC()); 1682732SN/A handleError(inst); 1692315SN/A 1702323SN/A // go to the next instruction 1712683SN/A thread->setPC(thread->readNextPC()); 1722683SN/A thread->setNextPC(thread->readNextPC() + sizeof(MachInst)); 1732315SN/A 1742354SN/A break; 1752323SN/A } else { 1762332SN/A // The instruction is carrying an ITB fault. Handle 1772332SN/A // the fault and see if our results match the CPU on 1782332SN/A // the next tick(). 1792323SN/A fault = inst->getFault(); 1802323SN/A } 1812315SN/A } 1822315SN/A 1832323SN/A if (fault == NoFault) { 1843349Sbinkertn@umich.edu PacketPtr pkt = new Packet(memReq, Packet::ReadReq, 1852679SN/A Packet::Broadcast); 1862679SN/A 1872679SN/A pkt->dataStatic(&machInst); 1882679SN/A 1892679SN/A icachePort->sendFunctional(pkt); 1902679SN/A 1912679SN/A delete pkt; 1922315SN/A 1932332SN/A // keep an instruction count 1942323SN/A numInst++; 1952315SN/A 1962323SN/A // decode the instruction 1972323SN/A machInst = gtoh(machInst); 1982323SN/A // Checks that the instruction matches what we expected it to be. 1992323SN/A // Checks both the machine instruction and the PC. 2002323SN/A validateInst(inst); 2012315SN/A 2023484Sktlim@umich.edu#if THE_ISA == ALPHA_ISA 2033484Sktlim@umich.edu curStaticInst = StaticInst::decode(makeExtMI(machInst, 2043484Sktlim@umich.edu thread->readPC())); 2053484Sktlim@umich.edu#elif THE_ISA == SPARC_ISA 2062332SN/A curStaticInst = StaticInst::decode(makeExtMI(machInst, 2073120Sgblack@eecs.umich.edu thread->getTC())); 2083484Sktlim@umich.edu#endif 2092315SN/A 2102315SN/A#if FULL_SYSTEM 2112683SN/A thread->setInst(machInst); 2122315SN/A#endif // FULL_SYSTEM 2132315SN/A 2142323SN/A fault = inst->getFault(); 2152323SN/A } 2162315SN/A 2172679SN/A // Discard fetch's memReq. 2182679SN/A delete memReq; 2192679SN/A memReq = NULL; 2202679SN/A 2212315SN/A // Either the instruction was a fault and we should process the fault, 2222315SN/A // or we should just go ahead execute the instruction. This assumes 2232315SN/A // that the instruction is properly marked as a fault. 2242315SN/A if (fault == NoFault) { 2252315SN/A 2262683SN/A thread->funcExeInst++; 2272315SN/A 2282354SN/A if (!inst->isUnverifiable()) 2292354SN/A fault = curStaticInst->execute(this, NULL); 2302315SN/A 2312315SN/A // Checks to make sure instrution results are correct. 2322315SN/A validateExecution(inst); 2332315SN/A 2342315SN/A if (curStaticInst->isLoad()) { 2352315SN/A ++numLoad; 2362315SN/A } 2372315SN/A } 2382315SN/A 2392315SN/A if (fault != NoFault) { 2402315SN/A#if FULL_SYSTEM 2412690SN/A fault->invoke(tc); 2422315SN/A willChangePC = true; 2432683SN/A newPC = thread->readPC(); 2442315SN/A DPRINTF(Checker, "Fault, PC is now %#x\n", newPC); 2452838Sktlim@umich.edu#endif 2462315SN/A } else { 2472315SN/A#if THE_ISA != MIPS_ISA 2482315SN/A // go to the next instruction 2492683SN/A thread->setPC(thread->readNextPC()); 2502683SN/A thread->setNextPC(thread->readNextPC() + sizeof(MachInst)); 2512315SN/A#else 2522315SN/A // go to the next instruction 2532683SN/A thread->setPC(thread->readNextPC()); 2542683SN/A thread->setNextPC(thread->readNextNPC()); 2552683SN/A thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst)); 2562315SN/A#endif 2572315SN/A 2582315SN/A } 2592315SN/A 2602315SN/A#if FULL_SYSTEM 2612332SN/A // @todo: Determine if these should happen only if the 2622332SN/A // instruction hasn't faulted. In the SimpleCPU case this may 2632332SN/A // not be true, but in the O3 or Ozone case this may be true. 2642315SN/A Addr oldpc; 2652315SN/A int count = 0; 2662315SN/A do { 2672683SN/A oldpc = thread->readPC(); 2682690SN/A system->pcEventQueue.service(tc); 2692315SN/A count++; 2702683SN/A } while (oldpc != thread->readPC()); 2712315SN/A if (count > 1) { 2722315SN/A willChangePC = true; 2732683SN/A newPC = thread->readPC(); 2742315SN/A DPRINTF(Checker, "PC Event, PC is now %#x\n", newPC); 2752315SN/A } 2762315SN/A#endif 2772315SN/A 2782332SN/A // @todo: Optionally can check all registers. (Or just those 2792315SN/A // that have been modified). 2802315SN/A validateState(); 2812315SN/A 2822679SN/A if (memReq) { 2832679SN/A delete memReq; 2842679SN/A memReq = NULL; 2852679SN/A } 2862679SN/A 2872332SN/A // Continue verifying instructions if there's another completed 2882332SN/A // instruction waiting to be verified. 2892315SN/A if (instList.empty()) { 2902315SN/A break; 2912315SN/A } else if (instList.front()->isCompleted()) { 2922315SN/A inst = instList.front(); 2932315SN/A instList.pop_front(); 2942315SN/A } else { 2952315SN/A break; 2962315SN/A } 2972315SN/A } 2982354SN/A unverifiedInst = NULL; 2992315SN/A} 3002315SN/A 3012315SN/Atemplate <class DynInstPtr> 3022315SN/Avoid 3032840Sktlim@umich.eduChecker<DynInstPtr>::switchOut() 3042315SN/A{ 3052315SN/A instList.clear(); 3062315SN/A} 3072315SN/A 3082315SN/Atemplate <class DynInstPtr> 3092315SN/Avoid 3102315SN/AChecker<DynInstPtr>::takeOverFrom(BaseCPU *oldCPU) 3112315SN/A{ 3122315SN/A} 3132315SN/A 3142315SN/Atemplate <class DynInstPtr> 3152315SN/Avoid 3162315SN/AChecker<DynInstPtr>::validateInst(DynInstPtr &inst) 3172315SN/A{ 3182683SN/A if (inst->readPC() != thread->readPC()) { 3192332SN/A warn("%lli: PCs do not match! Inst: %#x, checker: %#x", 3202683SN/A curTick, inst->readPC(), thread->readPC()); 3212315SN/A if (changedPC) { 3222332SN/A warn("%lli: Changed PCs recently, may not be an error", 3232332SN/A curTick); 3242315SN/A } else { 3252732SN/A handleError(inst); 3262315SN/A } 3272315SN/A } 3282315SN/A 3292332SN/A MachInst mi = static_cast<MachInst>(inst->staticInst->machInst); 3302332SN/A 3312332SN/A if (mi != machInst) { 3322332SN/A warn("%lli: Binary instructions do not match! Inst: %#x, " 3332332SN/A "checker: %#x", 3342332SN/A curTick, mi, machInst); 3352732SN/A handleError(inst); 3362315SN/A } 3372315SN/A} 3382315SN/A 3392315SN/Atemplate <class DynInstPtr> 3402315SN/Avoid 3412315SN/AChecker<DynInstPtr>::validateExecution(DynInstPtr &inst) 3422315SN/A{ 3432732SN/A bool result_mismatch = false; 3442315SN/A if (inst->numDestRegs()) { 3452332SN/A // @todo: Support more destination registers. 3462315SN/A if (inst->isUnverifiable()) { 3472332SN/A // Unverifiable instructions assume they were executed 3482332SN/A // properly by the CPU. Grab the result from the 3492332SN/A // instruction and write it to the register. 3502732SN/A copyResult(inst); 3512315SN/A } else if (result.integer != inst->readIntResult()) { 3522732SN/A result_mismatch = true; 3532732SN/A } 3542732SN/A } 3552732SN/A 3562732SN/A if (result_mismatch) { 3572732SN/A warn("%lli: Instruction results do not match! (Values may not " 3582732SN/A "actually be integers) Inst: %#x, checker: %#x", 3592732SN/A curTick, inst->readIntResult(), result.integer); 3602732SN/A 3612732SN/A // It's useful to verify load values from memory, but in MP 3622732SN/A // systems the value obtained at execute may be different than 3632732SN/A // the value obtained at completion. Similarly DMA can 3642732SN/A // present the same problem on even UP systems. Thus there is 3652732SN/A // the option to only warn on loads having a result error. 3662732SN/A if (inst->isLoad() && warnOnlyOnLoadError) { 3672732SN/A copyResult(inst); 3682732SN/A } else { 3692732SN/A handleError(inst); 3702315SN/A } 3712315SN/A } 3722315SN/A 3732683SN/A if (inst->readNextPC() != thread->readNextPC()) { 3742332SN/A warn("%lli: Instruction next PCs do not match! Inst: %#x, " 3752332SN/A "checker: %#x", 3762683SN/A curTick, inst->readNextPC(), thread->readNextPC()); 3772732SN/A handleError(inst); 3782315SN/A } 3792315SN/A 3802315SN/A // Checking side effect registers can be difficult if they are not 3812315SN/A // checked simultaneously with the execution of the instruction. 3822315SN/A // This is because other valid instructions may have modified 3832315SN/A // these registers in the meantime, and their values are not 3842315SN/A // stored within the DynInst. 3852315SN/A while (!miscRegIdxs.empty()) { 3862315SN/A int misc_reg_idx = miscRegIdxs.front(); 3872315SN/A miscRegIdxs.pop(); 3882315SN/A 3894172Ssaidi@eecs.umich.edu if (inst->tcBase()->readMiscRegNoEffect(misc_reg_idx) != 3904172Ssaidi@eecs.umich.edu thread->readMiscRegNoEffect(misc_reg_idx)) { 3912332SN/A warn("%lli: Misc reg idx %i (side effect) does not match! " 3922332SN/A "Inst: %#x, checker: %#x", 3932332SN/A curTick, misc_reg_idx, 3944172Ssaidi@eecs.umich.edu inst->tcBase()->readMiscRegNoEffect(misc_reg_idx), 3954172Ssaidi@eecs.umich.edu thread->readMiscRegNoEffect(misc_reg_idx)); 3962732SN/A handleError(inst); 3972315SN/A } 3982315SN/A } 3992315SN/A} 4002315SN/A 4012315SN/Atemplate <class DynInstPtr> 4022315SN/Avoid 4032315SN/AChecker<DynInstPtr>::validateState() 4042315SN/A{ 4052354SN/A if (updateThisCycle) { 4062354SN/A warn("%lli: Instruction PC %#x results didn't match up, copying all " 4072356SN/A "registers from main CPU", curTick, unverifiedInst->readPC()); 4082354SN/A // Heavy-weight copying of all registers 4093126Sktlim@umich.edu thread->copyArchRegs(unverifiedInst->tcBase()); 4102356SN/A // Also advance the PC. Hopefully no PC-based events happened. 4112356SN/A#if THE_ISA != MIPS_ISA 4122356SN/A // go to the next instruction 4133126Sktlim@umich.edu thread->setPC(thread->readNextPC()); 4143126Sktlim@umich.edu thread->setNextPC(thread->readNextPC() + sizeof(MachInst)); 4152356SN/A#else 4162356SN/A // go to the next instruction 4173126Sktlim@umich.edu thread->setPC(thread->readNextPC()); 4183126Sktlim@umich.edu thread->setNextPC(thread->readNextNPC()); 4193126Sktlim@umich.edu thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst)); 4202356SN/A#endif 4212354SN/A updateThisCycle = false; 4223126Sktlim@umich.edu } 4232315SN/A} 4242315SN/A 4252315SN/Atemplate <class DynInstPtr> 4262315SN/Avoid 4272732SN/AChecker<DynInstPtr>::copyResult(DynInstPtr &inst) 4282732SN/A{ 4292732SN/A RegIndex idx = inst->destRegIdx(0); 4302732SN/A if (idx < TheISA::FP_Base_DepTag) { 4312732SN/A thread->setIntReg(idx, inst->readIntResult()); 4322732SN/A } else if (idx < TheISA::Fpcr_DepTag) { 4332732SN/A thread->setFloatRegBits(idx, inst->readIntResult()); 4342732SN/A } else { 4354172Ssaidi@eecs.umich.edu thread->setMiscRegNoEffect(idx, inst->readIntResult()); 4362732SN/A } 4372732SN/A} 4382732SN/A 4392732SN/Atemplate <class DynInstPtr> 4402732SN/Avoid 4412732SN/AChecker<DynInstPtr>::dumpAndExit(DynInstPtr &inst) 4422732SN/A{ 4432732SN/A cprintf("Error detected, instruction information:\n"); 4442732SN/A cprintf("PC:%#x, nextPC:%#x\n[sn:%lli]\n[tid:%i]\n" 4452732SN/A "Completed:%i\n", 4462732SN/A inst->readPC(), 4472732SN/A inst->readNextPC(), 4482732SN/A inst->seqNum, 4492732SN/A inst->threadNumber, 4502732SN/A inst->isCompleted()); 4512732SN/A inst->dump(); 4522732SN/A CheckerCPU::dumpAndExit(); 4532732SN/A} 4542732SN/A 4552732SN/Atemplate <class DynInstPtr> 4562732SN/Avoid 4572315SN/AChecker<DynInstPtr>::dumpInsts() 4582315SN/A{ 4592315SN/A int num = 0; 4602315SN/A 4612315SN/A InstListIt inst_list_it = --(instList.end()); 4622315SN/A 4632315SN/A cprintf("Inst list size: %i\n", instList.size()); 4642315SN/A 4652315SN/A while (inst_list_it != instList.end()) 4662315SN/A { 4672315SN/A cprintf("Instruction:%i\n", 4682315SN/A num); 4692315SN/A 4702315SN/A cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n" 4712315SN/A "Completed:%i\n", 4722315SN/A (*inst_list_it)->readPC(), 4732315SN/A (*inst_list_it)->seqNum, 4742315SN/A (*inst_list_it)->threadNumber, 4752315SN/A (*inst_list_it)->isCompleted()); 4762315SN/A 4772315SN/A cprintf("\n"); 4782315SN/A 4792315SN/A inst_list_it--; 4802315SN/A ++num; 4812315SN/A } 4822315SN/A 4832315SN/A} 484