cpu_impl.hh revision 12107
12315SN/A/* 212107SRekai.GonzalezAlberquilla@arm.com * Copyright (c) 2011, 2016 ARM Limited 39913Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48733Sgeoffrey.blake@arm.com * All rights reserved 58733Sgeoffrey.blake@arm.com * 68733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 78733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 88733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 98733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 108733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 118733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 128733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 138733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 148733Sgeoffrey.blake@arm.com * 152332SN/A * Copyright (c) 2006 The Regents of The University of Michigan 162315SN/A * All rights reserved. 172315SN/A * 182315SN/A * Redistribution and use in source and binary forms, with or without 192315SN/A * modification, are permitted provided that the following conditions are 202315SN/A * met: redistributions of source code must retain the above copyright 212315SN/A * notice, this list of conditions and the following disclaimer; 222315SN/A * redistributions in binary form must reproduce the above copyright 232315SN/A * notice, this list of conditions and the following disclaimer in the 242315SN/A * documentation and/or other materials provided with the distribution; 252315SN/A * neither the name of the copyright holders nor the names of its 262315SN/A * contributors may be used to endorse or promote products derived from 272315SN/A * this software without specific prior written permission. 282315SN/A * 292315SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302315SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312315SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322315SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332315SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342315SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352315SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362315SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372315SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382315SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392315SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402689SN/A * 412689SN/A * Authors: Kevin Lim 428733Sgeoffrey.blake@arm.com * Geoffrey Blake 432315SN/A */ 442315SN/A 459944Smatt.horsnell@ARM.com#ifndef __CPU_CHECKER_CPU_IMPL_HH__ 469944Smatt.horsnell@ARM.com#define __CPU_CHECKER_CPU_IMPL_HH__ 479944Smatt.horsnell@ARM.com 482315SN/A#include <list> 492315SN/A#include <string> 502315SN/A 518888Sgeoffrey.blake@arm.com#include "arch/isa_traits.hh" 528793Sgblack@eecs.umich.edu#include "arch/vtophys.hh" 532315SN/A#include "base/refcnt.hh" 546658Snate@binkert.org#include "config/the_isa.hh" 552315SN/A#include "cpu/base_dyn_inst.hh" 568733Sgeoffrey.blake@arm.com#include "cpu/exetrace.hh" 579913Ssteve.reinhardt@amd.com#include "cpu/reg_class.hh" 582683SN/A#include "cpu/simple_thread.hh" 598229Snate@binkert.org#include "cpu/static_inst.hh" 602680SN/A#include "cpu/thread_context.hh" 618733Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 628733Sgeoffrey.blake@arm.com#include "debug/Checker.hh" 638793Sgblack@eecs.umich.edu#include "sim/full_system.hh" 642315SN/A#include "sim/sim_object.hh" 652315SN/A#include "sim/stats.hh" 662315SN/A 672315SN/Ausing namespace std; 688733Sgeoffrey.blake@arm.comusing namespace TheISA; 692315SN/A 708733Sgeoffrey.blake@arm.comtemplate <class Impl> 712315SN/Avoid 7210379Sandreas.hansson@arm.comChecker<Impl>::advancePC(const Fault &fault) 738733Sgeoffrey.blake@arm.com{ 748733Sgeoffrey.blake@arm.com if (fault != NoFault) { 758733Sgeoffrey.blake@arm.com curMacroStaticInst = StaticInst::nullStaticInstPtr; 768733Sgeoffrey.blake@arm.com fault->invoke(tc, curStaticInst); 779023Sgblack@eecs.umich.edu thread->decoder.reset(); 788733Sgeoffrey.blake@arm.com } else { 798733Sgeoffrey.blake@arm.com if (curStaticInst) { 808733Sgeoffrey.blake@arm.com if (curStaticInst->isLastMicroop()) 818733Sgeoffrey.blake@arm.com curMacroStaticInst = StaticInst::nullStaticInstPtr; 828733Sgeoffrey.blake@arm.com TheISA::PCState pcState = thread->pcState(); 838733Sgeoffrey.blake@arm.com TheISA::advancePC(pcState, curStaticInst); 848733Sgeoffrey.blake@arm.com thread->pcState(pcState); 858733Sgeoffrey.blake@arm.com DPRINTF(Checker, "Advancing PC to %s.\n", thread->pcState()); 868733Sgeoffrey.blake@arm.com } 878733Sgeoffrey.blake@arm.com } 888733Sgeoffrey.blake@arm.com} 898733Sgeoffrey.blake@arm.com////////////////////////////////////////////////// 908733Sgeoffrey.blake@arm.com 918733Sgeoffrey.blake@arm.comtemplate <class Impl> 928733Sgeoffrey.blake@arm.comvoid 938733Sgeoffrey.blake@arm.comChecker<Impl>::handlePendingInt() 948733Sgeoffrey.blake@arm.com{ 958733Sgeoffrey.blake@arm.com DPRINTF(Checker, "IRQ detected at PC: %s with %d insts in buffer\n", 968733Sgeoffrey.blake@arm.com thread->pcState(), instList.size()); 978733Sgeoffrey.blake@arm.com DynInstPtr boundaryInst = NULL; 988733Sgeoffrey.blake@arm.com if (!instList.empty()) { 998733Sgeoffrey.blake@arm.com // Set the instructions as completed and verify as much as possible. 1008733Sgeoffrey.blake@arm.com DynInstPtr inst; 1018733Sgeoffrey.blake@arm.com typename std::list<DynInstPtr>::iterator itr; 1028733Sgeoffrey.blake@arm.com 1038733Sgeoffrey.blake@arm.com for (itr = instList.begin(); itr != instList.end(); itr++) { 1048733Sgeoffrey.blake@arm.com (*itr)->setCompleted(); 1058733Sgeoffrey.blake@arm.com } 1068733Sgeoffrey.blake@arm.com 1078733Sgeoffrey.blake@arm.com inst = instList.front(); 1088733Sgeoffrey.blake@arm.com boundaryInst = instList.back(); 1098733Sgeoffrey.blake@arm.com verify(inst); // verify the instructions 1108733Sgeoffrey.blake@arm.com inst = NULL; 1118733Sgeoffrey.blake@arm.com } 1128733Sgeoffrey.blake@arm.com if ((!boundaryInst && curMacroStaticInst && 1138733Sgeoffrey.blake@arm.com curStaticInst->isDelayedCommit() && 1148733Sgeoffrey.blake@arm.com !curStaticInst->isLastMicroop()) || 1158733Sgeoffrey.blake@arm.com (boundaryInst && boundaryInst->isDelayedCommit() && 1168733Sgeoffrey.blake@arm.com !boundaryInst->isLastMicroop())) { 1178733Sgeoffrey.blake@arm.com panic("%lli: Trying to take an interrupt in middle of " 1188733Sgeoffrey.blake@arm.com "a non-interuptable instruction!", curTick()); 1198733Sgeoffrey.blake@arm.com } 1208733Sgeoffrey.blake@arm.com boundaryInst = NULL; 1219023Sgblack@eecs.umich.edu thread->decoder.reset(); 1228733Sgeoffrey.blake@arm.com curMacroStaticInst = StaticInst::nullStaticInstPtr; 1238733Sgeoffrey.blake@arm.com} 1248733Sgeoffrey.blake@arm.com 1258733Sgeoffrey.blake@arm.comtemplate <class Impl> 1268733Sgeoffrey.blake@arm.comvoid 1278733Sgeoffrey.blake@arm.comChecker<Impl>::verify(DynInstPtr &completed_inst) 1282315SN/A{ 1292315SN/A DynInstPtr inst; 1302315SN/A 1318733Sgeoffrey.blake@arm.com // Make sure serializing instructions are actually 1328733Sgeoffrey.blake@arm.com // seen as serializing to commit. instList should be 1338733Sgeoffrey.blake@arm.com // empty in these cases. 1348733Sgeoffrey.blake@arm.com if ((completed_inst->isSerializing() || 1358733Sgeoffrey.blake@arm.com completed_inst->isSerializeBefore()) && 1368733Sgeoffrey.blake@arm.com (!instList.empty() ? 1378733Sgeoffrey.blake@arm.com (instList.front()->seqNum != completed_inst->seqNum) : 0)) { 1388733Sgeoffrey.blake@arm.com panic("%lli: Instruction sn:%lli at PC %s is serializing before but is" 1398733Sgeoffrey.blake@arm.com " entering instList with other instructions\n", curTick(), 1408733Sgeoffrey.blake@arm.com completed_inst->seqNum, completed_inst->pcState()); 1418733Sgeoffrey.blake@arm.com } 1428733Sgeoffrey.blake@arm.com 1432332SN/A // Either check this instruction, or add it to a list of 1442332SN/A // instructions waiting to be checked. Instructions must be 1452332SN/A // checked in program order, so if a store has committed yet not 1462332SN/A // completed, there may be some instructions that are waiting 1472332SN/A // behind it that have completed and must be checked. 1482315SN/A if (!instList.empty()) { 1492315SN/A if (youngestSN < completed_inst->seqNum) { 1508733Sgeoffrey.blake@arm.com DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%s to list\n", 1518733Sgeoffrey.blake@arm.com completed_inst->seqNum, completed_inst->pcState()); 1522315SN/A instList.push_back(completed_inst); 1532315SN/A youngestSN = completed_inst->seqNum; 1542315SN/A } 1552315SN/A 1562315SN/A if (!instList.front()->isCompleted()) { 1572315SN/A return; 1582315SN/A } else { 1592315SN/A inst = instList.front(); 1602315SN/A instList.pop_front(); 1612315SN/A } 1622315SN/A } else { 1632315SN/A if (!completed_inst->isCompleted()) { 1642315SN/A if (youngestSN < completed_inst->seqNum) { 1658733Sgeoffrey.blake@arm.com DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%s to list\n", 1668733Sgeoffrey.blake@arm.com completed_inst->seqNum, completed_inst->pcState()); 1672315SN/A instList.push_back(completed_inst); 1682315SN/A youngestSN = completed_inst->seqNum; 1692315SN/A } 1702315SN/A return; 1712315SN/A } else { 1722315SN/A if (youngestSN < completed_inst->seqNum) { 1732315SN/A inst = completed_inst; 1742315SN/A youngestSN = completed_inst->seqNum; 1752315SN/A } else { 1762315SN/A return; 1772315SN/A } 1782315SN/A } 1792315SN/A } 1802315SN/A 1818733Sgeoffrey.blake@arm.com // Make sure a serializing instruction is actually seen as 1828733Sgeoffrey.blake@arm.com // serializing. instList should be empty here 1838733Sgeoffrey.blake@arm.com if (inst->isSerializeAfter() && !instList.empty()) { 1848733Sgeoffrey.blake@arm.com panic("%lli: Instruction sn:%lli at PC %s is serializing after but is" 1858733Sgeoffrey.blake@arm.com " exiting instList with other instructions\n", curTick(), 1868733Sgeoffrey.blake@arm.com completed_inst->seqNum, completed_inst->pcState()); 1878733Sgeoffrey.blake@arm.com } 1882354SN/A unverifiedInst = inst; 1898733Sgeoffrey.blake@arm.com inst = NULL; 1902354SN/A 1912332SN/A // Try to check all instructions that are completed, ending if we 1922332SN/A // run out of instructions to check or if an instruction is not 1932332SN/A // yet completed. 1942315SN/A while (1) { 1958733Sgeoffrey.blake@arm.com DPRINTF(Checker, "Processing instruction [sn:%lli] PC:%s.\n", 1968733Sgeoffrey.blake@arm.com unverifiedInst->seqNum, unverifiedInst->pcState()); 1978733Sgeoffrey.blake@arm.com unverifiedReq = NULL; 1988733Sgeoffrey.blake@arm.com unverifiedReq = unverifiedInst->reqToVerify; 1998733Sgeoffrey.blake@arm.com unverifiedMemData = unverifiedInst->memData; 2008733Sgeoffrey.blake@arm.com // Make sure results queue is empty 2018733Sgeoffrey.blake@arm.com while (!result.empty()) { 2028733Sgeoffrey.blake@arm.com result.pop(); 2038733Sgeoffrey.blake@arm.com } 2042315SN/A numCycles++; 2052315SN/A 2062315SN/A Fault fault = NoFault; 2072315SN/A 2082315SN/A // maintain $r0 semantics 2092683SN/A thread->setIntReg(ZeroReg, 0); 2108888Sgeoffrey.blake@arm.com#if THE_ISA == ALPHA_ISA 2118888Sgeoffrey.blake@arm.com thread->setFloatReg(ZeroReg, 0.0); 2128888Sgeoffrey.blake@arm.com#endif 2132315SN/A 2142332SN/A // Check if any recent PC changes match up with anything we 2152332SN/A // expect to happen. This is mostly to check if traps or 2162332SN/A // PC-based events have occurred in both the checker and CPU. 2172315SN/A if (changedPC) { 2188733Sgeoffrey.blake@arm.com DPRINTF(Checker, "Changed PC recently to %s\n", 2198733Sgeoffrey.blake@arm.com thread->pcState()); 2202315SN/A if (willChangePC) { 2218733Sgeoffrey.blake@arm.com if (newPCState == thread->pcState()) { 2222315SN/A DPRINTF(Checker, "Changed PC matches expected PC\n"); 2232315SN/A } else { 2242332SN/A warn("%lli: Changed PC does not match expected PC, " 2258733Sgeoffrey.blake@arm.com "changed: %s, expected: %s", 2268733Sgeoffrey.blake@arm.com curTick(), thread->pcState(), newPCState); 2272732SN/A CheckerCPU::handleError(); 2282315SN/A } 2292315SN/A willChangePC = false; 2302315SN/A } 2312315SN/A changedPC = false; 2322315SN/A } 2332315SN/A 2342332SN/A // Try to fetch the instruction 2358733Sgeoffrey.blake@arm.com uint64_t fetchOffset = 0; 2368733Sgeoffrey.blake@arm.com bool fetchDone = false; 2372332SN/A 2388733Sgeoffrey.blake@arm.com while (!fetchDone) { 2398733Sgeoffrey.blake@arm.com Addr fetch_PC = thread->instAddr(); 2408733Sgeoffrey.blake@arm.com fetch_PC = (fetch_PC & PCMask) + fetchOffset; 2412332SN/A 2429023Sgblack@eecs.umich.edu MachInst machInst; 2439023Sgblack@eecs.umich.edu 2448733Sgeoffrey.blake@arm.com // If not in the middle of a macro instruction 2458733Sgeoffrey.blake@arm.com if (!curMacroStaticInst) { 2468733Sgeoffrey.blake@arm.com // set up memory request for instruction fetch 2478733Sgeoffrey.blake@arm.com memReq = new Request(unverifiedInst->threadNumber, fetch_PC, 2488733Sgeoffrey.blake@arm.com sizeof(MachInst), 2498733Sgeoffrey.blake@arm.com 0, 2508887Sgeoffrey.blake@arm.com masterId, 25111435Smitch.hayenga@arm.com fetch_PC, thread->contextId()); 2528733Sgeoffrey.blake@arm.com memReq->setVirt(0, fetch_PC, sizeof(MachInst), 2538832SAli.Saidi@ARM.com Request::INST_FETCH, masterId, thread->instAddr()); 2542679SN/A 2552315SN/A 2568733Sgeoffrey.blake@arm.com fault = itb->translateFunctional(memReq, tc, BaseTLB::Execute); 2572315SN/A 2588733Sgeoffrey.blake@arm.com if (fault != NoFault) { 2598733Sgeoffrey.blake@arm.com if (unverifiedInst->getFault() == NoFault) { 2608733Sgeoffrey.blake@arm.com // In this case the instruction was not a dummy 2618733Sgeoffrey.blake@arm.com // instruction carrying an ITB fault. In the single 2628733Sgeoffrey.blake@arm.com // threaded case the ITB should still be able to 2638733Sgeoffrey.blake@arm.com // translate this instruction; in the SMT case it's 2648733Sgeoffrey.blake@arm.com // possible that its ITB entry was kicked out. 2658733Sgeoffrey.blake@arm.com warn("%lli: Instruction PC %s was not found in the " 2668733Sgeoffrey.blake@arm.com "ITB!", curTick(), thread->pcState()); 2678733Sgeoffrey.blake@arm.com handleError(unverifiedInst); 2682315SN/A 2698733Sgeoffrey.blake@arm.com // go to the next instruction 2708733Sgeoffrey.blake@arm.com advancePC(NoFault); 2712315SN/A 2728733Sgeoffrey.blake@arm.com // Give up on an ITB fault.. 2738733Sgeoffrey.blake@arm.com delete memReq; 2748733Sgeoffrey.blake@arm.com unverifiedInst = NULL; 2758733Sgeoffrey.blake@arm.com return; 2768733Sgeoffrey.blake@arm.com } else { 2778733Sgeoffrey.blake@arm.com // The instruction is carrying an ITB fault. Handle 2788733Sgeoffrey.blake@arm.com // the fault and see if our results match the CPU on 2798733Sgeoffrey.blake@arm.com // the next tick(). 2808733Sgeoffrey.blake@arm.com fault = unverifiedInst->getFault(); 2818733Sgeoffrey.blake@arm.com delete memReq; 2828733Sgeoffrey.blake@arm.com break; 2838733Sgeoffrey.blake@arm.com } 2848733Sgeoffrey.blake@arm.com } else { 2858949Sandreas.hansson@arm.com PacketPtr pkt = new Packet(memReq, MemCmd::ReadReq); 2868733Sgeoffrey.blake@arm.com 2878733Sgeoffrey.blake@arm.com pkt->dataStatic(&machInst); 2888733Sgeoffrey.blake@arm.com icachePort->sendFunctional(pkt); 2898733Sgeoffrey.blake@arm.com machInst = gtoh(machInst); 2908733Sgeoffrey.blake@arm.com 2918733Sgeoffrey.blake@arm.com delete memReq; 2928733Sgeoffrey.blake@arm.com delete pkt; 2938733Sgeoffrey.blake@arm.com } 2948733Sgeoffrey.blake@arm.com } 2958733Sgeoffrey.blake@arm.com 2968733Sgeoffrey.blake@arm.com if (fault == NoFault) { 2978733Sgeoffrey.blake@arm.com TheISA::PCState pcState = thread->pcState(); 2988733Sgeoffrey.blake@arm.com 2998733Sgeoffrey.blake@arm.com if (isRomMicroPC(pcState.microPC())) { 3008733Sgeoffrey.blake@arm.com fetchDone = true; 3018733Sgeoffrey.blake@arm.com curStaticInst = 3028733Sgeoffrey.blake@arm.com microcodeRom.fetchMicroop(pcState.microPC(), NULL); 3038733Sgeoffrey.blake@arm.com } else if (!curMacroStaticInst) { 3048733Sgeoffrey.blake@arm.com //We're not in the middle of a macro instruction 30510417Sandreas.hansson@arm.com StaticInstPtr instPtr = nullptr; 3068733Sgeoffrey.blake@arm.com 3078733Sgeoffrey.blake@arm.com //Predecode, ie bundle up an ExtMachInst 3088733Sgeoffrey.blake@arm.com //If more fetch data is needed, pass it in. 3098733Sgeoffrey.blake@arm.com Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset; 3109023Sgblack@eecs.umich.edu thread->decoder.moreBytes(pcState, fetchPC, machInst); 3118733Sgeoffrey.blake@arm.com 3128733Sgeoffrey.blake@arm.com //If an instruction is ready, decode it. 3138733Sgeoffrey.blake@arm.com //Otherwise, we'll have to fetch beyond the 3148733Sgeoffrey.blake@arm.com //MachInst at the current pc. 3159023Sgblack@eecs.umich.edu if (thread->decoder.instReady()) { 3168733Sgeoffrey.blake@arm.com fetchDone = true; 3179023Sgblack@eecs.umich.edu instPtr = thread->decoder.decode(pcState); 3188733Sgeoffrey.blake@arm.com thread->pcState(pcState); 3198733Sgeoffrey.blake@arm.com } else { 3208733Sgeoffrey.blake@arm.com fetchDone = false; 3218733Sgeoffrey.blake@arm.com fetchOffset += sizeof(TheISA::MachInst); 3228733Sgeoffrey.blake@arm.com } 3238733Sgeoffrey.blake@arm.com 3248733Sgeoffrey.blake@arm.com //If we decoded an instruction and it's microcoded, 3258733Sgeoffrey.blake@arm.com //start pulling out micro ops 3268733Sgeoffrey.blake@arm.com if (instPtr && instPtr->isMacroop()) { 3278733Sgeoffrey.blake@arm.com curMacroStaticInst = instPtr; 3288733Sgeoffrey.blake@arm.com curStaticInst = 3298733Sgeoffrey.blake@arm.com instPtr->fetchMicroop(pcState.microPC()); 3308733Sgeoffrey.blake@arm.com } else { 3318733Sgeoffrey.blake@arm.com curStaticInst = instPtr; 3328733Sgeoffrey.blake@arm.com } 3338733Sgeoffrey.blake@arm.com } else { 3348733Sgeoffrey.blake@arm.com // Read the next micro op from the macro-op 3358733Sgeoffrey.blake@arm.com curStaticInst = 3368733Sgeoffrey.blake@arm.com curMacroStaticInst->fetchMicroop(pcState.microPC()); 3378733Sgeoffrey.blake@arm.com fetchDone = true; 3388733Sgeoffrey.blake@arm.com } 3392323SN/A } 3402315SN/A } 3419023Sgblack@eecs.umich.edu // reset decoder on Checker 3429023Sgblack@eecs.umich.edu thread->decoder.reset(); 3432315SN/A 3448733Sgeoffrey.blake@arm.com // Check Checker and CPU get same instruction, and record 3458733Sgeoffrey.blake@arm.com // any faults the CPU may have had. 3468733Sgeoffrey.blake@arm.com Fault unverifiedFault; 3472323SN/A if (fault == NoFault) { 3488733Sgeoffrey.blake@arm.com unverifiedFault = unverifiedInst->getFault(); 3492679SN/A 3502323SN/A // Checks that the instruction matches what we expected it to be. 3512323SN/A // Checks both the machine instruction and the PC. 3528733Sgeoffrey.blake@arm.com validateInst(unverifiedInst); 3532323SN/A } 3542315SN/A 3558733Sgeoffrey.blake@arm.com // keep an instruction count 3568733Sgeoffrey.blake@arm.com numInst++; 3578733Sgeoffrey.blake@arm.com 3582679SN/A 3592315SN/A // Either the instruction was a fault and we should process the fault, 3602315SN/A // or we should just go ahead execute the instruction. This assumes 3612315SN/A // that the instruction is properly marked as a fault. 3622315SN/A if (fault == NoFault) { 3638733Sgeoffrey.blake@arm.com // Execute Checker instruction and trace 3648733Sgeoffrey.blake@arm.com if (!unverifiedInst->isUnverifiable()) { 3658733Sgeoffrey.blake@arm.com Trace::InstRecord *traceData = tracer->getInstRecord(curTick(), 3668733Sgeoffrey.blake@arm.com tc, 3678733Sgeoffrey.blake@arm.com curStaticInst, 3688733Sgeoffrey.blake@arm.com pcState(), 3698733Sgeoffrey.blake@arm.com curMacroStaticInst); 3708733Sgeoffrey.blake@arm.com fault = curStaticInst->execute(this, traceData); 3718733Sgeoffrey.blake@arm.com if (traceData) { 3728733Sgeoffrey.blake@arm.com traceData->dump(); 3738733Sgeoffrey.blake@arm.com delete traceData; 3748733Sgeoffrey.blake@arm.com } 3758733Sgeoffrey.blake@arm.com } 3762315SN/A 3778733Sgeoffrey.blake@arm.com if (fault == NoFault && unverifiedFault == NoFault) { 3788733Sgeoffrey.blake@arm.com thread->funcExeInst++; 3798733Sgeoffrey.blake@arm.com // Checks to make sure instrution results are correct. 3808733Sgeoffrey.blake@arm.com validateExecution(unverifiedInst); 3812315SN/A 3828733Sgeoffrey.blake@arm.com if (curStaticInst->isLoad()) { 3838733Sgeoffrey.blake@arm.com ++numLoad; 3848733Sgeoffrey.blake@arm.com } 3858733Sgeoffrey.blake@arm.com } else if (fault != NoFault && unverifiedFault == NoFault) { 3868733Sgeoffrey.blake@arm.com panic("%lli: sn: %lli at PC: %s took a fault in checker " 3878733Sgeoffrey.blake@arm.com "but not in driver CPU\n", curTick(), 3888733Sgeoffrey.blake@arm.com unverifiedInst->seqNum, unverifiedInst->pcState()); 3898733Sgeoffrey.blake@arm.com } else if (fault == NoFault && unverifiedFault != NoFault) { 3908733Sgeoffrey.blake@arm.com panic("%lli: sn: %lli at PC: %s took a fault in driver " 3918733Sgeoffrey.blake@arm.com "CPU but not in checker\n", curTick(), 3928733Sgeoffrey.blake@arm.com unverifiedInst->seqNum, unverifiedInst->pcState()); 3932315SN/A } 3942315SN/A } 3952315SN/A 3968733Sgeoffrey.blake@arm.com // Take any faults here 3972315SN/A if (fault != NoFault) { 3988887Sgeoffrey.blake@arm.com if (FullSystem) { 3998887Sgeoffrey.blake@arm.com fault->invoke(tc, curStaticInst); 4008887Sgeoffrey.blake@arm.com willChangePC = true; 4018887Sgeoffrey.blake@arm.com newPCState = thread->pcState(); 4028887Sgeoffrey.blake@arm.com DPRINTF(Checker, "Fault, PC is now %s\n", newPCState); 4038887Sgeoffrey.blake@arm.com curMacroStaticInst = StaticInst::nullStaticInstPtr; 4048887Sgeoffrey.blake@arm.com } 4052315SN/A } else { 4068733Sgeoffrey.blake@arm.com advancePC(fault); 4072315SN/A } 4082315SN/A 4098793Sgblack@eecs.umich.edu if (FullSystem) { 4108793Sgblack@eecs.umich.edu // @todo: Determine if these should happen only if the 4118793Sgblack@eecs.umich.edu // instruction hasn't faulted. In the SimpleCPU case this may 41210426Smitch.hayenga@arm.com // not be true, but in the O3 case this may be true. 4138793Sgblack@eecs.umich.edu Addr oldpc; 4148793Sgblack@eecs.umich.edu int count = 0; 4158793Sgblack@eecs.umich.edu do { 4168809Sgblack@eecs.umich.edu oldpc = thread->instAddr(); 4178793Sgblack@eecs.umich.edu system->pcEventQueue.service(tc); 4188793Sgblack@eecs.umich.edu count++; 4198809Sgblack@eecs.umich.edu } while (oldpc != thread->instAddr()); 4208793Sgblack@eecs.umich.edu if (count > 1) { 4218793Sgblack@eecs.umich.edu willChangePC = true; 4228809Sgblack@eecs.umich.edu newPCState = thread->pcState(); 4238809Sgblack@eecs.umich.edu DPRINTF(Checker, "PC Event, PC is now %s\n", newPCState); 4248793Sgblack@eecs.umich.edu } 4252315SN/A } 4262315SN/A 4272332SN/A // @todo: Optionally can check all registers. (Or just those 4282315SN/A // that have been modified). 4292315SN/A validateState(); 4302315SN/A 4312332SN/A // Continue verifying instructions if there's another completed 4322332SN/A // instruction waiting to be verified. 4332315SN/A if (instList.empty()) { 4342315SN/A break; 4352315SN/A } else if (instList.front()->isCompleted()) { 4368733Sgeoffrey.blake@arm.com unverifiedInst = NULL; 4378733Sgeoffrey.blake@arm.com unverifiedInst = instList.front(); 4382315SN/A instList.pop_front(); 4392315SN/A } else { 4402315SN/A break; 4412315SN/A } 4422315SN/A } 4432354SN/A unverifiedInst = NULL; 4442315SN/A} 4452315SN/A 4468733Sgeoffrey.blake@arm.comtemplate <class Impl> 4472315SN/Avoid 4488733Sgeoffrey.blake@arm.comChecker<Impl>::switchOut() 4492315SN/A{ 4502315SN/A instList.clear(); 4512315SN/A} 4522315SN/A 4538733Sgeoffrey.blake@arm.comtemplate <class Impl> 4542315SN/Avoid 4558733Sgeoffrey.blake@arm.comChecker<Impl>::takeOverFrom(BaseCPU *oldCPU) 4562315SN/A{ 4572315SN/A} 4582315SN/A 4598733Sgeoffrey.blake@arm.comtemplate <class Impl> 4602315SN/Avoid 4618733Sgeoffrey.blake@arm.comChecker<Impl>::validateInst(DynInstPtr &inst) 4622315SN/A{ 4638733Sgeoffrey.blake@arm.com if (inst->instAddr() != thread->instAddr()) { 4648733Sgeoffrey.blake@arm.com warn("%lli: PCs do not match! Inst: %s, checker: %s", 4658733Sgeoffrey.blake@arm.com curTick(), inst->pcState(), thread->pcState()); 4662315SN/A if (changedPC) { 4672332SN/A warn("%lli: Changed PCs recently, may not be an error", 4687823Ssteve.reinhardt@amd.com curTick()); 4692315SN/A } else { 4702732SN/A handleError(inst); 4712315SN/A } 4722315SN/A } 4732315SN/A 4749023Sgblack@eecs.umich.edu if (curStaticInst != inst->staticInst) { 4759023Sgblack@eecs.umich.edu warn("%lli: StaticInstPtrs don't match. (%s, %s).\n", curTick(), 4769023Sgblack@eecs.umich.edu curStaticInst->getName(), inst->staticInst->getName()); 4772315SN/A } 4782315SN/A} 4792315SN/A 4808733Sgeoffrey.blake@arm.comtemplate <class Impl> 4812315SN/Avoid 4828733Sgeoffrey.blake@arm.comChecker<Impl>::validateExecution(DynInstPtr &inst) 4832315SN/A{ 48412107SRekai.GonzalezAlberquilla@arm.com InstResult checker_val; 48512107SRekai.GonzalezAlberquilla@arm.com InstResult inst_val; 4868733Sgeoffrey.blake@arm.com int idx = -1; 4872732SN/A bool result_mismatch = false; 48812107SRekai.GonzalezAlberquilla@arm.com bool scalar_mismatch = false; 4898733Sgeoffrey.blake@arm.com 4908733Sgeoffrey.blake@arm.com if (inst->isUnverifiable()) { 4918733Sgeoffrey.blake@arm.com // Unverifiable instructions assume they were executed 4928733Sgeoffrey.blake@arm.com // properly by the CPU. Grab the result from the 4938733Sgeoffrey.blake@arm.com // instruction and write it to the register. 49412107SRekai.GonzalezAlberquilla@arm.com copyResult(inst, InstResult(0ul, InstResult::ResultType::Scalar), idx); 4958733Sgeoffrey.blake@arm.com } else if (inst->numDestRegs() > 0 && !result.empty()) { 4968733Sgeoffrey.blake@arm.com DPRINTF(Checker, "Dest regs %d, number of checker dest regs %d\n", 4978733Sgeoffrey.blake@arm.com inst->numDestRegs(), result.size()); 4988733Sgeoffrey.blake@arm.com for (int i = 0; i < inst->numDestRegs() && !result.empty(); i++) { 49912107SRekai.GonzalezAlberquilla@arm.com checker_val = result.front(); 5008733Sgeoffrey.blake@arm.com result.pop(); 50112107SRekai.GonzalezAlberquilla@arm.com inst_val = inst->popResult( 50212107SRekai.GonzalezAlberquilla@arm.com InstResult(0ul, InstResult::ResultType::Scalar)); 5038733Sgeoffrey.blake@arm.com if (checker_val != inst_val) { 5048733Sgeoffrey.blake@arm.com result_mismatch = true; 5058733Sgeoffrey.blake@arm.com idx = i; 50612107SRekai.GonzalezAlberquilla@arm.com scalar_mismatch = true; 5078733Sgeoffrey.blake@arm.com break; 5088733Sgeoffrey.blake@arm.com } 5092732SN/A } 5108733Sgeoffrey.blake@arm.com } // Checker CPU checks all the saved results in the dyninst passed by 5118733Sgeoffrey.blake@arm.com // the cpu model being checked against the saved results present in 5128733Sgeoffrey.blake@arm.com // the static inst executed in the Checker. Sometimes the number 5138733Sgeoffrey.blake@arm.com // of saved results differs between the dyninst and static inst, but 5148733Sgeoffrey.blake@arm.com // this is ok and not a bug. May be worthwhile to try and correct this. 5152732SN/A 5162732SN/A if (result_mismatch) { 51712107SRekai.GonzalezAlberquilla@arm.com if (scalar_mismatch) { 51812107SRekai.GonzalezAlberquilla@arm.com warn("%lli: Instruction results (%i) do not match! (Values may" 51912107SRekai.GonzalezAlberquilla@arm.com " not actually be integers) Inst: %#x, checker: %#x", 52012107SRekai.GonzalezAlberquilla@arm.com curTick(), idx, inst_val.asIntegerNoAssert(), 52112107SRekai.GonzalezAlberquilla@arm.com checker_val.asInteger()); 52212107SRekai.GonzalezAlberquilla@arm.com } 5232732SN/A 5242732SN/A // It's useful to verify load values from memory, but in MP 5252732SN/A // systems the value obtained at execute may be different than 5262732SN/A // the value obtained at completion. Similarly DMA can 5272732SN/A // present the same problem on even UP systems. Thus there is 5282732SN/A // the option to only warn on loads having a result error. 5298733Sgeoffrey.blake@arm.com // The load/store queue in Detailed CPU can also cause problems 5308733Sgeoffrey.blake@arm.com // if load/store forwarding is allowed. 5312732SN/A if (inst->isLoad() && warnOnlyOnLoadError) { 53210935Snilay@cs.wisc.edu copyResult(inst, inst_val, idx); 5332732SN/A } else { 5342732SN/A handleError(inst); 5352315SN/A } 5362315SN/A } 5372315SN/A 5388733Sgeoffrey.blake@arm.com if (inst->nextInstAddr() != thread->nextInstAddr()) { 5392332SN/A warn("%lli: Instruction next PCs do not match! Inst: %#x, " 5402332SN/A "checker: %#x", 5418733Sgeoffrey.blake@arm.com curTick(), inst->nextInstAddr(), thread->nextInstAddr()); 5422732SN/A handleError(inst); 5432315SN/A } 5442315SN/A 5452315SN/A // Checking side effect registers can be difficult if they are not 5462315SN/A // checked simultaneously with the execution of the instruction. 5472315SN/A // This is because other valid instructions may have modified 5482315SN/A // these registers in the meantime, and their values are not 5492315SN/A // stored within the DynInst. 5502315SN/A while (!miscRegIdxs.empty()) { 5512315SN/A int misc_reg_idx = miscRegIdxs.front(); 5522315SN/A miscRegIdxs.pop(); 5532315SN/A 5544172Ssaidi@eecs.umich.edu if (inst->tcBase()->readMiscRegNoEffect(misc_reg_idx) != 5554172Ssaidi@eecs.umich.edu thread->readMiscRegNoEffect(misc_reg_idx)) { 5562332SN/A warn("%lli: Misc reg idx %i (side effect) does not match! " 5572332SN/A "Inst: %#x, checker: %#x", 5587823Ssteve.reinhardt@amd.com curTick(), misc_reg_idx, 5594172Ssaidi@eecs.umich.edu inst->tcBase()->readMiscRegNoEffect(misc_reg_idx), 5604172Ssaidi@eecs.umich.edu thread->readMiscRegNoEffect(misc_reg_idx)); 5612732SN/A handleError(inst); 5622315SN/A } 5632315SN/A } 5642315SN/A} 5652315SN/A 5668733Sgeoffrey.blake@arm.com 5678733Sgeoffrey.blake@arm.com// This function is weird, if it is called it means the Checker and 5688733Sgeoffrey.blake@arm.com// O3 have diverged, so panic is called for now. It may be useful 5698733Sgeoffrey.blake@arm.com// to resynch states and continue if the divergence is a false positive 5708733Sgeoffrey.blake@arm.comtemplate <class Impl> 5712315SN/Avoid 5728733Sgeoffrey.blake@arm.comChecker<Impl>::validateState() 5732315SN/A{ 5742354SN/A if (updateThisCycle) { 5758733Sgeoffrey.blake@arm.com // Change this back to warn if divergences end up being false positives 5768733Sgeoffrey.blake@arm.com panic("%lli: Instruction PC %#x results didn't match up, copying all " 5778733Sgeoffrey.blake@arm.com "registers from main CPU", curTick(), unverifiedInst->instAddr()); 5788733Sgeoffrey.blake@arm.com 5798733Sgeoffrey.blake@arm.com // Terribly convoluted way to make sure O3 model does not implode 5809382SAli.Saidi@ARM.com bool no_squash_from_TC = unverifiedInst->thread->noSquashFromTC; 5819382SAli.Saidi@ARM.com unverifiedInst->thread->noSquashFromTC = true; 5828733Sgeoffrey.blake@arm.com 5832354SN/A // Heavy-weight copying of all registers 5843126Sktlim@umich.edu thread->copyArchRegs(unverifiedInst->tcBase()); 5859382SAli.Saidi@ARM.com unverifiedInst->thread->noSquashFromTC = no_squash_from_TC; 5868733Sgeoffrey.blake@arm.com 5878733Sgeoffrey.blake@arm.com // Set curStaticInst to unverifiedInst->staticInst 5888733Sgeoffrey.blake@arm.com curStaticInst = unverifiedInst->staticInst; 5892356SN/A // Also advance the PC. Hopefully no PC-based events happened. 5908733Sgeoffrey.blake@arm.com advancePC(NoFault); 5912354SN/A updateThisCycle = false; 5923126Sktlim@umich.edu } 5932315SN/A} 5942315SN/A 5958733Sgeoffrey.blake@arm.comtemplate <class Impl> 5962315SN/Avoid 59712107SRekai.GonzalezAlberquilla@arm.comChecker<Impl>::copyResult(DynInstPtr &inst, const InstResult& mismatch_val, 5988733Sgeoffrey.blake@arm.com int start_idx) 5992732SN/A{ 6008733Sgeoffrey.blake@arm.com // We've already popped one dest off the queue, 6018733Sgeoffrey.blake@arm.com // so do the fix-up then start with the next dest reg; 6028733Sgeoffrey.blake@arm.com if (start_idx >= 0) { 60312106SRekai.GonzalezAlberquilla@arm.com const RegId& idx = inst->destRegIdx(start_idx); 60412106SRekai.GonzalezAlberquilla@arm.com switch (idx.classValue()) { 6059913Ssteve.reinhardt@amd.com case IntRegClass: 60612107SRekai.GonzalezAlberquilla@arm.com panic_if(!mismatch_val.isScalar(), "Unexpected type of result"); 60712107SRekai.GonzalezAlberquilla@arm.com thread->setIntReg(idx.index(), mismatch_val.asInteger()); 6089913Ssteve.reinhardt@amd.com break; 6099913Ssteve.reinhardt@amd.com case FloatRegClass: 61012107SRekai.GonzalezAlberquilla@arm.com panic_if(!mismatch_val.isScalar(), "Unexpected type of result"); 61112107SRekai.GonzalezAlberquilla@arm.com thread->setFloatRegBits(idx.index(), mismatch_val.asInteger()); 6129913Ssteve.reinhardt@amd.com break; 6139920Syasuko.eckert@amd.com case CCRegClass: 61412107SRekai.GonzalezAlberquilla@arm.com panic_if(!mismatch_val.isScalar(), "Unexpected type of result"); 61512107SRekai.GonzalezAlberquilla@arm.com thread->setCCReg(idx.index(), mismatch_val.asInteger()); 6169920Syasuko.eckert@amd.com break; 6179913Ssteve.reinhardt@amd.com case MiscRegClass: 61812107SRekai.GonzalezAlberquilla@arm.com panic_if(!mismatch_val.isScalar(), "Unexpected type of result"); 61912107SRekai.GonzalezAlberquilla@arm.com thread->setMiscReg(idx.index(), mismatch_val.asInteger()); 6209913Ssteve.reinhardt@amd.com break; 6218733Sgeoffrey.blake@arm.com } 6228733Sgeoffrey.blake@arm.com } 6238733Sgeoffrey.blake@arm.com start_idx++; 62412107SRekai.GonzalezAlberquilla@arm.com InstResult res; 6258733Sgeoffrey.blake@arm.com for (int i = start_idx; i < inst->numDestRegs(); i++) { 62612106SRekai.GonzalezAlberquilla@arm.com const RegId& idx = inst->destRegIdx(i); 62712107SRekai.GonzalezAlberquilla@arm.com res = inst->popResult(); 62812106SRekai.GonzalezAlberquilla@arm.com switch (idx.classValue()) { 62910935Snilay@cs.wisc.edu case IntRegClass: 63012107SRekai.GonzalezAlberquilla@arm.com panic_if(!res.isScalar(), "Unexpected type of result"); 63112107SRekai.GonzalezAlberquilla@arm.com thread->setIntReg(idx.index(), res.asInteger()); 63210935Snilay@cs.wisc.edu break; 63310935Snilay@cs.wisc.edu case FloatRegClass: 63412107SRekai.GonzalezAlberquilla@arm.com panic_if(!res.isScalar(), "Unexpected type of result"); 63512107SRekai.GonzalezAlberquilla@arm.com thread->setFloatRegBits(idx.index(), res.asInteger()); 63610935Snilay@cs.wisc.edu break; 63710935Snilay@cs.wisc.edu case CCRegClass: 63812107SRekai.GonzalezAlberquilla@arm.com panic_if(!res.isScalar(), "Unexpected type of result"); 63912107SRekai.GonzalezAlberquilla@arm.com thread->setCCReg(idx.index(), res.asInteger()); 64010935Snilay@cs.wisc.edu break; 64110935Snilay@cs.wisc.edu case MiscRegClass: 64212107SRekai.GonzalezAlberquilla@arm.com panic_if(res.isValid(), "MiscReg expecting invalid result"); 64310935Snilay@cs.wisc.edu // Try to get the proper misc register index for ARM here... 64412107SRekai.GonzalezAlberquilla@arm.com thread->setMiscReg(idx.index(), 0); 64510935Snilay@cs.wisc.edu break; 6469913Ssteve.reinhardt@amd.com // else Register is out of range... 6479913Ssteve.reinhardt@amd.com } 6482732SN/A } 6492732SN/A} 6502732SN/A 6518733Sgeoffrey.blake@arm.comtemplate <class Impl> 6522732SN/Avoid 6538733Sgeoffrey.blake@arm.comChecker<Impl>::dumpAndExit(DynInstPtr &inst) 6542732SN/A{ 6552732SN/A cprintf("Error detected, instruction information:\n"); 6568733Sgeoffrey.blake@arm.com cprintf("PC:%s, nextPC:%#x\n[sn:%lli]\n[tid:%i]\n" 6572732SN/A "Completed:%i\n", 6588733Sgeoffrey.blake@arm.com inst->pcState(), 6598733Sgeoffrey.blake@arm.com inst->nextInstAddr(), 6602732SN/A inst->seqNum, 6612732SN/A inst->threadNumber, 6622732SN/A inst->isCompleted()); 6632732SN/A inst->dump(); 6642732SN/A CheckerCPU::dumpAndExit(); 6652732SN/A} 6662732SN/A 6678733Sgeoffrey.blake@arm.comtemplate <class Impl> 6682732SN/Avoid 6698733Sgeoffrey.blake@arm.comChecker<Impl>::dumpInsts() 6702315SN/A{ 6712315SN/A int num = 0; 6722315SN/A 6732315SN/A InstListIt inst_list_it = --(instList.end()); 6742315SN/A 6752315SN/A cprintf("Inst list size: %i\n", instList.size()); 6762315SN/A 6772315SN/A while (inst_list_it != instList.end()) 6782315SN/A { 6792315SN/A cprintf("Instruction:%i\n", 6802315SN/A num); 6812315SN/A 6828733Sgeoffrey.blake@arm.com cprintf("PC:%s\n[sn:%lli]\n[tid:%i]\n" 6832315SN/A "Completed:%i\n", 6848733Sgeoffrey.blake@arm.com (*inst_list_it)->pcState(), 6852315SN/A (*inst_list_it)->seqNum, 6862315SN/A (*inst_list_it)->threadNumber, 6872315SN/A (*inst_list_it)->isCompleted()); 6882315SN/A 6892315SN/A cprintf("\n"); 6902315SN/A 6912315SN/A inst_list_it--; 6922315SN/A ++num; 6932315SN/A } 6942315SN/A 6952315SN/A} 6969944Smatt.horsnell@ARM.com 6979944Smatt.horsnell@ARM.com#endif//__CPU_CHECKER_CPU_IMPL_HH__ 698