cpu.hh revision 8888
1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim 41 */ 42 43#ifndef __CPU_CHECKER_CPU_HH__ 44#define __CPU_CHECKER_CPU_HH__ 45 46#include <list> 47#include <map> 48#include <queue> 49 50#include "arch/predecoder.hh" 51#include "arch/types.hh" 52#include "base/statistics.hh" 53#include "cpu/base.hh" 54#include "cpu/base_dyn_inst.hh" 55#include "cpu/pc_event.hh" 56#include "cpu/simple_thread.hh" 57#include "cpu/static_inst.hh" 58#include "debug/Checker.hh" 59#include "params/CheckerCPU.hh" 60#include "sim/eventq.hh" 61 62// forward declarations 63namespace TheISA 64{ 65 class TLB; 66} 67 68template <class> 69class BaseDynInst; 70class ThreadContext; 71class Request; 72 73/** 74 * CheckerCPU class. Dynamically verifies instructions as they are 75 * completed by making sure that the instruction and its results match 76 * the independent execution of the benchmark inside the checker. The 77 * checker verifies instructions in order, regardless of the order in 78 * which instructions complete. There are certain results that can 79 * not be verified, specifically the result of a store conditional or 80 * the values of uncached accesses. In these cases, and with 81 * instructions marked as "IsUnverifiable", the checker assumes that 82 * the value from the main CPU's execution is correct and simply 83 * copies that value. It provides a CheckerThreadContext (see 84 * checker/thread_context.hh) that provides hooks for updating the 85 * Checker's state through any ThreadContext accesses. This allows the 86 * checker to be able to correctly verify instructions, even with 87 * external accesses to the ThreadContext that change state. 88 */ 89class CheckerCPU : public BaseCPU 90{ 91 protected: 92 typedef TheISA::MachInst MachInst; 93 typedef TheISA::FloatReg FloatReg; 94 typedef TheISA::FloatRegBits FloatRegBits; 95 typedef TheISA::MiscReg MiscReg; 96 97 /** id attached to all issued requests */ 98 MasterID masterId; 99 public: 100 virtual void init(); 101 102 public: 103 typedef CheckerCPUParams Params; 104 const Params *params() const 105 { return reinterpret_cast<const Params *>(_params); } 106 CheckerCPU(Params *p); 107 virtual ~CheckerCPU(); 108 109 std::vector<Process*> workload; 110 111 void setSystem(System *system); 112 113 System *systemPtr; 114 115 void setIcachePort(CpuPort *icache_port); 116 117 CpuPort *icachePort; 118 119 void setDcachePort(CpuPort *dcache_port); 120 121 CpuPort *dcachePort; 122 123 CpuPort &getDataPort() 124 { 125 panic("Not supported on checker!"); 126 return *dcachePort; 127 } 128 129 CpuPort &getInstPort() 130 { 131 panic("Not supported on checker!"); 132 return *icachePort; 133 } 134 135 virtual Port *getPort(const std::string &name, int idx) 136 { 137 panic("Not supported on checker!"); 138 return NULL; 139 } 140 141 public: 142 // Primary thread being run. 143 SimpleThread *thread; 144 145 ThreadContext *tc; 146 147 TheISA::TLB *itb; 148 TheISA::TLB *dtb; 149 150 Addr dbg_vtophys(Addr addr); 151 152 union Result { 153 uint64_t integer; 154 double dbl; 155 void set(uint64_t i) { integer = i; } 156 void set(double d) { dbl = d; } 157 void get(uint64_t& i) { i = integer; } 158 void get(double& d) { d = dbl; } 159 }; 160 161 // ISAs like ARM can have multiple destination registers to check, 162 // keep them all in a std::queue 163 std::queue<Result> result; 164 165 // current instruction 166 TheISA::MachInst machInst; 167 168 // Pointer to the one memory request. 169 RequestPtr memReq; 170 171 StaticInstPtr curStaticInst; 172 StaticInstPtr curMacroStaticInst; 173 174 // number of simulated instructions 175 Counter numInst; 176 Counter startNumInst; 177 178 std::queue<int> miscRegIdxs; 179 180 TheISA::TLB* getITBPtr() { return itb; } 181 TheISA::TLB* getDTBPtr() { return dtb; } 182 183 virtual Counter totalInsts() const 184 { 185 return 0; 186 } 187 188 virtual Counter totalOps() const 189 { 190 return 0; 191 } 192 193 // number of simulated loads 194 Counter numLoad; 195 Counter startNumLoad; 196 197 virtual void serialize(std::ostream &os); 198 virtual void unserialize(Checkpoint *cp, const std::string §ion); 199 200 // These functions are only used in CPU models that split 201 // effective address computation from the actual memory access. 202 void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); } 203 Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); } 204 205 // The register accessor methods provide the index of the 206 // instruction's operand (e.g., 0 or 1), not the architectural 207 // register index, to simplify the implementation of register 208 // renaming. We find the architectural register index by indexing 209 // into the instruction's own operand index table. Note that a 210 // raw pointer to the StaticInst is provided instead of a 211 // ref-counted StaticInstPtr to redice overhead. This is fine as 212 // long as these methods don't copy the pointer into any long-term 213 // storage (which is pretty hard to imagine they would have reason 214 // to do). 215 216 uint64_t readIntRegOperand(const StaticInst *si, int idx) 217 { 218 return thread->readIntReg(si->srcRegIdx(idx)); 219 } 220 221 FloatReg readFloatRegOperand(const StaticInst *si, int idx) 222 { 223 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 224 return thread->readFloatReg(reg_idx); 225 } 226 227 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 228 { 229 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 230 return thread->readFloatRegBits(reg_idx); 231 } 232 233 template <class T> 234 void setResult(T t) 235 { 236 Result instRes; 237 instRes.set(t); 238 result.push(instRes); 239 } 240 241 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 242 { 243 thread->setIntReg(si->destRegIdx(idx), val); 244 setResult<uint64_t>(val); 245 } 246 247 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 248 { 249 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 250 thread->setFloatReg(reg_idx, val); 251 setResult<double>(val); 252 } 253 254 void setFloatRegOperandBits(const StaticInst *si, int idx, 255 FloatRegBits val) 256 { 257 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 258 thread->setFloatRegBits(reg_idx, val); 259 setResult<uint64_t>(val); 260 } 261 262 bool readPredicate() { return thread->readPredicate(); } 263 void setPredicate(bool val) 264 { 265 thread->setPredicate(val); 266 } 267 268 TheISA::PCState pcState() { return thread->pcState(); } 269 void pcState(const TheISA::PCState &val) 270 { 271 DPRINTF(Checker, "Changing PC to %s, old PC %s.\n", 272 val, thread->pcState()); 273 thread->pcState(val); 274 } 275 Addr instAddr() { return thread->instAddr(); } 276 Addr nextInstAddr() { return thread->nextInstAddr(); } 277 MicroPC microPC() { return thread->microPC(); } 278 ////////////////////////////////////////// 279 280 MiscReg readMiscRegNoEffect(int misc_reg) 281 { 282 return thread->readMiscRegNoEffect(misc_reg); 283 } 284 285 MiscReg readMiscReg(int misc_reg) 286 { 287 return thread->readMiscReg(misc_reg); 288 } 289 290 void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 291 { 292 miscRegIdxs.push(misc_reg); 293 return thread->setMiscRegNoEffect(misc_reg, val); 294 } 295 296 void setMiscReg(int misc_reg, const MiscReg &val) 297 { 298 miscRegIdxs.push(misc_reg); 299 return thread->setMiscReg(misc_reg, val); 300 } 301 302 MiscReg readMiscRegOperand(const StaticInst *si, int idx) 303 { 304 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 305 return thread->readMiscReg(reg_idx); 306 } 307 308 void setMiscRegOperand( 309 const StaticInst *si, int idx, const MiscReg &val) 310 { 311 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 312 return thread->setMiscReg(reg_idx, val); 313 } 314 315#if THE_ISA == MIPS_ISA 316 uint64_t readRegOtherThread(int misc_reg) 317 { 318 panic("MIPS MT not defined for CheckerCPU.\n"); 319 return 0; 320 } 321 322 void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val) 323 { 324 panic("MIPS MT not defined for CheckerCPU.\n"); 325 } 326#endif 327 328 ///////////////////////////////////////// 329 330 void recordPCChange(const TheISA::PCState &val) 331 { 332 changedPC = true; 333 newPCState = val; 334 } 335 336 void demapPage(Addr vaddr, uint64_t asn) 337 { 338 this->itb->demapPage(vaddr, asn); 339 this->dtb->demapPage(vaddr, asn); 340 } 341 342 void demapInstPage(Addr vaddr, uint64_t asn) 343 { 344 this->itb->demapPage(vaddr, asn); 345 } 346 347 void demapDataPage(Addr vaddr, uint64_t asn) 348 { 349 this->dtb->demapPage(vaddr, asn); 350 } 351 352 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 353 Fault writeMem(uint8_t *data, unsigned size, 354 Addr addr, unsigned flags, uint64_t *res); 355 356 void setStCondFailures(unsigned sc_failures) 357 {} 358 ///////////////////////////////////////////////////// 359 360 Fault hwrei() { return thread->hwrei(); } 361 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 362 void wakeup() { } 363 // Assume that the normal CPU's call to syscall was successful. 364 // The checker's state would have already been updated by the syscall. 365 void syscall(uint64_t callnum) { } 366 367 void handleError() 368 { 369 if (exitOnError) 370 dumpAndExit(); 371 } 372 373 bool checkFlags(Request *unverified_req, Addr vAddr, 374 Addr pAddr, int flags); 375 376 void dumpAndExit(); 377 378 ThreadContext *tcBase() { return tc; } 379 SimpleThread *threadBase() { return thread; } 380 381 Result unverifiedResult; 382 Request *unverifiedReq; 383 uint8_t *unverifiedMemData; 384 385 bool changedPC; 386 bool willChangePC; 387 TheISA::PCState newPCState; 388 bool changedNextPC; 389 bool exitOnError; 390 bool updateOnError; 391 bool warnOnlyOnLoadError; 392 393 InstSeqNum youngestSN; 394}; 395 396/** 397 * Templated Checker class. This Checker class is templated on the 398 * DynInstPtr of the instruction type that will be verified. Proper 399 * template instantiations of the Checker must be placed at the bottom 400 * of checker/cpu.cc. 401 */ 402template <class Impl> 403class Checker : public CheckerCPU 404{ 405 private: 406 typedef typename Impl::DynInstPtr DynInstPtr; 407 408 public: 409 Checker(Params *p) 410 : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL), 411 predecoder(NULL) 412 { } 413 414 void switchOut(); 415 void takeOverFrom(BaseCPU *oldCPU); 416 417 void advancePC(Fault fault); 418 419 void verify(DynInstPtr &inst); 420 421 void validateInst(DynInstPtr &inst); 422 void validateExecution(DynInstPtr &inst); 423 void validateState(); 424 425 void copyResult(DynInstPtr &inst, uint64_t mismatch_val, int start_idx); 426 void handlePendingInt(); 427 428 private: 429 void handleError(DynInstPtr &inst) 430 { 431 if (exitOnError) { 432 dumpAndExit(inst); 433 } else if (updateOnError) { 434 updateThisCycle = true; 435 } 436 } 437 438 void dumpAndExit(DynInstPtr &inst); 439 440 bool updateThisCycle; 441 442 DynInstPtr unverifiedInst; 443 TheISA::Predecoder predecoder; 444 445 std::list<DynInstPtr> instList; 446 typedef typename std::list<DynInstPtr>::iterator InstListIt; 447 void dumpInsts(); 448}; 449 450#endif // __CPU_CHECKER_CPU_HH__ 451