cpu.hh revision 13557
1/* 2 * Copyright (c) 2011, 2016 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 */ 43 44#ifndef __CPU_CHECKER_CPU_HH__ 45#define __CPU_CHECKER_CPU_HH__ 46 47#include <list> 48#include <map> 49#include <queue> 50 51#include "arch/types.hh" 52#include "base/statistics.hh" 53#include "cpu/base.hh" 54#include "cpu/base_dyn_inst.hh" 55#include "cpu/exec_context.hh" 56#include "cpu/inst_res.hh" 57#include "cpu/pc_event.hh" 58#include "cpu/simple_thread.hh" 59#include "cpu/static_inst.hh" 60#include "debug/Checker.hh" 61#include "mem/request.hh" 62#include "params/CheckerCPU.hh" 63#include "sim/eventq.hh" 64 65class BaseTLB; 66template <class> 67class BaseDynInst; 68class ThreadContext; 69class Request; 70 71/** 72 * CheckerCPU class. Dynamically verifies instructions as they are 73 * completed by making sure that the instruction and its results match 74 * the independent execution of the benchmark inside the checker. The 75 * checker verifies instructions in order, regardless of the order in 76 * which instructions complete. There are certain results that can 77 * not be verified, specifically the result of a store conditional or 78 * the values of uncached accesses. In these cases, and with 79 * instructions marked as "IsUnverifiable", the checker assumes that 80 * the value from the main CPU's execution is correct and simply 81 * copies that value. It provides a CheckerThreadContext (see 82 * checker/thread_context.hh) that provides hooks for updating the 83 * Checker's state through any ThreadContext accesses. This allows the 84 * checker to be able to correctly verify instructions, even with 85 * external accesses to the ThreadContext that change state. 86 */ 87class CheckerCPU : public BaseCPU, public ExecContext 88{ 89 protected: 90 typedef TheISA::MachInst MachInst; 91 using VecRegContainer = TheISA::VecRegContainer; 92 93 /** id attached to all issued requests */ 94 MasterID masterId; 95 public: 96 void init() override; 97 98 typedef CheckerCPUParams Params; 99 CheckerCPU(Params *p); 100 virtual ~CheckerCPU(); 101 102 void setSystem(System *system); 103 104 void setIcachePort(MasterPort *icache_port); 105 106 void setDcachePort(MasterPort *dcache_port); 107 108 MasterPort &getDataPort() override 109 { 110 // the checker does not have ports on its own so return the 111 // data port of the actual CPU core 112 assert(dcachePort); 113 return *dcachePort; 114 } 115 116 MasterPort &getInstPort() override 117 { 118 // the checker does not have ports on its own so return the 119 // data port of the actual CPU core 120 assert(icachePort); 121 return *icachePort; 122 } 123 124 protected: 125 126 std::vector<Process*> workload; 127 128 System *systemPtr; 129 130 MasterPort *icachePort; 131 MasterPort *dcachePort; 132 133 ThreadContext *tc; 134 135 BaseTLB *itb; 136 BaseTLB *dtb; 137 138 Addr dbg_vtophys(Addr addr); 139 140 // ISAs like ARM can have multiple destination registers to check, 141 // keep them all in a std::queue 142 std::queue<InstResult> result; 143 144 StaticInstPtr curStaticInst; 145 StaticInstPtr curMacroStaticInst; 146 147 // number of simulated instructions 148 Counter numInst; 149 Counter startNumInst; 150 151 std::queue<int> miscRegIdxs; 152 153 public: 154 155 // Primary thread being run. 156 SimpleThread *thread; 157 158 BaseTLB* getITBPtr() { return itb; } 159 BaseTLB* getDTBPtr() { return dtb; } 160 161 virtual Counter totalInsts() const override 162 { 163 return 0; 164 } 165 166 virtual Counter totalOps() const override 167 { 168 return 0; 169 } 170 171 // number of simulated loads 172 Counter numLoad; 173 Counter startNumLoad; 174 175 void serialize(CheckpointOut &cp) const override; 176 void unserialize(CheckpointIn &cp) override; 177 178 // The register accessor methods provide the index of the 179 // instruction's operand (e.g., 0 or 1), not the architectural 180 // register index, to simplify the implementation of register 181 // renaming. We find the architectural register index by indexing 182 // into the instruction's own operand index table. Note that a 183 // raw pointer to the StaticInst is provided instead of a 184 // ref-counted StaticInstPtr to redice overhead. This is fine as 185 // long as these methods don't copy the pointer into any long-term 186 // storage (which is pretty hard to imagine they would have reason 187 // to do). 188 189 RegVal 190 readIntRegOperand(const StaticInst *si, int idx) override 191 { 192 const RegId& reg = si->srcRegIdx(idx); 193 assert(reg.isIntReg()); 194 return thread->readIntReg(reg.index()); 195 } 196 197 RegVal 198 readFloatRegOperandBits(const StaticInst *si, int idx) override 199 { 200 const RegId& reg = si->srcRegIdx(idx); 201 assert(reg.isFloatReg()); 202 return thread->readFloatRegBits(reg.index()); 203 } 204 205 /** 206 * Read source vector register operand. 207 */ 208 const VecRegContainer & 209 readVecRegOperand(const StaticInst *si, int idx) const override 210 { 211 const RegId& reg = si->srcRegIdx(idx); 212 assert(reg.isVecReg()); 213 return thread->readVecReg(reg); 214 } 215 216 /** 217 * Read destination vector register operand for modification. 218 */ 219 VecRegContainer & 220 getWritableVecRegOperand(const StaticInst *si, int idx) override 221 { 222 const RegId& reg = si->destRegIdx(idx); 223 assert(reg.isVecReg()); 224 return thread->getWritableVecReg(reg); 225 } 226 227 /** Vector Register Lane Interfaces. */ 228 /** @{ */ 229 /** Reads source vector 8bit operand. */ 230 virtual ConstVecLane8 231 readVec8BitLaneOperand(const StaticInst *si, int idx) const override 232 { 233 const RegId& reg = si->destRegIdx(idx); 234 assert(reg.isVecReg()); 235 return thread->readVec8BitLaneReg(reg); 236 } 237 238 /** Reads source vector 16bit operand. */ 239 virtual ConstVecLane16 240 readVec16BitLaneOperand(const StaticInst *si, int idx) const override 241 { 242 const RegId& reg = si->destRegIdx(idx); 243 assert(reg.isVecReg()); 244 return thread->readVec16BitLaneReg(reg); 245 } 246 247 /** Reads source vector 32bit operand. */ 248 virtual ConstVecLane32 249 readVec32BitLaneOperand(const StaticInst *si, int idx) const override 250 { 251 const RegId& reg = si->destRegIdx(idx); 252 assert(reg.isVecReg()); 253 return thread->readVec32BitLaneReg(reg); 254 } 255 256 /** Reads source vector 64bit operand. */ 257 virtual ConstVecLane64 258 readVec64BitLaneOperand(const StaticInst *si, int idx) const override 259 { 260 const RegId& reg = si->destRegIdx(idx); 261 assert(reg.isVecReg()); 262 return thread->readVec64BitLaneReg(reg); 263 } 264 265 /** Write a lane of the destination vector operand. */ 266 template <typename LD> 267 void 268 setVecLaneOperandT(const StaticInst *si, int idx, const LD& val) 269 { 270 const RegId& reg = si->destRegIdx(idx); 271 assert(reg.isVecReg()); 272 return thread->setVecLane(reg, val); 273 } 274 virtual void 275 setVecLaneOperand(const StaticInst *si, int idx, 276 const LaneData<LaneSize::Byte>& val) override 277 { 278 setVecLaneOperandT(si, idx, val); 279 } 280 virtual void 281 setVecLaneOperand(const StaticInst *si, int idx, 282 const LaneData<LaneSize::TwoByte>& val) override 283 { 284 setVecLaneOperandT(si, idx, val); 285 } 286 virtual void 287 setVecLaneOperand(const StaticInst *si, int idx, 288 const LaneData<LaneSize::FourByte>& val) override 289 { 290 setVecLaneOperandT(si, idx, val); 291 } 292 virtual void 293 setVecLaneOperand(const StaticInst *si, int idx, 294 const LaneData<LaneSize::EightByte>& val) override 295 { 296 setVecLaneOperandT(si, idx, val); 297 } 298 /** @} */ 299 300 VecElem 301 readVecElemOperand(const StaticInst *si, int idx) const override 302 { 303 const RegId& reg = si->srcRegIdx(idx); 304 return thread->readVecElem(reg); 305 } 306 307 CCReg 308 readCCRegOperand(const StaticInst *si, int idx) override 309 { 310 const RegId& reg = si->srcRegIdx(idx); 311 assert(reg.isCCReg()); 312 return thread->readCCReg(reg.index()); 313 } 314 315 template<typename T> 316 void 317 setScalarResult(T&& t) 318 { 319 result.push(InstResult(std::forward<T>(t), 320 InstResult::ResultType::Scalar)); 321 } 322 323 template<typename T> 324 void 325 setVecResult(T&& t) 326 { 327 result.push(InstResult(std::forward<T>(t), 328 InstResult::ResultType::VecReg)); 329 } 330 331 template<typename T> 332 void 333 setVecElemResult(T&& t) 334 { 335 result.push(InstResult(std::forward<T>(t), 336 InstResult::ResultType::VecElem)); 337 } 338 339 void 340 setIntRegOperand(const StaticInst *si, int idx, RegVal val) override 341 { 342 const RegId& reg = si->destRegIdx(idx); 343 assert(reg.isIntReg()); 344 thread->setIntReg(reg.index(), val); 345 setScalarResult(val); 346 } 347 348 void 349 setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override 350 { 351 const RegId& reg = si->destRegIdx(idx); 352 assert(reg.isFloatReg()); 353 thread->setFloatRegBits(reg.index(), val); 354 setScalarResult(val); 355 } 356 357 void 358 setCCRegOperand(const StaticInst *si, int idx, CCReg val) override 359 { 360 const RegId& reg = si->destRegIdx(idx); 361 assert(reg.isCCReg()); 362 thread->setCCReg(reg.index(), val); 363 setScalarResult((uint64_t)val); 364 } 365 366 void 367 setVecRegOperand(const StaticInst *si, int idx, 368 const VecRegContainer& val) override 369 { 370 const RegId& reg = si->destRegIdx(idx); 371 assert(reg.isVecReg()); 372 thread->setVecReg(reg, val); 373 setVecResult(val); 374 } 375 376 void 377 setVecElemOperand(const StaticInst *si, int idx, 378 const VecElem val) override 379 { 380 const RegId& reg = si->destRegIdx(idx); 381 assert(reg.isVecElem()); 382 thread->setVecElem(reg, val); 383 setVecElemResult(val); 384 } 385 386 bool readPredicate() const override { return thread->readPredicate(); } 387 388 void 389 setPredicate(bool val) override 390 { 391 thread->setPredicate(val); 392 } 393 394 TheISA::PCState pcState() const override { return thread->pcState(); } 395 void 396 pcState(const TheISA::PCState &val) override 397 { 398 DPRINTF(Checker, "Changing PC to %s, old PC %s.\n", 399 val, thread->pcState()); 400 thread->pcState(val); 401 } 402 Addr instAddr() { return thread->instAddr(); } 403 Addr nextInstAddr() { return thread->nextInstAddr(); } 404 MicroPC microPC() { return thread->microPC(); } 405 ////////////////////////////////////////// 406 407 RegVal 408 readMiscRegNoEffect(int misc_reg) const 409 { 410 return thread->readMiscRegNoEffect(misc_reg); 411 } 412 413 RegVal 414 readMiscReg(int misc_reg) override 415 { 416 return thread->readMiscReg(misc_reg); 417 } 418 419 void 420 setMiscRegNoEffect(int misc_reg, const RegVal &val) 421 { 422 DPRINTF(Checker, "Setting misc reg %d with no effect to check later\n", 423 misc_reg); 424 miscRegIdxs.push(misc_reg); 425 return thread->setMiscRegNoEffect(misc_reg, val); 426 } 427 428 void 429 setMiscReg(int misc_reg, const RegVal &val) override 430 { 431 DPRINTF(Checker, "Setting misc reg %d with effect to check later\n", 432 misc_reg); 433 miscRegIdxs.push(misc_reg); 434 return thread->setMiscReg(misc_reg, val); 435 } 436 437 RegVal 438 readMiscRegOperand(const StaticInst *si, int idx) override 439 { 440 const RegId& reg = si->srcRegIdx(idx); 441 assert(reg.isMiscReg()); 442 return thread->readMiscReg(reg.index()); 443 } 444 445 void 446 setMiscRegOperand(const StaticInst *si, int idx, 447 const RegVal &val) override 448 { 449 const RegId& reg = si->destRegIdx(idx); 450 assert(reg.isMiscReg()); 451 return this->setMiscReg(reg.index(), val); 452 } 453 454#if THE_ISA == MIPS_ISA 455 RegVal 456 readRegOtherThread(const RegId &misc_reg, ThreadID tid) override 457 { 458 panic("MIPS MT not defined for CheckerCPU.\n"); 459 return 0; 460 } 461 462 void 463 setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid) override 464 { 465 panic("MIPS MT not defined for CheckerCPU.\n"); 466 } 467#endif 468 469 ///////////////////////////////////////// 470 471 void 472 recordPCChange(const TheISA::PCState &val) 473 { 474 changedPC = true; 475 newPCState = val; 476 } 477 478 void 479 demapPage(Addr vaddr, uint64_t asn) override 480 { 481 this->itb->demapPage(vaddr, asn); 482 this->dtb->demapPage(vaddr, asn); 483 } 484 485 // monitor/mwait funtions 486 void armMonitor(Addr address) override { BaseCPU::armMonitor(0, address); } 487 bool mwait(PacketPtr pkt) override { return BaseCPU::mwait(0, pkt); } 488 void mwaitAtomic(ThreadContext *tc) override 489 { return BaseCPU::mwaitAtomic(0, tc, thread->dtb); } 490 AddressMonitor *getAddrMonitor() override 491 { return BaseCPU::getCpuAddrMonitor(0); } 492 493 void 494 demapInstPage(Addr vaddr, uint64_t asn) 495 { 496 this->itb->demapPage(vaddr, asn); 497 } 498 499 void 500 demapDataPage(Addr vaddr, uint64_t asn) 501 { 502 this->dtb->demapPage(vaddr, asn); 503 } 504 505 Fault readMem(Addr addr, uint8_t *data, unsigned size, 506 Request::Flags flags) override; 507 Fault writeMem(uint8_t *data, unsigned size, Addr addr, 508 Request::Flags flags, uint64_t *res) override; 509 510 unsigned int 511 readStCondFailures() const override { 512 return thread->readStCondFailures(); 513 } 514 515 void setStCondFailures(unsigned int sc_failures) override {} 516 ///////////////////////////////////////////////////// 517 518 Fault hwrei() override { return thread->hwrei(); } 519 bool simPalCheck(int palFunc) override 520 { return thread->simPalCheck(palFunc); } 521 void wakeup(ThreadID tid) override { } 522 // Assume that the normal CPU's call to syscall was successful. 523 // The checker's state would have already been updated by the syscall. 524 void syscall(int64_t callnum, Fault *fault) override { } 525 526 void 527 handleError() 528 { 529 if (exitOnError) 530 dumpAndExit(); 531 } 532 533 bool checkFlags(const RequestPtr &unverified_req, Addr vAddr, 534 Addr pAddr, int flags); 535 536 void dumpAndExit(); 537 538 ThreadContext *tcBase() override { return tc; } 539 SimpleThread *threadBase() { return thread; } 540 541 InstResult unverifiedResult; 542 RequestPtr unverifiedReq; 543 uint8_t *unverifiedMemData; 544 545 bool changedPC; 546 bool willChangePC; 547 TheISA::PCState newPCState; 548 bool exitOnError; 549 bool updateOnError; 550 bool warnOnlyOnLoadError; 551 552 InstSeqNum youngestSN; 553}; 554 555/** 556 * Templated Checker class. This Checker class is templated on the 557 * DynInstPtr of the instruction type that will be verified. Proper 558 * template instantiations of the Checker must be placed at the bottom 559 * of checker/cpu.cc. 560 */ 561template <class Impl> 562class Checker : public CheckerCPU 563{ 564 private: 565 typedef typename Impl::DynInstPtr DynInstPtr; 566 567 public: 568 Checker(Params *p) 569 : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL) 570 { } 571 572 void switchOut(); 573 void takeOverFrom(BaseCPU *oldCPU); 574 575 void advancePC(const Fault &fault); 576 577 void verify(const DynInstPtr &inst); 578 579 void validateInst(const DynInstPtr &inst); 580 void validateExecution(const DynInstPtr &inst); 581 void validateState(); 582 583 void copyResult(const DynInstPtr &inst, const InstResult& mismatch_val, 584 int start_idx); 585 void handlePendingInt(); 586 587 private: 588 void handleError(const DynInstPtr &inst) 589 { 590 if (exitOnError) { 591 dumpAndExit(inst); 592 } else if (updateOnError) { 593 updateThisCycle = true; 594 } 595 } 596 597 void dumpAndExit(const DynInstPtr &inst); 598 599 bool updateThisCycle; 600 601 DynInstPtr unverifiedInst; 602 603 std::list<DynInstPtr> instList; 604 typedef typename std::list<DynInstPtr>::iterator InstListIt; 605 void dumpInsts(); 606}; 607 608#endif // __CPU_CHECKER_CPU_HH__ 609