cpu.hh revision 12104:edd63f9c6184
1/* 2 * Copyright (c) 2011 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 */ 43 44#ifndef __CPU_CHECKER_CPU_HH__ 45#define __CPU_CHECKER_CPU_HH__ 46 47#include <list> 48#include <map> 49#include <queue> 50 51#include "arch/types.hh" 52#include "base/statistics.hh" 53#include "cpu/base.hh" 54#include "cpu/base_dyn_inst.hh" 55#include "cpu/exec_context.hh" 56#include "cpu/pc_event.hh" 57#include "cpu/simple_thread.hh" 58#include "cpu/static_inst.hh" 59#include "debug/Checker.hh" 60#include "mem/request.hh" 61#include "params/CheckerCPU.hh" 62#include "sim/eventq.hh" 63 64// forward declarations 65namespace TheISA 66{ 67 class TLB; 68} 69 70template <class> 71class BaseDynInst; 72class ThreadContext; 73class Request; 74 75/** 76 * CheckerCPU class. Dynamically verifies instructions as they are 77 * completed by making sure that the instruction and its results match 78 * the independent execution of the benchmark inside the checker. The 79 * checker verifies instructions in order, regardless of the order in 80 * which instructions complete. There are certain results that can 81 * not be verified, specifically the result of a store conditional or 82 * the values of uncached accesses. In these cases, and with 83 * instructions marked as "IsUnverifiable", the checker assumes that 84 * the value from the main CPU's execution is correct and simply 85 * copies that value. It provides a CheckerThreadContext (see 86 * checker/thread_context.hh) that provides hooks for updating the 87 * Checker's state through any ThreadContext accesses. This allows the 88 * checker to be able to correctly verify instructions, even with 89 * external accesses to the ThreadContext that change state. 90 */ 91class CheckerCPU : public BaseCPU, public ExecContext 92{ 93 protected: 94 typedef TheISA::MachInst MachInst; 95 typedef TheISA::FloatReg FloatReg; 96 typedef TheISA::FloatRegBits FloatRegBits; 97 typedef TheISA::MiscReg MiscReg; 98 99 /** id attached to all issued requests */ 100 MasterID masterId; 101 public: 102 void init() override; 103 104 typedef CheckerCPUParams Params; 105 CheckerCPU(Params *p); 106 virtual ~CheckerCPU(); 107 108 void setSystem(System *system); 109 110 void setIcachePort(MasterPort *icache_port); 111 112 void setDcachePort(MasterPort *dcache_port); 113 114 MasterPort &getDataPort() override 115 { 116 // the checker does not have ports on its own so return the 117 // data port of the actual CPU core 118 assert(dcachePort); 119 return *dcachePort; 120 } 121 122 MasterPort &getInstPort() override 123 { 124 // the checker does not have ports on its own so return the 125 // data port of the actual CPU core 126 assert(icachePort); 127 return *icachePort; 128 } 129 130 protected: 131 132 std::vector<Process*> workload; 133 134 System *systemPtr; 135 136 MasterPort *icachePort; 137 MasterPort *dcachePort; 138 139 ThreadContext *tc; 140 141 TheISA::TLB *itb; 142 TheISA::TLB *dtb; 143 144 Addr dbg_vtophys(Addr addr); 145 146 union Result { 147 uint64_t integer; 148 double dbl; 149 void set(uint64_t i) { integer = i; } 150 void set(double d) { dbl = d; } 151 void get(uint64_t& i) { i = integer; } 152 void get(double& d) { d = dbl; } 153 }; 154 155 // ISAs like ARM can have multiple destination registers to check, 156 // keep them all in a std::queue 157 std::queue<Result> result; 158 159 // Pointer to the one memory request. 160 RequestPtr memReq; 161 162 StaticInstPtr curStaticInst; 163 StaticInstPtr curMacroStaticInst; 164 165 // number of simulated instructions 166 Counter numInst; 167 Counter startNumInst; 168 169 std::queue<int> miscRegIdxs; 170 171 public: 172 173 // Primary thread being run. 174 SimpleThread *thread; 175 176 TheISA::TLB* getITBPtr() { return itb; } 177 TheISA::TLB* getDTBPtr() { return dtb; } 178 179 virtual Counter totalInsts() const override 180 { 181 return 0; 182 } 183 184 virtual Counter totalOps() const override 185 { 186 return 0; 187 } 188 189 // number of simulated loads 190 Counter numLoad; 191 Counter startNumLoad; 192 193 void serialize(CheckpointOut &cp) const override; 194 void unserialize(CheckpointIn &cp) override; 195 196 // These functions are only used in CPU models that split 197 // effective address computation from the actual memory access. 198 void setEA(Addr EA) override 199 { panic("CheckerCPU::setEA() not implemented\n"); } 200 Addr getEA() const override 201 { panic("CheckerCPU::getEA() not implemented\n"); } 202 203 // The register accessor methods provide the index of the 204 // instruction's operand (e.g., 0 or 1), not the architectural 205 // register index, to simplify the implementation of register 206 // renaming. We find the architectural register index by indexing 207 // into the instruction's own operand index table. Note that a 208 // raw pointer to the StaticInst is provided instead of a 209 // ref-counted StaticInstPtr to redice overhead. This is fine as 210 // long as these methods don't copy the pointer into any long-term 211 // storage (which is pretty hard to imagine they would have reason 212 // to do). 213 214 IntReg readIntRegOperand(const StaticInst *si, int idx) override 215 { 216 RegId reg = si->srcRegIdx(idx); 217 assert(reg.regClass == IntRegClass); 218 return thread->readIntReg(reg.regIdx); 219 } 220 221 FloatReg readFloatRegOperand(const StaticInst *si, int idx) override 222 { 223 RegId reg = si->srcRegIdx(idx); 224 assert(reg.regClass == FloatRegClass); 225 return thread->readFloatReg(reg.regIdx); 226 } 227 228 FloatRegBits readFloatRegOperandBits(const StaticInst *si, 229 int idx) override 230 { 231 RegId reg = si->srcRegIdx(idx); 232 assert(reg.regClass == FloatRegClass); 233 return thread->readFloatRegBits(reg.regIdx); 234 } 235 236 CCReg readCCRegOperand(const StaticInst *si, int idx) override 237 { 238 RegId reg = si->srcRegIdx(idx); 239 assert(reg.regClass == CCRegClass); 240 return thread->readCCReg(reg.regIdx); 241 } 242 243 template <class T> 244 void setResult(T t) 245 { 246 Result instRes; 247 instRes.set(t); 248 result.push(instRes); 249 } 250 251 void setIntRegOperand(const StaticInst *si, int idx, 252 IntReg val) override 253 { 254 RegId reg = si->destRegIdx(idx); 255 assert(reg.regClass == IntRegClass); 256 thread->setIntReg(reg.regIdx, val); 257 setResult<uint64_t>(val); 258 } 259 260 void setFloatRegOperand(const StaticInst *si, int idx, 261 FloatReg val) override 262 { 263 RegId reg = si->destRegIdx(idx); 264 assert(reg.regClass == FloatRegClass); 265 thread->setFloatReg(reg.regIdx, val); 266 setResult<double>(val); 267 } 268 269 void setFloatRegOperandBits(const StaticInst *si, int idx, 270 FloatRegBits val) override 271 { 272 RegId reg = si->destRegIdx(idx); 273 assert(reg.regClass == FloatRegClass); 274 thread->setFloatRegBits(reg.regIdx, val); 275 setResult<uint64_t>(val); 276 } 277 278 void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override 279 { 280 RegId reg = si->destRegIdx(idx); 281 assert(reg.regClass == CCRegClass); 282 thread->setCCReg(reg.regIdx, val); 283 setResult<uint64_t>(val); 284 } 285 286 bool readPredicate() override { return thread->readPredicate(); } 287 void setPredicate(bool val) override 288 { 289 thread->setPredicate(val); 290 } 291 292 TheISA::PCState pcState() const override { return thread->pcState(); } 293 void pcState(const TheISA::PCState &val) override 294 { 295 DPRINTF(Checker, "Changing PC to %s, old PC %s.\n", 296 val, thread->pcState()); 297 thread->pcState(val); 298 } 299 Addr instAddr() { return thread->instAddr(); } 300 Addr nextInstAddr() { return thread->nextInstAddr(); } 301 MicroPC microPC() { return thread->microPC(); } 302 ////////////////////////////////////////// 303 304 MiscReg readMiscRegNoEffect(int misc_reg) const 305 { 306 return thread->readMiscRegNoEffect(misc_reg); 307 } 308 309 MiscReg readMiscReg(int misc_reg) override 310 { 311 return thread->readMiscReg(misc_reg); 312 } 313 314 void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 315 { 316 DPRINTF(Checker, "Setting misc reg %d with no effect to check later\n", misc_reg); 317 miscRegIdxs.push(misc_reg); 318 return thread->setMiscRegNoEffect(misc_reg, val); 319 } 320 321 void setMiscReg(int misc_reg, const MiscReg &val) override 322 { 323 DPRINTF(Checker, "Setting misc reg %d with effect to check later\n", misc_reg); 324 miscRegIdxs.push(misc_reg); 325 return thread->setMiscReg(misc_reg, val); 326 } 327 328 MiscReg readMiscRegOperand(const StaticInst *si, int idx) override 329 { 330 RegId reg = si->srcRegIdx(idx); 331 assert(reg.regClass == MiscRegClass); 332 return thread->readMiscReg(reg.regIdx); 333 } 334 335 void setMiscRegOperand(const StaticInst *si, int idx, 336 const MiscReg &val) override 337 { 338 RegId reg = si->destRegIdx(idx); 339 assert(reg.regClass == MiscRegClass); 340 return this->setMiscReg(reg.regIdx, val); 341 } 342 343#if THE_ISA == MIPS_ISA 344 MiscReg readRegOtherThread(RegId misc_reg, ThreadID tid) override 345 { 346 panic("MIPS MT not defined for CheckerCPU.\n"); 347 return 0; 348 } 349 350 void setRegOtherThread(RegId misc_reg, MiscReg val, ThreadID tid) override 351 { 352 panic("MIPS MT not defined for CheckerCPU.\n"); 353 } 354#endif 355 356 ///////////////////////////////////////// 357 358 void recordPCChange(const TheISA::PCState &val) 359 { 360 changedPC = true; 361 newPCState = val; 362 } 363 364 void demapPage(Addr vaddr, uint64_t asn) override 365 { 366 this->itb->demapPage(vaddr, asn); 367 this->dtb->demapPage(vaddr, asn); 368 } 369 370 // monitor/mwait funtions 371 void armMonitor(Addr address) override 372 { BaseCPU::armMonitor(0, address); } 373 bool mwait(PacketPtr pkt) override { return BaseCPU::mwait(0, pkt); } 374 void mwaitAtomic(ThreadContext *tc) override 375 { return BaseCPU::mwaitAtomic(0, tc, thread->dtb); } 376 AddressMonitor *getAddrMonitor() override 377 { return BaseCPU::getCpuAddrMonitor(0); } 378 379 void demapInstPage(Addr vaddr, uint64_t asn) 380 { 381 this->itb->demapPage(vaddr, asn); 382 } 383 384 void demapDataPage(Addr vaddr, uint64_t asn) 385 { 386 this->dtb->demapPage(vaddr, asn); 387 } 388 389 Fault readMem(Addr addr, uint8_t *data, unsigned size, 390 Request::Flags flags) override; 391 Fault writeMem(uint8_t *data, unsigned size, Addr addr, 392 Request::Flags flags, uint64_t *res) override; 393 394 unsigned int readStCondFailures() const override { 395 return thread->readStCondFailures(); 396 } 397 398 void setStCondFailures(unsigned int sc_failures) override 399 {} 400 ///////////////////////////////////////////////////// 401 402 Fault hwrei() override { return thread->hwrei(); } 403 bool simPalCheck(int palFunc) override 404 { return thread->simPalCheck(palFunc); } 405 void wakeup(ThreadID tid) override { } 406 // Assume that the normal CPU's call to syscall was successful. 407 // The checker's state would have already been updated by the syscall. 408 void syscall(int64_t callnum, Fault *fault) override { } 409 410 void handleError() 411 { 412 if (exitOnError) 413 dumpAndExit(); 414 } 415 416 bool checkFlags(Request *unverified_req, Addr vAddr, 417 Addr pAddr, int flags); 418 419 void dumpAndExit(); 420 421 ThreadContext *tcBase() override { return tc; } 422 SimpleThread *threadBase() { return thread; } 423 424 Result unverifiedResult; 425 Request *unverifiedReq; 426 uint8_t *unverifiedMemData; 427 428 bool changedPC; 429 bool willChangePC; 430 TheISA::PCState newPCState; 431 bool exitOnError; 432 bool updateOnError; 433 bool warnOnlyOnLoadError; 434 435 InstSeqNum youngestSN; 436}; 437 438/** 439 * Templated Checker class. This Checker class is templated on the 440 * DynInstPtr of the instruction type that will be verified. Proper 441 * template instantiations of the Checker must be placed at the bottom 442 * of checker/cpu.cc. 443 */ 444template <class Impl> 445class Checker : public CheckerCPU 446{ 447 private: 448 typedef typename Impl::DynInstPtr DynInstPtr; 449 450 public: 451 Checker(Params *p) 452 : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL) 453 { } 454 455 void switchOut(); 456 void takeOverFrom(BaseCPU *oldCPU); 457 458 void advancePC(const Fault &fault); 459 460 void verify(DynInstPtr &inst); 461 462 void validateInst(DynInstPtr &inst); 463 void validateExecution(DynInstPtr &inst); 464 void validateState(); 465 466 void copyResult(DynInstPtr &inst, uint64_t mismatch_val, int start_idx); 467 void handlePendingInt(); 468 469 private: 470 void handleError(DynInstPtr &inst) 471 { 472 if (exitOnError) { 473 dumpAndExit(inst); 474 } else if (updateOnError) { 475 updateThisCycle = true; 476 } 477 } 478 479 void dumpAndExit(DynInstPtr &inst); 480 481 bool updateThisCycle; 482 483 DynInstPtr unverifiedInst; 484 485 std::list<DynInstPtr> instList; 486 typedef typename std::list<DynInstPtr>::iterator InstListIt; 487 void dumpInsts(); 488}; 489 490#endif // __CPU_CHECKER_CPU_HH__ 491