cpu.hh revision 10319
1/* 2 * Copyright (c) 2011 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 */ 43 44#ifndef __CPU_CHECKER_CPU_HH__ 45#define __CPU_CHECKER_CPU_HH__ 46 47#include <list> 48#include <map> 49#include <queue> 50 51#include "arch/types.hh" 52#include "base/statistics.hh" 53#include "cpu/base.hh" 54#include "cpu/base_dyn_inst.hh" 55#include "cpu/exec_context.hh" 56#include "cpu/pc_event.hh" 57#include "cpu/simple_thread.hh" 58#include "cpu/static_inst.hh" 59#include "debug/Checker.hh" 60#include "params/CheckerCPU.hh" 61#include "sim/eventq.hh" 62 63// forward declarations 64namespace TheISA 65{ 66 class TLB; 67} 68 69template <class> 70class BaseDynInst; 71class ThreadContext; 72class Request; 73 74/** 75 * CheckerCPU class. Dynamically verifies instructions as they are 76 * completed by making sure that the instruction and its results match 77 * the independent execution of the benchmark inside the checker. The 78 * checker verifies instructions in order, regardless of the order in 79 * which instructions complete. There are certain results that can 80 * not be verified, specifically the result of a store conditional or 81 * the values of uncached accesses. In these cases, and with 82 * instructions marked as "IsUnverifiable", the checker assumes that 83 * the value from the main CPU's execution is correct and simply 84 * copies that value. It provides a CheckerThreadContext (see 85 * checker/thread_context.hh) that provides hooks for updating the 86 * Checker's state through any ThreadContext accesses. This allows the 87 * checker to be able to correctly verify instructions, even with 88 * external accesses to the ThreadContext that change state. 89 */ 90class CheckerCPU : public BaseCPU, public ExecContext 91{ 92 protected: 93 typedef TheISA::MachInst MachInst; 94 typedef TheISA::FloatReg FloatReg; 95 typedef TheISA::FloatRegBits FloatRegBits; 96 typedef TheISA::MiscReg MiscReg; 97 98 /** id attached to all issued requests */ 99 MasterID masterId; 100 public: 101 virtual void init(); 102 103 typedef CheckerCPUParams Params; 104 CheckerCPU(Params *p); 105 virtual ~CheckerCPU(); 106 107 void setSystem(System *system); 108 109 void setIcachePort(MasterPort *icache_port); 110 111 void setDcachePort(MasterPort *dcache_port); 112 113 MasterPort &getDataPort() 114 { 115 // the checker does not have ports on its own so return the 116 // data port of the actual CPU core 117 assert(dcachePort); 118 return *dcachePort; 119 } 120 121 MasterPort &getInstPort() 122 { 123 // the checker does not have ports on its own so return the 124 // data port of the actual CPU core 125 assert(icachePort); 126 return *icachePort; 127 } 128 129 protected: 130 131 std::vector<Process*> workload; 132 133 System *systemPtr; 134 135 MasterPort *icachePort; 136 MasterPort *dcachePort; 137 138 ThreadContext *tc; 139 140 TheISA::TLB *itb; 141 TheISA::TLB *dtb; 142 143 Addr dbg_vtophys(Addr addr); 144 145 union Result { 146 uint64_t integer; 147 double dbl; 148 void set(uint64_t i) { integer = i; } 149 void set(double d) { dbl = d; } 150 void get(uint64_t& i) { i = integer; } 151 void get(double& d) { d = dbl; } 152 }; 153 154 // ISAs like ARM can have multiple destination registers to check, 155 // keep them all in a std::queue 156 std::queue<Result> result; 157 158 // Pointer to the one memory request. 159 RequestPtr memReq; 160 161 StaticInstPtr curStaticInst; 162 StaticInstPtr curMacroStaticInst; 163 164 // number of simulated instructions 165 Counter numInst; 166 Counter startNumInst; 167 168 std::queue<int> miscRegIdxs; 169 170 public: 171 172 // Primary thread being run. 173 SimpleThread *thread; 174 175 TheISA::TLB* getITBPtr() { return itb; } 176 TheISA::TLB* getDTBPtr() { return dtb; } 177 178 virtual Counter totalInsts() const 179 { 180 return 0; 181 } 182 183 virtual Counter totalOps() const 184 { 185 return 0; 186 } 187 188 // number of simulated loads 189 Counter numLoad; 190 Counter startNumLoad; 191 192 virtual void serialize(std::ostream &os); 193 virtual void unserialize(Checkpoint *cp, const std::string §ion); 194 195 // These functions are only used in CPU models that split 196 // effective address computation from the actual memory access. 197 void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); } 198 Addr getEA() const { panic("SimpleCPU::getEA() not implemented\n"); } 199 200 // The register accessor methods provide the index of the 201 // instruction's operand (e.g., 0 or 1), not the architectural 202 // register index, to simplify the implementation of register 203 // renaming. We find the architectural register index by indexing 204 // into the instruction's own operand index table. Note that a 205 // raw pointer to the StaticInst is provided instead of a 206 // ref-counted StaticInstPtr to redice overhead. This is fine as 207 // long as these methods don't copy the pointer into any long-term 208 // storage (which is pretty hard to imagine they would have reason 209 // to do). 210 211 IntReg readIntRegOperand(const StaticInst *si, int idx) 212 { 213 return thread->readIntReg(si->srcRegIdx(idx)); 214 } 215 216 FloatReg readFloatRegOperand(const StaticInst *si, int idx) 217 { 218 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base; 219 return thread->readFloatReg(reg_idx); 220 } 221 222 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 223 { 224 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base; 225 return thread->readFloatRegBits(reg_idx); 226 } 227 228 CCReg readCCRegOperand(const StaticInst *si, int idx) 229 { 230 int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base; 231 return thread->readCCReg(reg_idx); 232 } 233 234 template <class T> 235 void setResult(T t) 236 { 237 Result instRes; 238 instRes.set(t); 239 result.push(instRes); 240 } 241 242 void setIntRegOperand(const StaticInst *si, int idx, IntReg val) 243 { 244 thread->setIntReg(si->destRegIdx(idx), val); 245 setResult<uint64_t>(val); 246 } 247 248 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 249 { 250 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base; 251 thread->setFloatReg(reg_idx, val); 252 setResult<double>(val); 253 } 254 255 void setFloatRegOperandBits(const StaticInst *si, int idx, 256 FloatRegBits val) 257 { 258 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base; 259 thread->setFloatRegBits(reg_idx, val); 260 setResult<uint64_t>(val); 261 } 262 263 void setCCRegOperand(const StaticInst *si, int idx, CCReg val) 264 { 265 int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base; 266 thread->setCCReg(reg_idx, val); 267 setResult<uint64_t>(val); 268 } 269 270 bool readPredicate() { return thread->readPredicate(); } 271 void setPredicate(bool val) 272 { 273 thread->setPredicate(val); 274 } 275 276 TheISA::PCState pcState() const { return thread->pcState(); } 277 void pcState(const TheISA::PCState &val) 278 { 279 DPRINTF(Checker, "Changing PC to %s, old PC %s.\n", 280 val, thread->pcState()); 281 thread->pcState(val); 282 } 283 Addr instAddr() { return thread->instAddr(); } 284 Addr nextInstAddr() { return thread->nextInstAddr(); } 285 MicroPC microPC() { return thread->microPC(); } 286 ////////////////////////////////////////// 287 288 MiscReg readMiscRegNoEffect(int misc_reg) 289 { 290 return thread->readMiscRegNoEffect(misc_reg); 291 } 292 293 MiscReg readMiscReg(int misc_reg) 294 { 295 return thread->readMiscReg(misc_reg); 296 } 297 298 void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 299 { 300 DPRINTF(Checker, "Setting misc reg %d with no effect to check later\n", misc_reg); 301 miscRegIdxs.push(misc_reg); 302 return thread->setMiscRegNoEffect(misc_reg, val); 303 } 304 305 void setMiscReg(int misc_reg, const MiscReg &val) 306 { 307 DPRINTF(Checker, "Setting misc reg %d with effect to check later\n", misc_reg); 308 miscRegIdxs.push(misc_reg); 309 return thread->setMiscReg(misc_reg, val); 310 } 311 312 MiscReg readMiscRegOperand(const StaticInst *si, int idx) 313 { 314 int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base; 315 return thread->readMiscReg(reg_idx); 316 } 317 318 void setMiscRegOperand( 319 const StaticInst *si, int idx, const MiscReg &val) 320 { 321 int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base; 322 return this->setMiscReg(reg_idx, val); 323 } 324 325#if THE_ISA == MIPS_ISA 326 MiscReg readRegOtherThread(int misc_reg, ThreadID tid) 327 { 328 panic("MIPS MT not defined for CheckerCPU.\n"); 329 return 0; 330 } 331 332 void setRegOtherThread(int misc_reg, MiscReg val, ThreadID tid) 333 { 334 panic("MIPS MT not defined for CheckerCPU.\n"); 335 } 336#endif 337 338 ///////////////////////////////////////// 339 340 void recordPCChange(const TheISA::PCState &val) 341 { 342 changedPC = true; 343 newPCState = val; 344 } 345 346 void demapPage(Addr vaddr, uint64_t asn) 347 { 348 this->itb->demapPage(vaddr, asn); 349 this->dtb->demapPage(vaddr, asn); 350 } 351 352 void demapInstPage(Addr vaddr, uint64_t asn) 353 { 354 this->itb->demapPage(vaddr, asn); 355 } 356 357 void demapDataPage(Addr vaddr, uint64_t asn) 358 { 359 this->dtb->demapPage(vaddr, asn); 360 } 361 362 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 363 Fault writeMem(uint8_t *data, unsigned size, 364 Addr addr, unsigned flags, uint64_t *res); 365 366 unsigned int readStCondFailures() const { 367 return thread->readStCondFailures(); 368 } 369 370 void setStCondFailures(unsigned int sc_failures) 371 {} 372 ///////////////////////////////////////////////////// 373 374 Fault hwrei() { return thread->hwrei(); } 375 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 376 void wakeup() { } 377 // Assume that the normal CPU's call to syscall was successful. 378 // The checker's state would have already been updated by the syscall. 379 void syscall(int64_t callnum) { } 380 381 void handleError() 382 { 383 if (exitOnError) 384 dumpAndExit(); 385 } 386 387 bool checkFlags(Request *unverified_req, Addr vAddr, 388 Addr pAddr, int flags); 389 390 void dumpAndExit(); 391 392 ThreadContext *tcBase() { return tc; } 393 SimpleThread *threadBase() { return thread; } 394 395 Result unverifiedResult; 396 Request *unverifiedReq; 397 uint8_t *unverifiedMemData; 398 399 bool changedPC; 400 bool willChangePC; 401 TheISA::PCState newPCState; 402 bool exitOnError; 403 bool updateOnError; 404 bool warnOnlyOnLoadError; 405 406 InstSeqNum youngestSN; 407}; 408 409/** 410 * Templated Checker class. This Checker class is templated on the 411 * DynInstPtr of the instruction type that will be verified. Proper 412 * template instantiations of the Checker must be placed at the bottom 413 * of checker/cpu.cc. 414 */ 415template <class Impl> 416class Checker : public CheckerCPU 417{ 418 private: 419 typedef typename Impl::DynInstPtr DynInstPtr; 420 421 public: 422 Checker(Params *p) 423 : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL) 424 { } 425 426 void switchOut(); 427 void takeOverFrom(BaseCPU *oldCPU); 428 429 void advancePC(Fault fault); 430 431 void verify(DynInstPtr &inst); 432 433 void validateInst(DynInstPtr &inst); 434 void validateExecution(DynInstPtr &inst); 435 void validateState(); 436 437 void copyResult(DynInstPtr &inst, uint64_t mismatch_val, int start_idx); 438 void handlePendingInt(); 439 440 private: 441 void handleError(DynInstPtr &inst) 442 { 443 if (exitOnError) { 444 dumpAndExit(inst); 445 } else if (updateOnError) { 446 updateThisCycle = true; 447 } 448 } 449 450 void dumpAndExit(DynInstPtr &inst); 451 452 bool updateThisCycle; 453 454 DynInstPtr unverifiedInst; 455 456 std::list<DynInstPtr> instList; 457 typedef typename std::list<DynInstPtr>::iterator InstListIt; 458 void dumpInsts(); 459}; 460 461#endif // __CPU_CHECKER_CPU_HH__ 462