cpu.hh revision 9920
12736Sktlim@umich.edu/* 22736Sktlim@umich.edu * Copyright (c) 2011 ARM Limited 32736Sktlim@umich.edu * Copyright (c) 2013 Advanced Micro Devices, Inc. 42736Sktlim@umich.edu * All rights reserved 52736Sktlim@umich.edu * 62736Sktlim@umich.edu * The license below extends only to copyright in the software and shall 72736Sktlim@umich.edu * not be construed as granting a license to any other intellectual 82736Sktlim@umich.edu * property including but not limited to intellectual property relating 92736Sktlim@umich.edu * to a hardware implementation of the functionality of the software 102736Sktlim@umich.edu * licensed hereunder. You may use the software subject to the license 112736Sktlim@umich.edu * terms below provided that you ensure that this notice is replicated 122736Sktlim@umich.edu * unmodified and in its entirety in all distributions of the software, 132736Sktlim@umich.edu * modified or unmodified, in source code or in binary form. 142736Sktlim@umich.edu * 152736Sktlim@umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 162736Sktlim@umich.edu * All rights reserved. 172736Sktlim@umich.edu * 182736Sktlim@umich.edu * Redistribution and use in source and binary forms, with or without 192736Sktlim@umich.edu * modification, are permitted provided that the following conditions are 202736Sktlim@umich.edu * met: redistributions of source code must retain the above copyright 212736Sktlim@umich.edu * notice, this list of conditions and the following disclaimer; 222736Sktlim@umich.edu * redistributions in binary form must reproduce the above copyright 232736Sktlim@umich.edu * notice, this list of conditions and the following disclaimer in the 242736Sktlim@umich.edu * documentation and/or other materials provided with the distribution; 252736Sktlim@umich.edu * neither the name of the copyright holders nor the names of its 262736Sktlim@umich.edu * contributors may be used to endorse or promote products derived from 272736Sktlim@umich.edu * this software without specific prior written permission. 282736Sktlim@umich.edu * 292736Sktlim@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302736Sktlim@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312736Sktlim@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322736Sktlim@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332736Sktlim@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342736Sktlim@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352736Sktlim@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362736Sktlim@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372736Sktlim@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382736Sktlim@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 398229Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 405034Smilesck@eecs.umich.edu * 412736Sktlim@umich.edu * Authors: Kevin Lim 422736Sktlim@umich.edu */ 432736Sktlim@umich.edu 442736Sktlim@umich.edu#ifndef __CPU_CHECKER_CPU_HH__ 452736Sktlim@umich.edu#define __CPU_CHECKER_CPU_HH__ 462736Sktlim@umich.edu 472736Sktlim@umich.edu#include <list> 482736Sktlim@umich.edu#include <map> 492736Sktlim@umich.edu#include <queue> 508737Skoansin.tan@gmail.com 512736Sktlim@umich.edu#include "arch/types.hh" 528737Skoansin.tan@gmail.com#include "base/statistics.hh" 532736Sktlim@umich.edu#include "cpu/base.hh" 549184Sandreas.hansson@arm.com#include "cpu/base_dyn_inst.hh" 5510807Snilay@cs.wisc.edu#include "cpu/pc_event.hh" 562736Sktlim@umich.edu#include "cpu/simple_thread.hh" 575034Smilesck@eecs.umich.edu#include "cpu/static_inst.hh" 585034Smilesck@eecs.umich.edu#include "debug/Checker.hh" 5910807Snilay@cs.wisc.edu#include "params/CheckerCPU.hh" 602736Sktlim@umich.edu#include "sim/eventq.hh" 612736Sktlim@umich.edu 628737Skoansin.tan@gmail.com// forward declarations 632736Sktlim@umich.edunamespace TheISA 648737Skoansin.tan@gmail.com{ 652736Sktlim@umich.edu class TLB; 662736Sktlim@umich.edu} 672736Sktlim@umich.edu 685034Smilesck@eecs.umich.edutemplate <class> 695034Smilesck@eecs.umich.educlass BaseDynInst; 702736Sktlim@umich.educlass ThreadContext; 712736Sktlim@umich.educlass Request; 725034Smilesck@eecs.umich.edu 735034Smilesck@eecs.umich.edu/** 742736Sktlim@umich.edu * CheckerCPU class. Dynamically verifies instructions as they are 752736Sktlim@umich.edu * completed by making sure that the instruction and its results match 762736Sktlim@umich.edu * the independent execution of the benchmark inside the checker. The 772736Sktlim@umich.edu * checker verifies instructions in order, regardless of the order in 782736Sktlim@umich.edu * which instructions complete. There are certain results that can 792736Sktlim@umich.edu * not be verified, specifically the result of a store conditional or 802736Sktlim@umich.edu * the values of uncached accesses. In these cases, and with 812736Sktlim@umich.edu * instructions marked as "IsUnverifiable", the checker assumes that 822736Sktlim@umich.edu * the value from the main CPU's execution is correct and simply 832736Sktlim@umich.edu * copies that value. It provides a CheckerThreadContext (see 842736Sktlim@umich.edu * checker/thread_context.hh) that provides hooks for updating the 852736Sktlim@umich.edu * Checker's state through any ThreadContext accesses. This allows the 862736Sktlim@umich.edu * checker to be able to correctly verify instructions, even with 872736Sktlim@umich.edu * external accesses to the ThreadContext that change state. 8810807Snilay@cs.wisc.edu */ 892736Sktlim@umich.educlass CheckerCPU : public BaseCPU 902736Sktlim@umich.edu{ 912736Sktlim@umich.edu protected: 922736Sktlim@umich.edu typedef TheISA::MachInst MachInst; 932736Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 942736Sktlim@umich.edu typedef TheISA::FloatRegBits FloatRegBits; 952736Sktlim@umich.edu typedef TheISA::MiscReg MiscReg; 962736Sktlim@umich.edu 9710807Snilay@cs.wisc.edu /** id attached to all issued requests */ 982736Sktlim@umich.edu MasterID masterId; 992736Sktlim@umich.edu public: 1002736Sktlim@umich.edu virtual void init(); 1012736Sktlim@umich.edu 1022736Sktlim@umich.edu typedef CheckerCPUParams Params; 10310807Snilay@cs.wisc.edu CheckerCPU(Params *p); 1042736Sktlim@umich.edu virtual ~CheckerCPU(); 1052736Sktlim@umich.edu 1062736Sktlim@umich.edu void setSystem(System *system); 107 108 void setIcachePort(MasterPort *icache_port); 109 110 void setDcachePort(MasterPort *dcache_port); 111 112 MasterPort &getDataPort() 113 { 114 // the checker does not have ports on its own so return the 115 // data port of the actual CPU core 116 assert(dcachePort); 117 return *dcachePort; 118 } 119 120 MasterPort &getInstPort() 121 { 122 // the checker does not have ports on its own so return the 123 // data port of the actual CPU core 124 assert(icachePort); 125 return *icachePort; 126 } 127 128 protected: 129 130 std::vector<Process*> workload; 131 132 System *systemPtr; 133 134 MasterPort *icachePort; 135 MasterPort *dcachePort; 136 137 ThreadContext *tc; 138 139 TheISA::TLB *itb; 140 TheISA::TLB *dtb; 141 142 Addr dbg_vtophys(Addr addr); 143 144 union Result { 145 uint64_t integer; 146 double dbl; 147 void set(uint64_t i) { integer = i; } 148 void set(double d) { dbl = d; } 149 void get(uint64_t& i) { i = integer; } 150 void get(double& d) { d = dbl; } 151 }; 152 153 // ISAs like ARM can have multiple destination registers to check, 154 // keep them all in a std::queue 155 std::queue<Result> result; 156 157 // Pointer to the one memory request. 158 RequestPtr memReq; 159 160 StaticInstPtr curStaticInst; 161 StaticInstPtr curMacroStaticInst; 162 163 // number of simulated instructions 164 Counter numInst; 165 Counter startNumInst; 166 167 std::queue<int> miscRegIdxs; 168 169 public: 170 171 // Primary thread being run. 172 SimpleThread *thread; 173 174 TheISA::TLB* getITBPtr() { return itb; } 175 TheISA::TLB* getDTBPtr() { return dtb; } 176 177 virtual Counter totalInsts() const 178 { 179 return 0; 180 } 181 182 virtual Counter totalOps() const 183 { 184 return 0; 185 } 186 187 // number of simulated loads 188 Counter numLoad; 189 Counter startNumLoad; 190 191 virtual void serialize(std::ostream &os); 192 virtual void unserialize(Checkpoint *cp, const std::string §ion); 193 194 // These functions are only used in CPU models that split 195 // effective address computation from the actual memory access. 196 void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); } 197 Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); } 198 199 // The register accessor methods provide the index of the 200 // instruction's operand (e.g., 0 or 1), not the architectural 201 // register index, to simplify the implementation of register 202 // renaming. We find the architectural register index by indexing 203 // into the instruction's own operand index table. Note that a 204 // raw pointer to the StaticInst is provided instead of a 205 // ref-counted StaticInstPtr to redice overhead. This is fine as 206 // long as these methods don't copy the pointer into any long-term 207 // storage (which is pretty hard to imagine they would have reason 208 // to do). 209 210 uint64_t readIntRegOperand(const StaticInst *si, int idx) 211 { 212 return thread->readIntReg(si->srcRegIdx(idx)); 213 } 214 215 FloatReg readFloatRegOperand(const StaticInst *si, int idx) 216 { 217 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base; 218 return thread->readFloatReg(reg_idx); 219 } 220 221 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 222 { 223 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base; 224 return thread->readFloatRegBits(reg_idx); 225 } 226 227 uint64_t readCCRegOperand(const StaticInst *si, int idx) 228 { 229 int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base; 230 return thread->readCCReg(reg_idx); 231 } 232 233 template <class T> 234 void setResult(T t) 235 { 236 Result instRes; 237 instRes.set(t); 238 result.push(instRes); 239 } 240 241 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 242 { 243 thread->setIntReg(si->destRegIdx(idx), val); 244 setResult<uint64_t>(val); 245 } 246 247 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 248 { 249 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base; 250 thread->setFloatReg(reg_idx, val); 251 setResult<double>(val); 252 } 253 254 void setFloatRegOperandBits(const StaticInst *si, int idx, 255 FloatRegBits val) 256 { 257 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base; 258 thread->setFloatRegBits(reg_idx, val); 259 setResult<uint64_t>(val); 260 } 261 262 void setCCRegOperand(const StaticInst *si, int idx, uint64_t val) 263 { 264 int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base; 265 thread->setCCReg(reg_idx, val); 266 setResult<uint64_t>(val); 267 } 268 269 bool readPredicate() { return thread->readPredicate(); } 270 void setPredicate(bool val) 271 { 272 thread->setPredicate(val); 273 } 274 275 TheISA::PCState pcState() { return thread->pcState(); } 276 void pcState(const TheISA::PCState &val) 277 { 278 DPRINTF(Checker, "Changing PC to %s, old PC %s.\n", 279 val, thread->pcState()); 280 thread->pcState(val); 281 } 282 Addr instAddr() { return thread->instAddr(); } 283 Addr nextInstAddr() { return thread->nextInstAddr(); } 284 MicroPC microPC() { return thread->microPC(); } 285 ////////////////////////////////////////// 286 287 MiscReg readMiscRegNoEffect(int misc_reg) 288 { 289 return thread->readMiscRegNoEffect(misc_reg); 290 } 291 292 MiscReg readMiscReg(int misc_reg) 293 { 294 return thread->readMiscReg(misc_reg); 295 } 296 297 void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 298 { 299 miscRegIdxs.push(misc_reg); 300 return thread->setMiscRegNoEffect(misc_reg, val); 301 } 302 303 void setMiscReg(int misc_reg, const MiscReg &val) 304 { 305 miscRegIdxs.push(misc_reg); 306 return thread->setMiscReg(misc_reg, val); 307 } 308 309 MiscReg readMiscRegOperand(const StaticInst *si, int idx) 310 { 311 int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base; 312 return thread->readMiscReg(reg_idx); 313 } 314 315 void setMiscRegOperand( 316 const StaticInst *si, int idx, const MiscReg &val) 317 { 318 int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base; 319 return thread->setMiscReg(reg_idx, val); 320 } 321 322#if THE_ISA == MIPS_ISA 323 uint64_t readRegOtherThread(int misc_reg) 324 { 325 panic("MIPS MT not defined for CheckerCPU.\n"); 326 return 0; 327 } 328 329 void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val) 330 { 331 panic("MIPS MT not defined for CheckerCPU.\n"); 332 } 333#endif 334 335 ///////////////////////////////////////// 336 337 void recordPCChange(const TheISA::PCState &val) 338 { 339 changedPC = true; 340 newPCState = val; 341 } 342 343 void demapPage(Addr vaddr, uint64_t asn) 344 { 345 this->itb->demapPage(vaddr, asn); 346 this->dtb->demapPage(vaddr, asn); 347 } 348 349 void demapInstPage(Addr vaddr, uint64_t asn) 350 { 351 this->itb->demapPage(vaddr, asn); 352 } 353 354 void demapDataPage(Addr vaddr, uint64_t asn) 355 { 356 this->dtb->demapPage(vaddr, asn); 357 } 358 359 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 360 Fault writeMem(uint8_t *data, unsigned size, 361 Addr addr, unsigned flags, uint64_t *res); 362 363 void setStCondFailures(unsigned sc_failures) 364 {} 365 ///////////////////////////////////////////////////// 366 367 Fault hwrei() { return thread->hwrei(); } 368 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 369 void wakeup() { } 370 // Assume that the normal CPU's call to syscall was successful. 371 // The checker's state would have already been updated by the syscall. 372 void syscall(uint64_t callnum) { } 373 374 void handleError() 375 { 376 if (exitOnError) 377 dumpAndExit(); 378 } 379 380 bool checkFlags(Request *unverified_req, Addr vAddr, 381 Addr pAddr, int flags); 382 383 void dumpAndExit(); 384 385 ThreadContext *tcBase() { return tc; } 386 SimpleThread *threadBase() { return thread; } 387 388 Result unverifiedResult; 389 Request *unverifiedReq; 390 uint8_t *unverifiedMemData; 391 392 bool changedPC; 393 bool willChangePC; 394 TheISA::PCState newPCState; 395 bool changedNextPC; 396 bool exitOnError; 397 bool updateOnError; 398 bool warnOnlyOnLoadError; 399 400 InstSeqNum youngestSN; 401}; 402 403/** 404 * Templated Checker class. This Checker class is templated on the 405 * DynInstPtr of the instruction type that will be verified. Proper 406 * template instantiations of the Checker must be placed at the bottom 407 * of checker/cpu.cc. 408 */ 409template <class Impl> 410class Checker : public CheckerCPU 411{ 412 private: 413 typedef typename Impl::DynInstPtr DynInstPtr; 414 415 public: 416 Checker(Params *p) 417 : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL) 418 { } 419 420 void switchOut(); 421 void takeOverFrom(BaseCPU *oldCPU); 422 423 void advancePC(Fault fault); 424 425 void verify(DynInstPtr &inst); 426 427 void validateInst(DynInstPtr &inst); 428 void validateExecution(DynInstPtr &inst); 429 void validateState(); 430 431 void copyResult(DynInstPtr &inst, uint64_t mismatch_val, int start_idx); 432 void handlePendingInt(); 433 434 private: 435 void handleError(DynInstPtr &inst) 436 { 437 if (exitOnError) { 438 dumpAndExit(inst); 439 } else if (updateOnError) { 440 updateThisCycle = true; 441 } 442 } 443 444 void dumpAndExit(DynInstPtr &inst); 445 446 bool updateThisCycle; 447 448 DynInstPtr unverifiedInst; 449 450 std::list<DynInstPtr> instList; 451 typedef typename std::list<DynInstPtr>::iterator InstListIt; 452 void dumpInsts(); 453}; 454 455#endif // __CPU_CHECKER_CPU_HH__ 456