cpu.hh revision 8832
12315SN/A/* 28733Sgeoffrey.blake@arm.com * Copyright (c) 2011 ARM Limited 38733Sgeoffrey.blake@arm.com * All rights reserved 48733Sgeoffrey.blake@arm.com * 58733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 68733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 78733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 88733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 98733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 108733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 118733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 128733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 138733Sgeoffrey.blake@arm.com * 142332SN/A * Copyright (c) 2006 The Regents of The University of Michigan 152315SN/A * All rights reserved. 162315SN/A * 172315SN/A * Redistribution and use in source and binary forms, with or without 182315SN/A * modification, are permitted provided that the following conditions are 192315SN/A * met: redistributions of source code must retain the above copyright 202315SN/A * notice, this list of conditions and the following disclaimer; 212315SN/A * redistributions in binary form must reproduce the above copyright 222315SN/A * notice, this list of conditions and the following disclaimer in the 232315SN/A * documentation and/or other materials provided with the distribution; 242315SN/A * neither the name of the copyright holders nor the names of its 252315SN/A * contributors may be used to endorse or promote products derived from 262315SN/A * this software without specific prior written permission. 272315SN/A * 282315SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292315SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302315SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312315SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322315SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332315SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342315SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352315SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362315SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372315SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382315SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392689Sktlim@umich.edu * 402689Sktlim@umich.edu * Authors: Kevin Lim 412315SN/A */ 422315SN/A 432315SN/A#ifndef __CPU_CHECKER_CPU_HH__ 442315SN/A#define __CPU_CHECKER_CPU_HH__ 452315SN/A 462315SN/A#include <list> 478229Snate@binkert.org#include <map> 482315SN/A#include <queue> 492315SN/A 508733Sgeoffrey.blake@arm.com#include "arch/predecoder.hh" 512669Sktlim@umich.edu#include "arch/types.hh" 522315SN/A#include "base/statistics.hh" 532315SN/A#include "cpu/base.hh" 542315SN/A#include "cpu/base_dyn_inst.hh" 558229Snate@binkert.org#include "cpu/pc_event.hh" 562683Sktlim@umich.edu#include "cpu/simple_thread.hh" 572315SN/A#include "cpu/static_inst.hh" 588733Sgeoffrey.blake@arm.com#include "debug/Checker.hh" 598733Sgeoffrey.blake@arm.com#include "params/CheckerCPU.hh" 602315SN/A#include "sim/eventq.hh" 612315SN/A 622315SN/A// forward declarations 633468Sgblack@eecs.umich.edunamespace TheISA 643468Sgblack@eecs.umich.edu{ 656022Sgblack@eecs.umich.edu class TLB; 663468Sgblack@eecs.umich.edu} 672315SN/A 682315SN/Atemplate <class> 692315SN/Aclass BaseDynInst; 702680Sktlim@umich.educlass ThreadContext; 712669Sktlim@umich.educlass Request; 722315SN/A 732350SN/A/** 742350SN/A * CheckerCPU class. Dynamically verifies instructions as they are 752350SN/A * completed by making sure that the instruction and its results match 762350SN/A * the independent execution of the benchmark inside the checker. The 772350SN/A * checker verifies instructions in order, regardless of the order in 782350SN/A * which instructions complete. There are certain results that can 792350SN/A * not be verified, specifically the result of a store conditional or 802350SN/A * the values of uncached accesses. In these cases, and with 812350SN/A * instructions marked as "IsUnverifiable", the checker assumes that 822350SN/A * the value from the main CPU's execution is correct and simply 832680Sktlim@umich.edu * copies that value. It provides a CheckerThreadContext (see 842683Sktlim@umich.edu * checker/thread_context.hh) that provides hooks for updating the 852680Sktlim@umich.edu * Checker's state through any ThreadContext accesses. This allows the 862350SN/A * checker to be able to correctly verify instructions, even with 872680Sktlim@umich.edu * external accesses to the ThreadContext that change state. 882350SN/A */ 892315SN/Aclass CheckerCPU : public BaseCPU 902315SN/A{ 912315SN/A protected: 922315SN/A typedef TheISA::MachInst MachInst; 932669Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 942669Sktlim@umich.edu typedef TheISA::FloatRegBits FloatRegBits; 952315SN/A typedef TheISA::MiscReg MiscReg; 968832SAli.Saidi@ARM.com 978832SAli.Saidi@ARM.com /** id attached to all issued requests */ 988832SAli.Saidi@ARM.com MasterID masterId; 992315SN/A public: 1002315SN/A virtual void init(); 1012315SN/A 1022315SN/A public: 1035529Snate@binkert.org typedef CheckerCPUParams Params; 1045529Snate@binkert.org const Params *params() const 1058733Sgeoffrey.blake@arm.com { return reinterpret_cast<const Params *>(_params); } 1062315SN/A CheckerCPU(Params *p); 1072315SN/A virtual ~CheckerCPU(); 1082315SN/A 1098733Sgeoffrey.blake@arm.com std::vector<Process*> workload; 1102679Sktlim@umich.edu 1112315SN/A void setSystem(System *system); 1122315SN/A 1132315SN/A System *systemPtr; 1142679Sktlim@umich.edu 1152679Sktlim@umich.edu void setIcachePort(Port *icache_port); 1162679Sktlim@umich.edu 1172679Sktlim@umich.edu Port *icachePort; 1182679Sktlim@umich.edu 1192679Sktlim@umich.edu void setDcachePort(Port *dcache_port); 1202679Sktlim@umich.edu 1212679Sktlim@umich.edu Port *dcachePort; 1222679Sktlim@umich.edu 1232871Sktlim@umich.edu virtual Port *getPort(const std::string &name, int idx) 1242871Sktlim@umich.edu { 1252871Sktlim@umich.edu panic("Not supported on checker!"); 1262871Sktlim@umich.edu return NULL; 1272871Sktlim@umich.edu } 1282871Sktlim@umich.edu 1292315SN/A public: 1302683Sktlim@umich.edu // Primary thread being run. 1312683Sktlim@umich.edu SimpleThread *thread; 1322315SN/A 1332680Sktlim@umich.edu ThreadContext *tc; 1342315SN/A 1356022Sgblack@eecs.umich.edu TheISA::TLB *itb; 1366022Sgblack@eecs.umich.edu TheISA::TLB *dtb; 1372315SN/A 1382315SN/A Addr dbg_vtophys(Addr addr); 1392315SN/A 1402315SN/A union Result { 1412315SN/A uint64_t integer; 1422315SN/A double dbl; 1438733Sgeoffrey.blake@arm.com void set(uint64_t i) { integer = i; } 1448733Sgeoffrey.blake@arm.com void set(double d) { dbl = d; } 1458733Sgeoffrey.blake@arm.com void get(uint64_t& i) { i = integer; } 1468733Sgeoffrey.blake@arm.com void get(double& d) { d = dbl; } 1472315SN/A }; 1482315SN/A 1498733Sgeoffrey.blake@arm.com // ISAs like ARM can have multiple destination registers to check, 1508733Sgeoffrey.blake@arm.com // keep them all in a std::queue 1518733Sgeoffrey.blake@arm.com std::queue<Result> result; 1522315SN/A 1532315SN/A // current instruction 1548733Sgeoffrey.blake@arm.com TheISA::MachInst machInst; 1552315SN/A 1562679Sktlim@umich.edu // Pointer to the one memory request. 1572679Sktlim@umich.edu RequestPtr memReq; 1582315SN/A 1592315SN/A StaticInstPtr curStaticInst; 1608733Sgeoffrey.blake@arm.com StaticInstPtr curMacroStaticInst; 1612315SN/A 1622315SN/A // number of simulated instructions 1632315SN/A Counter numInst; 1642315SN/A Counter startNumInst; 1652315SN/A 1662315SN/A std::queue<int> miscRegIdxs; 1672315SN/A 1688733Sgeoffrey.blake@arm.com TheISA::TLB* getITBPtr() { return itb; } 1698733Sgeoffrey.blake@arm.com TheISA::TLB* getDTBPtr() { return dtb; } 1708733Sgeoffrey.blake@arm.com 1712315SN/A virtual Counter totalInstructions() const 1722315SN/A { 1732930Sktlim@umich.edu return 0; 1742315SN/A } 1752315SN/A 1762315SN/A // number of simulated loads 1772315SN/A Counter numLoad; 1782315SN/A Counter startNumLoad; 1792315SN/A 1802315SN/A virtual void serialize(std::ostream &os); 1812315SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 1822315SN/A 1832315SN/A // These functions are only used in CPU models that split 1842315SN/A // effective address computation from the actual memory access. 1852315SN/A void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); } 1865543Ssaidi@eecs.umich.edu Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); } 1872315SN/A 1882315SN/A // The register accessor methods provide the index of the 1892315SN/A // instruction's operand (e.g., 0 or 1), not the architectural 1902315SN/A // register index, to simplify the implementation of register 1912315SN/A // renaming. We find the architectural register index by indexing 1922315SN/A // into the instruction's own operand index table. Note that a 1932315SN/A // raw pointer to the StaticInst is provided instead of a 1942315SN/A // ref-counted StaticInstPtr to redice overhead. This is fine as 1952315SN/A // long as these methods don't copy the pointer into any long-term 1962315SN/A // storage (which is pretty hard to imagine they would have reason 1972315SN/A // to do). 1982315SN/A 1993735Sstever@eecs.umich.edu uint64_t readIntRegOperand(const StaticInst *si, int idx) 2002315SN/A { 2012683Sktlim@umich.edu return thread->readIntReg(si->srcRegIdx(idx)); 2022315SN/A } 2032315SN/A 2043735Sstever@eecs.umich.edu FloatReg readFloatRegOperand(const StaticInst *si, int idx) 2052315SN/A { 2062315SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2072683Sktlim@umich.edu return thread->readFloatReg(reg_idx); 2082315SN/A } 2092315SN/A 2103735Sstever@eecs.umich.edu FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 2112669Sktlim@umich.edu { 2122669Sktlim@umich.edu int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2132683Sktlim@umich.edu return thread->readFloatRegBits(reg_idx); 2142315SN/A } 2152315SN/A 2168733Sgeoffrey.blake@arm.com template <class T> 2178733Sgeoffrey.blake@arm.com void setResult(T t) 2188733Sgeoffrey.blake@arm.com { 2198733Sgeoffrey.blake@arm.com Result instRes; 2208733Sgeoffrey.blake@arm.com instRes.set(t); 2218733Sgeoffrey.blake@arm.com result.push(instRes); 2228733Sgeoffrey.blake@arm.com } 2238733Sgeoffrey.blake@arm.com 2243735Sstever@eecs.umich.edu void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 2252315SN/A { 2262683Sktlim@umich.edu thread->setIntReg(si->destRegIdx(idx), val); 2278733Sgeoffrey.blake@arm.com setResult<uint64_t>(val); 2282315SN/A } 2292315SN/A 2303735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 2312669Sktlim@umich.edu { 2322669Sktlim@umich.edu int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2332683Sktlim@umich.edu thread->setFloatReg(reg_idx, val); 2348733Sgeoffrey.blake@arm.com setResult<double>(val); 2352315SN/A } 2362315SN/A 2373735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, 2383735Sstever@eecs.umich.edu FloatRegBits val) 2392315SN/A { 2402315SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2412683Sktlim@umich.edu thread->setFloatRegBits(reg_idx, val); 2428733Sgeoffrey.blake@arm.com setResult<uint64_t>(val); 2432315SN/A } 2442315SN/A 2458733Sgeoffrey.blake@arm.com bool readPredicate() { return thread->readPredicate(); } 2468733Sgeoffrey.blake@arm.com void setPredicate(bool val) 2478733Sgeoffrey.blake@arm.com { 2488733Sgeoffrey.blake@arm.com thread->setPredicate(val); 2498733Sgeoffrey.blake@arm.com } 2502669Sktlim@umich.edu 2518733Sgeoffrey.blake@arm.com TheISA::PCState pcState() { return thread->pcState(); } 2528733Sgeoffrey.blake@arm.com void pcState(const TheISA::PCState &val) 2538733Sgeoffrey.blake@arm.com { 2548733Sgeoffrey.blake@arm.com DPRINTF(Checker, "Changing PC to %s, old PC %s.\n", 2558733Sgeoffrey.blake@arm.com val, thread->pcState()); 2568733Sgeoffrey.blake@arm.com thread->pcState(val); 2578733Sgeoffrey.blake@arm.com } 2588733Sgeoffrey.blake@arm.com Addr instAddr() { return thread->instAddr(); } 2598733Sgeoffrey.blake@arm.com Addr nextInstAddr() { return thread->nextInstAddr(); } 2608733Sgeoffrey.blake@arm.com MicroPC microPC() { return thread->microPC(); } 2618733Sgeoffrey.blake@arm.com ////////////////////////////////////////// 2622315SN/A 2634172Ssaidi@eecs.umich.edu MiscReg readMiscRegNoEffect(int misc_reg) 2644172Ssaidi@eecs.umich.edu { 2654172Ssaidi@eecs.umich.edu return thread->readMiscRegNoEffect(misc_reg); 2664172Ssaidi@eecs.umich.edu } 2674172Ssaidi@eecs.umich.edu 2682315SN/A MiscReg readMiscReg(int misc_reg) 2692315SN/A { 2702683Sktlim@umich.edu return thread->readMiscReg(misc_reg); 2712315SN/A } 2722315SN/A 2734172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 2742315SN/A { 2754172Ssaidi@eecs.umich.edu miscRegIdxs.push(misc_reg); 2764172Ssaidi@eecs.umich.edu return thread->setMiscRegNoEffect(misc_reg, val); 2772315SN/A } 2782315SN/A 2793468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 2802315SN/A { 2812315SN/A miscRegIdxs.push(misc_reg); 2822683Sktlim@umich.edu return thread->setMiscReg(misc_reg, val); 2832315SN/A } 2842315SN/A 2858733Sgeoffrey.blake@arm.com MiscReg readMiscRegOperand(const StaticInst *si, int idx) 2868733Sgeoffrey.blake@arm.com { 2878733Sgeoffrey.blake@arm.com int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 2888733Sgeoffrey.blake@arm.com return thread->readMiscReg(reg_idx); 2898733Sgeoffrey.blake@arm.com } 2908733Sgeoffrey.blake@arm.com 2918733Sgeoffrey.blake@arm.com void setMiscRegOperand( 2928733Sgeoffrey.blake@arm.com const StaticInst *si, int idx, const MiscReg &val) 2938733Sgeoffrey.blake@arm.com { 2948733Sgeoffrey.blake@arm.com int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 2958733Sgeoffrey.blake@arm.com return thread->setMiscReg(reg_idx, val); 2968733Sgeoffrey.blake@arm.com } 2978733Sgeoffrey.blake@arm.com ///////////////////////////////////////// 2988733Sgeoffrey.blake@arm.com 2998733Sgeoffrey.blake@arm.com void recordPCChange(const TheISA::PCState &val) 3008733Sgeoffrey.blake@arm.com { 3018733Sgeoffrey.blake@arm.com changedPC = true; 3028733Sgeoffrey.blake@arm.com newPCState = val; 3038733Sgeoffrey.blake@arm.com } 3042315SN/A 3055358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 3065358Sgblack@eecs.umich.edu { 3075358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 3085358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 3095358Sgblack@eecs.umich.edu } 3105358Sgblack@eecs.umich.edu 3115358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 3125358Sgblack@eecs.umich.edu { 3135358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 3145358Sgblack@eecs.umich.edu } 3155358Sgblack@eecs.umich.edu 3165358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 3175358Sgblack@eecs.umich.edu { 3185358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 3195358Sgblack@eecs.umich.edu } 3205358Sgblack@eecs.umich.edu 3218733Sgeoffrey.blake@arm.com Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 3228733Sgeoffrey.blake@arm.com Fault writeMem(uint8_t *data, unsigned size, 3238733Sgeoffrey.blake@arm.com Addr addr, unsigned flags, uint64_t *res); 3248733Sgeoffrey.blake@arm.com 3258733Sgeoffrey.blake@arm.com void setStCondFailures(unsigned sc_failures) 3268733Sgeoffrey.blake@arm.com {} 3278733Sgeoffrey.blake@arm.com ///////////////////////////////////////////////////// 3288733Sgeoffrey.blake@arm.com 3295702Ssaidi@eecs.umich.edu Fault hwrei() { return thread->hwrei(); } 3305702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 3318733Sgeoffrey.blake@arm.com void wakeup() { } 3322315SN/A // Assume that the normal CPU's call to syscall was successful. 3332332SN/A // The checker's state would have already been updated by the syscall. 3342669Sktlim@umich.edu void syscall(uint64_t callnum) { } 3352315SN/A 3362315SN/A void handleError() 3372315SN/A { 3382315SN/A if (exitOnError) 3392732Sktlim@umich.edu dumpAndExit(); 3402315SN/A } 3412732Sktlim@umich.edu 3428733Sgeoffrey.blake@arm.com bool checkFlags(Request *unverified_req, Addr vAddr, 3438733Sgeoffrey.blake@arm.com Addr pAddr, int flags); 3442315SN/A 3452732Sktlim@umich.edu void dumpAndExit(); 3462732Sktlim@umich.edu 3472680Sktlim@umich.edu ThreadContext *tcBase() { return tc; } 3482683Sktlim@umich.edu SimpleThread *threadBase() { return thread; } 3492315SN/A 3502315SN/A Result unverifiedResult; 3512669Sktlim@umich.edu Request *unverifiedReq; 3522679Sktlim@umich.edu uint8_t *unverifiedMemData; 3532315SN/A 3542315SN/A bool changedPC; 3552315SN/A bool willChangePC; 3568733Sgeoffrey.blake@arm.com TheISA::PCState newPCState; 3572315SN/A bool changedNextPC; 3582315SN/A bool exitOnError; 3592354SN/A bool updateOnError; 3602732Sktlim@umich.edu bool warnOnlyOnLoadError; 3612315SN/A 3622315SN/A InstSeqNum youngestSN; 3632315SN/A}; 3642315SN/A 3652350SN/A/** 3662350SN/A * Templated Checker class. This Checker class is templated on the 3672350SN/A * DynInstPtr of the instruction type that will be verified. Proper 3682350SN/A * template instantiations of the Checker must be placed at the bottom 3692350SN/A * of checker/cpu.cc. 3702350SN/A */ 3718733Sgeoffrey.blake@arm.comtemplate <class Impl> 3722315SN/Aclass Checker : public CheckerCPU 3732315SN/A{ 3748733Sgeoffrey.blake@arm.com private: 3758733Sgeoffrey.blake@arm.com typedef typename Impl::DynInstPtr DynInstPtr; 3768733Sgeoffrey.blake@arm.com 3772315SN/A public: 3782315SN/A Checker(Params *p) 3798733Sgeoffrey.blake@arm.com : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL), 3808733Sgeoffrey.blake@arm.com predecoder(NULL) 3812315SN/A { } 3822315SN/A 3832840Sktlim@umich.edu void switchOut(); 3842315SN/A void takeOverFrom(BaseCPU *oldCPU); 3852315SN/A 3868733Sgeoffrey.blake@arm.com void advancePC(Fault fault); 3878733Sgeoffrey.blake@arm.com 3882732Sktlim@umich.edu void verify(DynInstPtr &inst); 3892315SN/A 3902315SN/A void validateInst(DynInstPtr &inst); 3912315SN/A void validateExecution(DynInstPtr &inst); 3922315SN/A void validateState(); 3932315SN/A 3948733Sgeoffrey.blake@arm.com void copyResult(DynInstPtr &inst, uint64_t mismatch_val, int start_idx); 3958733Sgeoffrey.blake@arm.com void handlePendingInt(); 3962732Sktlim@umich.edu 3972732Sktlim@umich.edu private: 3982732Sktlim@umich.edu void handleError(DynInstPtr &inst) 3992732Sktlim@umich.edu { 4002360SN/A if (exitOnError) { 4012732Sktlim@umich.edu dumpAndExit(inst); 4022360SN/A } else if (updateOnError) { 4032354SN/A updateThisCycle = true; 4042360SN/A } 4052732Sktlim@umich.edu } 4062732Sktlim@umich.edu 4072732Sktlim@umich.edu void dumpAndExit(DynInstPtr &inst); 4082732Sktlim@umich.edu 4092354SN/A bool updateThisCycle; 4102354SN/A 4112354SN/A DynInstPtr unverifiedInst; 4128733Sgeoffrey.blake@arm.com TheISA::Predecoder predecoder; 4132354SN/A 4142315SN/A std::list<DynInstPtr> instList; 4152315SN/A typedef typename std::list<DynInstPtr>::iterator InstListIt; 4162315SN/A void dumpInsts(); 4172315SN/A}; 4182315SN/A 4192315SN/A#endif // __CPU_CHECKER_CPU_HH__ 420