cpu.hh revision 3735
12315SN/A/* 22332SN/A * Copyright (c) 2006 The Regents of The University of Michigan 32315SN/A * All rights reserved. 42315SN/A * 52315SN/A * Redistribution and use in source and binary forms, with or without 62315SN/A * modification, are permitted provided that the following conditions are 72315SN/A * met: redistributions of source code must retain the above copyright 82315SN/A * notice, this list of conditions and the following disclaimer; 92315SN/A * redistributions in binary form must reproduce the above copyright 102315SN/A * notice, this list of conditions and the following disclaimer in the 112315SN/A * documentation and/or other materials provided with the distribution; 122315SN/A * neither the name of the copyright holders nor the names of its 132315SN/A * contributors may be used to endorse or promote products derived from 142315SN/A * this software without specific prior written permission. 152315SN/A * 162315SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172315SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182315SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192315SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202315SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212315SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222315SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232315SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242315SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252315SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262315SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272689Sktlim@umich.edu * 282689Sktlim@umich.edu * Authors: Kevin Lim 292315SN/A */ 302315SN/A 312315SN/A#ifndef __CPU_CHECKER_CPU_HH__ 322315SN/A#define __CPU_CHECKER_CPU_HH__ 332315SN/A 342315SN/A#include <list> 352315SN/A#include <queue> 362315SN/A#include <map> 372315SN/A 382669Sktlim@umich.edu#include "arch/types.hh" 392315SN/A#include "base/statistics.hh" 402315SN/A#include "config/full_system.hh" 412315SN/A#include "cpu/base.hh" 422315SN/A#include "cpu/base_dyn_inst.hh" 432683Sktlim@umich.edu#include "cpu/simple_thread.hh" 442315SN/A#include "cpu/pc_event.hh" 452315SN/A#include "cpu/static_inst.hh" 462315SN/A#include "sim/eventq.hh" 472315SN/A 482315SN/A// forward declarations 492315SN/A#if FULL_SYSTEM 503468Sgblack@eecs.umich.edunamespace TheISA 513468Sgblack@eecs.umich.edu{ 523468Sgblack@eecs.umich.edu class ITB; 533468Sgblack@eecs.umich.edu class DTB; 543468Sgblack@eecs.umich.edu} 552315SN/Aclass Processor; 562315SN/Aclass PhysicalMemory; 572315SN/A 582315SN/Aclass RemoteGDB; 592315SN/Aclass GDBListener; 602315SN/A 612315SN/A#else 622315SN/A 632315SN/Aclass Process; 642315SN/A 652315SN/A#endif // FULL_SYSTEM 662315SN/Atemplate <class> 672315SN/Aclass BaseDynInst; 682680Sktlim@umich.educlass ThreadContext; 692315SN/Aclass MemInterface; 702315SN/Aclass Checkpoint; 712669Sktlim@umich.educlass Request; 722315SN/A 732350SN/A/** 742350SN/A * CheckerCPU class. Dynamically verifies instructions as they are 752350SN/A * completed by making sure that the instruction and its results match 762350SN/A * the independent execution of the benchmark inside the checker. The 772350SN/A * checker verifies instructions in order, regardless of the order in 782350SN/A * which instructions complete. There are certain results that can 792350SN/A * not be verified, specifically the result of a store conditional or 802350SN/A * the values of uncached accesses. In these cases, and with 812350SN/A * instructions marked as "IsUnverifiable", the checker assumes that 822350SN/A * the value from the main CPU's execution is correct and simply 832680Sktlim@umich.edu * copies that value. It provides a CheckerThreadContext (see 842683Sktlim@umich.edu * checker/thread_context.hh) that provides hooks for updating the 852680Sktlim@umich.edu * Checker's state through any ThreadContext accesses. This allows the 862350SN/A * checker to be able to correctly verify instructions, even with 872680Sktlim@umich.edu * external accesses to the ThreadContext that change state. 882350SN/A */ 892315SN/Aclass CheckerCPU : public BaseCPU 902315SN/A{ 912315SN/A protected: 922315SN/A typedef TheISA::MachInst MachInst; 932669Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 942669Sktlim@umich.edu typedef TheISA::FloatRegBits FloatRegBits; 952315SN/A typedef TheISA::MiscReg MiscReg; 962315SN/A public: 972315SN/A virtual void init(); 982315SN/A 992315SN/A struct Params : public BaseCPU::Params 1002315SN/A { 1012315SN/A#if FULL_SYSTEM 1023468Sgblack@eecs.umich.edu TheISA::ITB *itb; 1033468Sgblack@eecs.umich.edu TheISA::DTB *dtb; 1042315SN/A#else 1052315SN/A Process *process; 1062315SN/A#endif 1072315SN/A bool exitOnError; 1082354SN/A bool updateOnError; 1092732Sktlim@umich.edu bool warnOnlyOnLoadError; 1102315SN/A }; 1112315SN/A 1122315SN/A public: 1132315SN/A CheckerCPU(Params *p); 1142315SN/A virtual ~CheckerCPU(); 1152315SN/A 1162679Sktlim@umich.edu Process *process; 1172679Sktlim@umich.edu 1182315SN/A void setSystem(System *system); 1192315SN/A 1202315SN/A System *systemPtr; 1212679Sktlim@umich.edu 1222679Sktlim@umich.edu void setIcachePort(Port *icache_port); 1232679Sktlim@umich.edu 1242679Sktlim@umich.edu Port *icachePort; 1252679Sktlim@umich.edu 1262679Sktlim@umich.edu void setDcachePort(Port *dcache_port); 1272679Sktlim@umich.edu 1282679Sktlim@umich.edu Port *dcachePort; 1292679Sktlim@umich.edu 1302871Sktlim@umich.edu virtual Port *getPort(const std::string &name, int idx) 1312871Sktlim@umich.edu { 1322871Sktlim@umich.edu panic("Not supported on checker!"); 1332871Sktlim@umich.edu return NULL; 1342871Sktlim@umich.edu } 1352871Sktlim@umich.edu 1362315SN/A public: 1372683Sktlim@umich.edu // Primary thread being run. 1382683Sktlim@umich.edu SimpleThread *thread; 1392315SN/A 1402680Sktlim@umich.edu ThreadContext *tc; 1412315SN/A 1423468Sgblack@eecs.umich.edu TheISA::ITB *itb; 1433468Sgblack@eecs.umich.edu TheISA::DTB *dtb; 1442315SN/A 1452315SN/A#if FULL_SYSTEM 1462315SN/A Addr dbg_vtophys(Addr addr); 1472315SN/A#endif 1482315SN/A 1492315SN/A union Result { 1502315SN/A uint64_t integer; 1512360SN/A// float fp; 1522315SN/A double dbl; 1532315SN/A }; 1542315SN/A 1552315SN/A Result result; 1562315SN/A 1572315SN/A // current instruction 1582315SN/A MachInst machInst; 1592315SN/A 1602679Sktlim@umich.edu // Pointer to the one memory request. 1612679Sktlim@umich.edu RequestPtr memReq; 1622315SN/A 1632315SN/A StaticInstPtr curStaticInst; 1642315SN/A 1652315SN/A // number of simulated instructions 1662315SN/A Counter numInst; 1672315SN/A Counter startNumInst; 1682315SN/A 1692315SN/A std::queue<int> miscRegIdxs; 1702315SN/A 1712315SN/A virtual Counter totalInstructions() const 1722315SN/A { 1732930Sktlim@umich.edu return 0; 1742315SN/A } 1752315SN/A 1762315SN/A // number of simulated loads 1772315SN/A Counter numLoad; 1782315SN/A Counter startNumLoad; 1792315SN/A 1802315SN/A virtual void serialize(std::ostream &os); 1812315SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 1822315SN/A 1832315SN/A template <class T> 1842315SN/A Fault read(Addr addr, T &data, unsigned flags); 1852315SN/A 1862315SN/A template <class T> 1872315SN/A Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 1882315SN/A 1892315SN/A // These functions are only used in CPU models that split 1902315SN/A // effective address computation from the actual memory access. 1912315SN/A void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); } 1922315SN/A Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); } 1932315SN/A 1942315SN/A void prefetch(Addr addr, unsigned flags) 1952315SN/A { 1962315SN/A // need to do this... 1972315SN/A } 1982315SN/A 1992315SN/A void writeHint(Addr addr, int size, unsigned flags) 2002315SN/A { 2012315SN/A // need to do this... 2022315SN/A } 2032315SN/A 2042315SN/A Fault copySrcTranslate(Addr src); 2052315SN/A 2062315SN/A Fault copy(Addr dest); 2072315SN/A 2082315SN/A // The register accessor methods provide the index of the 2092315SN/A // instruction's operand (e.g., 0 or 1), not the architectural 2102315SN/A // register index, to simplify the implementation of register 2112315SN/A // renaming. We find the architectural register index by indexing 2122315SN/A // into the instruction's own operand index table. Note that a 2132315SN/A // raw pointer to the StaticInst is provided instead of a 2142315SN/A // ref-counted StaticInstPtr to redice overhead. This is fine as 2152315SN/A // long as these methods don't copy the pointer into any long-term 2162315SN/A // storage (which is pretty hard to imagine they would have reason 2172315SN/A // to do). 2182315SN/A 2193735Sstever@eecs.umich.edu uint64_t readIntRegOperand(const StaticInst *si, int idx) 2202315SN/A { 2212683Sktlim@umich.edu return thread->readIntReg(si->srcRegIdx(idx)); 2222315SN/A } 2232315SN/A 2243735Sstever@eecs.umich.edu FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width) 2252315SN/A { 2262315SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2272683Sktlim@umich.edu return thread->readFloatReg(reg_idx, width); 2282315SN/A } 2292315SN/A 2303735Sstever@eecs.umich.edu FloatReg readFloatRegOperand(const StaticInst *si, int idx) 2312315SN/A { 2322315SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2332683Sktlim@umich.edu return thread->readFloatReg(reg_idx); 2342315SN/A } 2352315SN/A 2363735Sstever@eecs.umich.edu FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx, 2373735Sstever@eecs.umich.edu int width) 2382315SN/A { 2392315SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2402683Sktlim@umich.edu return thread->readFloatRegBits(reg_idx, width); 2412669Sktlim@umich.edu } 2422669Sktlim@umich.edu 2433735Sstever@eecs.umich.edu FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 2442669Sktlim@umich.edu { 2452669Sktlim@umich.edu int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2462683Sktlim@umich.edu return thread->readFloatRegBits(reg_idx); 2472315SN/A } 2482315SN/A 2493735Sstever@eecs.umich.edu void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 2502315SN/A { 2512683Sktlim@umich.edu thread->setIntReg(si->destRegIdx(idx), val); 2522315SN/A result.integer = val; 2532315SN/A } 2542315SN/A 2553735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 2563735Sstever@eecs.umich.edu int width) 2572315SN/A { 2582315SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2592683Sktlim@umich.edu thread->setFloatReg(reg_idx, val, width); 2602669Sktlim@umich.edu switch(width) { 2612669Sktlim@umich.edu case 32: 2623126Sktlim@umich.edu result.dbl = (double)val; 2632669Sktlim@umich.edu break; 2642669Sktlim@umich.edu case 64: 2652669Sktlim@umich.edu result.dbl = val; 2662669Sktlim@umich.edu break; 2672669Sktlim@umich.edu }; 2682669Sktlim@umich.edu } 2692669Sktlim@umich.edu 2703735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 2712669Sktlim@umich.edu { 2722669Sktlim@umich.edu int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2732683Sktlim@umich.edu thread->setFloatReg(reg_idx, val); 2742360SN/A result.dbl = (double)val; 2752315SN/A } 2762315SN/A 2773735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, 2783735Sstever@eecs.umich.edu FloatRegBits val, int width) 2792315SN/A { 2802315SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2812683Sktlim@umich.edu thread->setFloatRegBits(reg_idx, val, width); 2822669Sktlim@umich.edu result.integer = val; 2832315SN/A } 2842315SN/A 2853735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, 2863735Sstever@eecs.umich.edu FloatRegBits val) 2872315SN/A { 2882315SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2892683Sktlim@umich.edu thread->setFloatRegBits(reg_idx, val); 2902315SN/A result.integer = val; 2912315SN/A } 2922315SN/A 2932683Sktlim@umich.edu uint64_t readPC() { return thread->readPC(); } 2942669Sktlim@umich.edu 2952683Sktlim@umich.edu uint64_t readNextPC() { return thread->readNextPC(); } 2962669Sktlim@umich.edu 2972315SN/A void setNextPC(uint64_t val) { 2982683Sktlim@umich.edu thread->setNextPC(val); 2992315SN/A } 3002315SN/A 3012315SN/A MiscReg readMiscReg(int misc_reg) 3022315SN/A { 3032683Sktlim@umich.edu return thread->readMiscReg(misc_reg); 3042315SN/A } 3052315SN/A 3063468Sgblack@eecs.umich.edu MiscReg readMiscRegWithEffect(int misc_reg) 3072315SN/A { 3083468Sgblack@eecs.umich.edu return thread->readMiscRegWithEffect(misc_reg); 3092315SN/A } 3102315SN/A 3113468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 3122315SN/A { 3132315SN/A result.integer = val; 3142315SN/A miscRegIdxs.push(misc_reg); 3152683Sktlim@umich.edu return thread->setMiscReg(misc_reg, val); 3162315SN/A } 3172315SN/A 3183468Sgblack@eecs.umich.edu void setMiscRegWithEffect(int misc_reg, const MiscReg &val) 3192315SN/A { 3202315SN/A miscRegIdxs.push(misc_reg); 3212683Sktlim@umich.edu return thread->setMiscRegWithEffect(misc_reg, val); 3222315SN/A } 3232315SN/A 3242360SN/A void recordPCChange(uint64_t val) { changedPC = true; newPC = val; } 3252315SN/A void recordNextPCChange(uint64_t val) { changedNextPC = true; } 3262315SN/A 3272669Sktlim@umich.edu bool translateInstReq(Request *req); 3282669Sktlim@umich.edu void translateDataWriteReq(Request *req); 3292669Sktlim@umich.edu void translateDataReadReq(Request *req); 3302315SN/A 3312315SN/A#if FULL_SYSTEM 3322683Sktlim@umich.edu Fault hwrei() { return thread->hwrei(); } 3332690Sktlim@umich.edu void ev5_trap(Fault fault) { fault->invoke(tc); } 3342683Sktlim@umich.edu bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 3352315SN/A#else 3362315SN/A // Assume that the normal CPU's call to syscall was successful. 3372332SN/A // The checker's state would have already been updated by the syscall. 3382669Sktlim@umich.edu void syscall(uint64_t callnum) { } 3392315SN/A#endif 3402315SN/A 3412315SN/A void handleError() 3422315SN/A { 3432315SN/A if (exitOnError) 3442732Sktlim@umich.edu dumpAndExit(); 3452315SN/A } 3462732Sktlim@umich.edu 3472669Sktlim@umich.edu bool checkFlags(Request *req); 3482315SN/A 3492732Sktlim@umich.edu void dumpAndExit(); 3502732Sktlim@umich.edu 3512680Sktlim@umich.edu ThreadContext *tcBase() { return tc; } 3522683Sktlim@umich.edu SimpleThread *threadBase() { return thread; } 3532315SN/A 3542315SN/A Result unverifiedResult; 3552669Sktlim@umich.edu Request *unverifiedReq; 3562679Sktlim@umich.edu uint8_t *unverifiedMemData; 3572315SN/A 3582315SN/A bool changedPC; 3592315SN/A bool willChangePC; 3602315SN/A uint64_t newPC; 3612315SN/A bool changedNextPC; 3622315SN/A bool exitOnError; 3632354SN/A bool updateOnError; 3642732Sktlim@umich.edu bool warnOnlyOnLoadError; 3652315SN/A 3662315SN/A InstSeqNum youngestSN; 3672315SN/A}; 3682315SN/A 3692350SN/A/** 3702350SN/A * Templated Checker class. This Checker class is templated on the 3712350SN/A * DynInstPtr of the instruction type that will be verified. Proper 3722350SN/A * template instantiations of the Checker must be placed at the bottom 3732350SN/A * of checker/cpu.cc. 3742350SN/A */ 3752315SN/Atemplate <class DynInstPtr> 3762315SN/Aclass Checker : public CheckerCPU 3772315SN/A{ 3782315SN/A public: 3792315SN/A Checker(Params *p) 3802354SN/A : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL) 3812315SN/A { } 3822315SN/A 3832840Sktlim@umich.edu void switchOut(); 3842315SN/A void takeOverFrom(BaseCPU *oldCPU); 3852315SN/A 3862732Sktlim@umich.edu void verify(DynInstPtr &inst); 3872315SN/A 3882315SN/A void validateInst(DynInstPtr &inst); 3892315SN/A void validateExecution(DynInstPtr &inst); 3902315SN/A void validateState(); 3912315SN/A 3922732Sktlim@umich.edu void copyResult(DynInstPtr &inst); 3932732Sktlim@umich.edu 3942732Sktlim@umich.edu private: 3952732Sktlim@umich.edu void handleError(DynInstPtr &inst) 3962732Sktlim@umich.edu { 3972360SN/A if (exitOnError) { 3982732Sktlim@umich.edu dumpAndExit(inst); 3992360SN/A } else if (updateOnError) { 4002354SN/A updateThisCycle = true; 4012360SN/A } 4022732Sktlim@umich.edu } 4032732Sktlim@umich.edu 4042732Sktlim@umich.edu void dumpAndExit(DynInstPtr &inst); 4052732Sktlim@umich.edu 4062354SN/A bool updateThisCycle; 4072354SN/A 4082354SN/A DynInstPtr unverifiedInst; 4092354SN/A 4102315SN/A std::list<DynInstPtr> instList; 4112315SN/A typedef typename std::list<DynInstPtr>::iterator InstListIt; 4122315SN/A void dumpInsts(); 4132315SN/A}; 4142315SN/A 4152315SN/A#endif // __CPU_CHECKER_CPU_HH__ 416