cpu.hh revision 2669
12315SN/A/* 22332SN/A * Copyright (c) 2006 The Regents of The University of Michigan 32315SN/A * All rights reserved. 42315SN/A * 52315SN/A * Redistribution and use in source and binary forms, with or without 62315SN/A * modification, are permitted provided that the following conditions are 72315SN/A * met: redistributions of source code must retain the above copyright 82315SN/A * notice, this list of conditions and the following disclaimer; 92315SN/A * redistributions in binary form must reproduce the above copyright 102315SN/A * notice, this list of conditions and the following disclaimer in the 112315SN/A * documentation and/or other materials provided with the distribution; 122315SN/A * neither the name of the copyright holders nor the names of its 132315SN/A * contributors may be used to endorse or promote products derived from 142315SN/A * this software without specific prior written permission. 152315SN/A * 162315SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172315SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182315SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192315SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202315SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212315SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222315SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232315SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242315SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252315SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262315SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272315SN/A */ 282315SN/A 292315SN/A#ifndef __CPU_CHECKER_CPU_HH__ 302315SN/A#define __CPU_CHECKER_CPU_HH__ 312315SN/A 322315SN/A#include <list> 332315SN/A#include <queue> 342315SN/A#include <map> 352315SN/A 362669Sktlim@umich.edu#include "arch/types.hh" 372315SN/A#include "base/statistics.hh" 382315SN/A#include "config/full_system.hh" 392315SN/A#include "cpu/base.hh" 402315SN/A#include "cpu/base_dyn_inst.hh" 412315SN/A#include "cpu/cpu_exec_context.hh" 422315SN/A#include "cpu/pc_event.hh" 432315SN/A#include "cpu/static_inst.hh" 442315SN/A#include "sim/eventq.hh" 452315SN/A 462315SN/A// forward declarations 472315SN/A#if FULL_SYSTEM 482315SN/Aclass Processor; 492315SN/Aclass AlphaITB; 502315SN/Aclass AlphaDTB; 512315SN/Aclass PhysicalMemory; 522315SN/A 532315SN/Aclass RemoteGDB; 542315SN/Aclass GDBListener; 552315SN/A 562315SN/A#else 572315SN/A 582315SN/Aclass Process; 592315SN/A 602315SN/A#endif // FULL_SYSTEM 612315SN/Atemplate <class> 622315SN/Aclass BaseDynInst; 632315SN/Aclass ExecContext; 642315SN/Aclass MemInterface; 652315SN/Aclass Checkpoint; 662669Sktlim@umich.educlass Request; 672332SN/Aclass Sampler; 682315SN/A 692315SN/Aclass CheckerCPU : public BaseCPU 702315SN/A{ 712315SN/A protected: 722315SN/A typedef TheISA::MachInst MachInst; 732669Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 742669Sktlim@umich.edu typedef TheISA::FloatRegBits FloatRegBits; 752315SN/A typedef TheISA::MiscReg MiscReg; 762315SN/A public: 772315SN/A // main simulation loop (one cycle) 782315SN/A virtual void init(); 792315SN/A 802315SN/A struct Params : public BaseCPU::Params 812315SN/A { 822315SN/A#if FULL_SYSTEM 832315SN/A AlphaITB *itb; 842315SN/A AlphaDTB *dtb; 852315SN/A FunctionalMemory *mem; 862315SN/A#else 872315SN/A Process *process; 882315SN/A#endif 892315SN/A bool exitOnError; 902315SN/A }; 912315SN/A 922315SN/A public: 932315SN/A CheckerCPU(Params *p); 942315SN/A virtual ~CheckerCPU(); 952315SN/A 962669Sktlim@umich.edu void setMemory(MemObject *mem); 972315SN/A 982669Sktlim@umich.edu MemObject *memPtr; 992315SN/A 1002315SN/A#if FULL_SYSTEM 1012315SN/A void setSystem(System *system); 1022315SN/A 1032315SN/A System *systemPtr; 1042315SN/A#endif 1052315SN/A public: 1062315SN/A // execution context 1072315SN/A CPUExecContext *cpuXC; 1082315SN/A 1092315SN/A ExecContext *xcProxy; 1102315SN/A 1112315SN/A AlphaITB *itb; 1122315SN/A AlphaDTB *dtb; 1132315SN/A 1142315SN/A#if FULL_SYSTEM 1152315SN/A Addr dbg_vtophys(Addr addr); 1162315SN/A#endif 1172315SN/A 1182315SN/A union Result { 1192315SN/A uint64_t integer; 1202315SN/A float fp; 1212315SN/A double dbl; 1222315SN/A }; 1232315SN/A 1242315SN/A Result result; 1252315SN/A 1262315SN/A // current instruction 1272315SN/A MachInst machInst; 1282315SN/A 1292315SN/A // Refcounted pointer to the one memory request. 1302669Sktlim@umich.edu Request *memReq; 1312315SN/A 1322315SN/A StaticInstPtr curStaticInst; 1332315SN/A 1342315SN/A // number of simulated instructions 1352315SN/A Counter numInst; 1362315SN/A Counter startNumInst; 1372315SN/A 1382315SN/A std::queue<int> miscRegIdxs; 1392315SN/A 1402315SN/A virtual Counter totalInstructions() const 1412315SN/A { 1422315SN/A return numInst - startNumInst; 1432315SN/A } 1442315SN/A 1452315SN/A // number of simulated loads 1462315SN/A Counter numLoad; 1472315SN/A Counter startNumLoad; 1482315SN/A 1492315SN/A virtual void serialize(std::ostream &os); 1502315SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 1512315SN/A 1522315SN/A template <class T> 1532315SN/A Fault read(Addr addr, T &data, unsigned flags); 1542315SN/A 1552315SN/A template <class T> 1562315SN/A Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 1572315SN/A 1582315SN/A // These functions are only used in CPU models that split 1592315SN/A // effective address computation from the actual memory access. 1602315SN/A void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); } 1612315SN/A Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); } 1622315SN/A 1632315SN/A void prefetch(Addr addr, unsigned flags) 1642315SN/A { 1652315SN/A // need to do this... 1662315SN/A } 1672315SN/A 1682315SN/A void writeHint(Addr addr, int size, unsigned flags) 1692315SN/A { 1702315SN/A // need to do this... 1712315SN/A } 1722315SN/A 1732315SN/A Fault copySrcTranslate(Addr src); 1742315SN/A 1752315SN/A Fault copy(Addr dest); 1762315SN/A 1772315SN/A // The register accessor methods provide the index of the 1782315SN/A // instruction's operand (e.g., 0 or 1), not the architectural 1792315SN/A // register index, to simplify the implementation of register 1802315SN/A // renaming. We find the architectural register index by indexing 1812315SN/A // into the instruction's own operand index table. Note that a 1822315SN/A // raw pointer to the StaticInst is provided instead of a 1832315SN/A // ref-counted StaticInstPtr to redice overhead. This is fine as 1842315SN/A // long as these methods don't copy the pointer into any long-term 1852315SN/A // storage (which is pretty hard to imagine they would have reason 1862315SN/A // to do). 1872315SN/A 1882315SN/A uint64_t readIntReg(const StaticInst *si, int idx) 1892315SN/A { 1902315SN/A return cpuXC->readIntReg(si->srcRegIdx(idx)); 1912315SN/A } 1922315SN/A 1932669Sktlim@umich.edu FloatReg readFloatReg(const StaticInst *si, int idx, int width) 1942315SN/A { 1952315SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 1962669Sktlim@umich.edu return cpuXC->readFloatReg(reg_idx, width); 1972315SN/A } 1982315SN/A 1992669Sktlim@umich.edu FloatReg readFloatReg(const StaticInst *si, int idx) 2002315SN/A { 2012315SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2022669Sktlim@umich.edu return cpuXC->readFloatReg(reg_idx); 2032315SN/A } 2042315SN/A 2052669Sktlim@umich.edu FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width) 2062315SN/A { 2072315SN/A int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2082669Sktlim@umich.edu return cpuXC->readFloatRegBits(reg_idx, width); 2092669Sktlim@umich.edu } 2102669Sktlim@umich.edu 2112669Sktlim@umich.edu FloatRegBits readFloatRegBits(const StaticInst *si, int idx) 2122669Sktlim@umich.edu { 2132669Sktlim@umich.edu int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 2142669Sktlim@umich.edu return cpuXC->readFloatRegBits(reg_idx); 2152315SN/A } 2162315SN/A 2172315SN/A void setIntReg(const StaticInst *si, int idx, uint64_t val) 2182315SN/A { 2192315SN/A cpuXC->setIntReg(si->destRegIdx(idx), val); 2202315SN/A result.integer = val; 2212315SN/A } 2222315SN/A 2232669Sktlim@umich.edu void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width) 2242315SN/A { 2252315SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2262669Sktlim@umich.edu cpuXC->setFloatReg(reg_idx, val, width); 2272669Sktlim@umich.edu switch(width) { 2282669Sktlim@umich.edu case 32: 2292669Sktlim@umich.edu result.fp = val; 2302669Sktlim@umich.edu break; 2312669Sktlim@umich.edu case 64: 2322669Sktlim@umich.edu result.dbl = val; 2332669Sktlim@umich.edu break; 2342669Sktlim@umich.edu }; 2352669Sktlim@umich.edu } 2362669Sktlim@umich.edu 2372669Sktlim@umich.edu void setFloatReg(const StaticInst *si, int idx, FloatReg val) 2382669Sktlim@umich.edu { 2392669Sktlim@umich.edu int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2402669Sktlim@umich.edu cpuXC->setFloatReg(reg_idx, val); 2412315SN/A result.fp = val; 2422315SN/A } 2432315SN/A 2442669Sktlim@umich.edu void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val, 2452669Sktlim@umich.edu int width) 2462315SN/A { 2472315SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2482669Sktlim@umich.edu cpuXC->setFloatRegBits(reg_idx, val, width); 2492669Sktlim@umich.edu result.integer = val; 2502315SN/A } 2512315SN/A 2522669Sktlim@umich.edu void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val) 2532315SN/A { 2542315SN/A int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 2552669Sktlim@umich.edu cpuXC->setFloatRegBits(reg_idx, val); 2562315SN/A result.integer = val; 2572315SN/A } 2582315SN/A 2592315SN/A uint64_t readPC() { return cpuXC->readPC(); } 2602669Sktlim@umich.edu 2612669Sktlim@umich.edu uint64_t readNextPC() { return cpuXC->readNextPC(); } 2622669Sktlim@umich.edu 2632315SN/A void setNextPC(uint64_t val) { 2642315SN/A cpuXC->setNextPC(val); 2652315SN/A } 2662315SN/A 2672315SN/A MiscReg readMiscReg(int misc_reg) 2682315SN/A { 2692315SN/A return cpuXC->readMiscReg(misc_reg); 2702315SN/A } 2712315SN/A 2722315SN/A MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) 2732315SN/A { 2742315SN/A return cpuXC->readMiscRegWithEffect(misc_reg, fault); 2752315SN/A } 2762315SN/A 2772315SN/A Fault setMiscReg(int misc_reg, const MiscReg &val) 2782315SN/A { 2792315SN/A result.integer = val; 2802315SN/A miscRegIdxs.push(misc_reg); 2812315SN/A return cpuXC->setMiscReg(misc_reg, val); 2822315SN/A } 2832315SN/A 2842315SN/A Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) 2852315SN/A { 2862315SN/A miscRegIdxs.push(misc_reg); 2872315SN/A return cpuXC->setMiscRegWithEffect(misc_reg, val); 2882315SN/A } 2892315SN/A 2902315SN/A void recordPCChange(uint64_t val) { changedPC = true; } 2912315SN/A void recordNextPCChange(uint64_t val) { changedNextPC = true; } 2922315SN/A 2932669Sktlim@umich.edu bool translateInstReq(Request *req); 2942669Sktlim@umich.edu void translateDataWriteReq(Request *req); 2952669Sktlim@umich.edu void translateDataReadReq(Request *req); 2962315SN/A 2972315SN/A#if FULL_SYSTEM 2982315SN/A Fault hwrei() { return cpuXC->hwrei(); } 2992315SN/A int readIntrFlag() { return cpuXC->readIntrFlag(); } 3002315SN/A void setIntrFlag(int val) { cpuXC->setIntrFlag(val); } 3012315SN/A bool inPalMode() { return cpuXC->inPalMode(); } 3022315SN/A void ev5_trap(Fault fault) { fault->invoke(xcProxy); } 3032315SN/A bool simPalCheck(int palFunc) { return cpuXC->simPalCheck(palFunc); } 3042315SN/A#else 3052315SN/A // Assume that the normal CPU's call to syscall was successful. 3062332SN/A // The checker's state would have already been updated by the syscall. 3072669Sktlim@umich.edu void syscall(uint64_t callnum) { } 3082315SN/A#endif 3092315SN/A 3102315SN/A void handleError() 3112315SN/A { 3122315SN/A if (exitOnError) 3132315SN/A panic("Checker found error!"); 3142315SN/A } 3152669Sktlim@umich.edu bool checkFlags(Request *req); 3162315SN/A 3172315SN/A ExecContext *xcBase() { return xcProxy; } 3182315SN/A CPUExecContext *cpuXCBase() { return cpuXC; } 3192315SN/A 3202315SN/A Result unverifiedResult; 3212669Sktlim@umich.edu Request *unverifiedReq; 3222315SN/A 3232315SN/A bool changedPC; 3242315SN/A bool willChangePC; 3252315SN/A uint64_t newPC; 3262315SN/A bool changedNextPC; 3272315SN/A bool exitOnError; 3282315SN/A 3292315SN/A InstSeqNum youngestSN; 3302315SN/A}; 3312315SN/A 3322315SN/Atemplate <class DynInstPtr> 3332315SN/Aclass Checker : public CheckerCPU 3342315SN/A{ 3352315SN/A public: 3362315SN/A Checker(Params *p) 3372315SN/A : CheckerCPU(p) 3382315SN/A { } 3392315SN/A 3402315SN/A void switchOut(Sampler *s); 3412315SN/A void takeOverFrom(BaseCPU *oldCPU); 3422315SN/A 3432315SN/A void tick(DynInstPtr &inst); 3442315SN/A 3452315SN/A void validateInst(DynInstPtr &inst); 3462315SN/A void validateExecution(DynInstPtr &inst); 3472315SN/A void validateState(); 3482315SN/A 3492315SN/A std::list<DynInstPtr> instList; 3502315SN/A typedef typename std::list<DynInstPtr>::iterator InstListIt; 3512315SN/A void dumpInsts(); 3522315SN/A}; 3532315SN/A 3542315SN/A#endif // __CPU_CHECKER_CPU_HH__ 355