cpu.hh revision 12107
12315SN/A/* 212107SRekai.GonzalezAlberquilla@arm.com * Copyright (c) 2011, 2016 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48733Sgeoffrey.blake@arm.com * All rights reserved 58733Sgeoffrey.blake@arm.com * 68733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 78733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 88733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 98733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 108733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 118733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 128733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 138733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 148733Sgeoffrey.blake@arm.com * 152332SN/A * Copyright (c) 2006 The Regents of The University of Michigan 162315SN/A * All rights reserved. 172315SN/A * 182315SN/A * Redistribution and use in source and binary forms, with or without 192315SN/A * modification, are permitted provided that the following conditions are 202315SN/A * met: redistributions of source code must retain the above copyright 212315SN/A * notice, this list of conditions and the following disclaimer; 222315SN/A * redistributions in binary form must reproduce the above copyright 232315SN/A * notice, this list of conditions and the following disclaimer in the 242315SN/A * documentation and/or other materials provided with the distribution; 252315SN/A * neither the name of the copyright holders nor the names of its 262315SN/A * contributors may be used to endorse or promote products derived from 272315SN/A * this software without specific prior written permission. 282315SN/A * 292315SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302315SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312315SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322315SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332315SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342315SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352315SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362315SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372315SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382315SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392315SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402689Sktlim@umich.edu * 412689Sktlim@umich.edu * Authors: Kevin Lim 422315SN/A */ 432315SN/A 442315SN/A#ifndef __CPU_CHECKER_CPU_HH__ 452315SN/A#define __CPU_CHECKER_CPU_HH__ 462315SN/A 472315SN/A#include <list> 488229Snate@binkert.org#include <map> 492315SN/A#include <queue> 502315SN/A 512669Sktlim@umich.edu#include "arch/types.hh" 522315SN/A#include "base/statistics.hh" 532315SN/A#include "cpu/base.hh" 542315SN/A#include "cpu/base_dyn_inst.hh" 5510319SAndreas.Sandberg@ARM.com#include "cpu/exec_context.hh" 5612107SRekai.GonzalezAlberquilla@arm.com#include "cpu/inst_res.hh" 578229Snate@binkert.org#include "cpu/pc_event.hh" 582683Sktlim@umich.edu#include "cpu/simple_thread.hh" 592315SN/A#include "cpu/static_inst.hh" 608733Sgeoffrey.blake@arm.com#include "debug/Checker.hh" 6111608Snikos.nikoleris@arm.com#include "mem/request.hh" 628733Sgeoffrey.blake@arm.com#include "params/CheckerCPU.hh" 632315SN/A#include "sim/eventq.hh" 642315SN/A 652315SN/A// forward declarations 663468Sgblack@eecs.umich.edunamespace TheISA 673468Sgblack@eecs.umich.edu{ 686022Sgblack@eecs.umich.edu class TLB; 693468Sgblack@eecs.umich.edu} 702315SN/A 712315SN/Atemplate <class> 722315SN/Aclass BaseDynInst; 732680Sktlim@umich.educlass ThreadContext; 742669Sktlim@umich.educlass Request; 752315SN/A 762350SN/A/** 772350SN/A * CheckerCPU class. Dynamically verifies instructions as they are 782350SN/A * completed by making sure that the instruction and its results match 792350SN/A * the independent execution of the benchmark inside the checker. The 802350SN/A * checker verifies instructions in order, regardless of the order in 812350SN/A * which instructions complete. There are certain results that can 822350SN/A * not be verified, specifically the result of a store conditional or 832350SN/A * the values of uncached accesses. In these cases, and with 842350SN/A * instructions marked as "IsUnverifiable", the checker assumes that 852350SN/A * the value from the main CPU's execution is correct and simply 862680Sktlim@umich.edu * copies that value. It provides a CheckerThreadContext (see 872683Sktlim@umich.edu * checker/thread_context.hh) that provides hooks for updating the 882680Sktlim@umich.edu * Checker's state through any ThreadContext accesses. This allows the 892350SN/A * checker to be able to correctly verify instructions, even with 902680Sktlim@umich.edu * external accesses to the ThreadContext that change state. 912350SN/A */ 9210319SAndreas.Sandberg@ARM.comclass CheckerCPU : public BaseCPU, public ExecContext 932315SN/A{ 942315SN/A protected: 952315SN/A typedef TheISA::MachInst MachInst; 962669Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 972669Sktlim@umich.edu typedef TheISA::FloatRegBits FloatRegBits; 982315SN/A typedef TheISA::MiscReg MiscReg; 998832SAli.Saidi@ARM.com 1008832SAli.Saidi@ARM.com /** id attached to all issued requests */ 1018832SAli.Saidi@ARM.com MasterID masterId; 1022315SN/A public: 10311169Sandreas.hansson@arm.com void init() override; 1042315SN/A 1055529Snate@binkert.org typedef CheckerCPUParams Params; 1062315SN/A CheckerCPU(Params *p); 1072315SN/A virtual ~CheckerCPU(); 1082315SN/A 1092315SN/A void setSystem(System *system); 1102315SN/A 1119608Sandreas.hansson@arm.com void setIcachePort(MasterPort *icache_port); 1122679Sktlim@umich.edu 1139608Sandreas.hansson@arm.com void setDcachePort(MasterPort *dcache_port); 1142679Sktlim@umich.edu 11511169Sandreas.hansson@arm.com MasterPort &getDataPort() override 1168887Sgeoffrey.blake@arm.com { 1179176Sandreas.hansson@arm.com // the checker does not have ports on its own so return the 1189176Sandreas.hansson@arm.com // data port of the actual CPU core 1199176Sandreas.hansson@arm.com assert(dcachePort); 1208887Sgeoffrey.blake@arm.com return *dcachePort; 1218887Sgeoffrey.blake@arm.com } 1228887Sgeoffrey.blake@arm.com 12311169Sandreas.hansson@arm.com MasterPort &getInstPort() override 1248887Sgeoffrey.blake@arm.com { 1259176Sandreas.hansson@arm.com // the checker does not have ports on its own so return the 1269176Sandreas.hansson@arm.com // data port of the actual CPU core 1279176Sandreas.hansson@arm.com assert(icachePort); 1288887Sgeoffrey.blake@arm.com return *icachePort; 1298887Sgeoffrey.blake@arm.com } 1302679Sktlim@umich.edu 1319176Sandreas.hansson@arm.com protected: 1329176Sandreas.hansson@arm.com 1339176Sandreas.hansson@arm.com std::vector<Process*> workload; 1349176Sandreas.hansson@arm.com 1359176Sandreas.hansson@arm.com System *systemPtr; 1369176Sandreas.hansson@arm.com 1379608Sandreas.hansson@arm.com MasterPort *icachePort; 1389608Sandreas.hansson@arm.com MasterPort *dcachePort; 1392315SN/A 1402680Sktlim@umich.edu ThreadContext *tc; 1412315SN/A 1426022Sgblack@eecs.umich.edu TheISA::TLB *itb; 1436022Sgblack@eecs.umich.edu TheISA::TLB *dtb; 1442315SN/A 1452315SN/A Addr dbg_vtophys(Addr addr); 1462315SN/A 1478733Sgeoffrey.blake@arm.com // ISAs like ARM can have multiple destination registers to check, 1488733Sgeoffrey.blake@arm.com // keep them all in a std::queue 14912107SRekai.GonzalezAlberquilla@arm.com std::queue<InstResult> result; 1502315SN/A 1512679Sktlim@umich.edu // Pointer to the one memory request. 1522679Sktlim@umich.edu RequestPtr memReq; 1532315SN/A 1542315SN/A StaticInstPtr curStaticInst; 1558733Sgeoffrey.blake@arm.com StaticInstPtr curMacroStaticInst; 1562315SN/A 1572315SN/A // number of simulated instructions 1582315SN/A Counter numInst; 1592315SN/A Counter startNumInst; 1602315SN/A 1612315SN/A std::queue<int> miscRegIdxs; 1622315SN/A 1639176Sandreas.hansson@arm.com public: 1649176Sandreas.hansson@arm.com 1659176Sandreas.hansson@arm.com // Primary thread being run. 1669176Sandreas.hansson@arm.com SimpleThread *thread; 1679176Sandreas.hansson@arm.com 1688733Sgeoffrey.blake@arm.com TheISA::TLB* getITBPtr() { return itb; } 1698733Sgeoffrey.blake@arm.com TheISA::TLB* getDTBPtr() { return dtb; } 1708733Sgeoffrey.blake@arm.com 17111169Sandreas.hansson@arm.com virtual Counter totalInsts() const override 1728887Sgeoffrey.blake@arm.com { 1738887Sgeoffrey.blake@arm.com return 0; 1748887Sgeoffrey.blake@arm.com } 1758887Sgeoffrey.blake@arm.com 17611169Sandreas.hansson@arm.com virtual Counter totalOps() const override 1772315SN/A { 1782930Sktlim@umich.edu return 0; 1792315SN/A } 1802315SN/A 1812315SN/A // number of simulated loads 1822315SN/A Counter numLoad; 1832315SN/A Counter startNumLoad; 1842315SN/A 18511168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 18611168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 1872315SN/A 1882315SN/A // These functions are only used in CPU models that split 1892315SN/A // effective address computation from the actual memory access. 19011169Sandreas.hansson@arm.com void setEA(Addr EA) override 19111169Sandreas.hansson@arm.com { panic("CheckerCPU::setEA() not implemented\n"); } 19211169Sandreas.hansson@arm.com Addr getEA() const override 19311169Sandreas.hansson@arm.com { panic("CheckerCPU::getEA() not implemented\n"); } 1942315SN/A 1952315SN/A // The register accessor methods provide the index of the 1962315SN/A // instruction's operand (e.g., 0 or 1), not the architectural 1972315SN/A // register index, to simplify the implementation of register 1982315SN/A // renaming. We find the architectural register index by indexing 1992315SN/A // into the instruction's own operand index table. Note that a 2002315SN/A // raw pointer to the StaticInst is provided instead of a 2012315SN/A // ref-counted StaticInstPtr to redice overhead. This is fine as 2022315SN/A // long as these methods don't copy the pointer into any long-term 2032315SN/A // storage (which is pretty hard to imagine they would have reason 2042315SN/A // to do). 2052315SN/A 20611169Sandreas.hansson@arm.com IntReg readIntRegOperand(const StaticInst *si, int idx) override 2072315SN/A { 20812106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 20912106SRekai.GonzalezAlberquilla@arm.com assert(reg.isIntReg()); 21012106SRekai.GonzalezAlberquilla@arm.com return thread->readIntReg(reg.index()); 2112315SN/A } 2122315SN/A 21311169Sandreas.hansson@arm.com FloatReg readFloatRegOperand(const StaticInst *si, int idx) override 2142315SN/A { 21512106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 21612106SRekai.GonzalezAlberquilla@arm.com assert(reg.isFloatReg()); 21712106SRekai.GonzalezAlberquilla@arm.com return thread->readFloatReg(reg.index()); 2182315SN/A } 2192315SN/A 22011169Sandreas.hansson@arm.com FloatRegBits readFloatRegOperandBits(const StaticInst *si, 22111169Sandreas.hansson@arm.com int idx) override 2222669Sktlim@umich.edu { 22312106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 22412106SRekai.GonzalezAlberquilla@arm.com assert(reg.isFloatReg()); 22512106SRekai.GonzalezAlberquilla@arm.com return thread->readFloatRegBits(reg.index()); 2262315SN/A } 2272315SN/A 22811169Sandreas.hansson@arm.com CCReg readCCRegOperand(const StaticInst *si, int idx) override 2299920Syasuko.eckert@amd.com { 23012106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 23112106SRekai.GonzalezAlberquilla@arm.com assert(reg.isCCReg()); 23212106SRekai.GonzalezAlberquilla@arm.com return thread->readCCReg(reg.index()); 2339920Syasuko.eckert@amd.com } 2349920Syasuko.eckert@amd.com 23512107SRekai.GonzalezAlberquilla@arm.com template<typename T> 23612107SRekai.GonzalezAlberquilla@arm.com void setScalarResult(T&& t) 2378733Sgeoffrey.blake@arm.com { 23812107SRekai.GonzalezAlberquilla@arm.com result.push(InstResult(std::forward<T>(t), 23912107SRekai.GonzalezAlberquilla@arm.com InstResult::ResultType::Scalar)); 2408733Sgeoffrey.blake@arm.com } 2418733Sgeoffrey.blake@arm.com 24211169Sandreas.hansson@arm.com void setIntRegOperand(const StaticInst *si, int idx, 24311169Sandreas.hansson@arm.com IntReg val) override 2442315SN/A { 24512106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 24612106SRekai.GonzalezAlberquilla@arm.com assert(reg.isIntReg()); 24712106SRekai.GonzalezAlberquilla@arm.com thread->setIntReg(reg.index(), val); 24812107SRekai.GonzalezAlberquilla@arm.com setScalarResult(val); 2492315SN/A } 2502315SN/A 25111169Sandreas.hansson@arm.com void setFloatRegOperand(const StaticInst *si, int idx, 25211169Sandreas.hansson@arm.com FloatReg val) override 2532669Sktlim@umich.edu { 25412106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 25512106SRekai.GonzalezAlberquilla@arm.com assert(reg.isFloatReg()); 25612106SRekai.GonzalezAlberquilla@arm.com thread->setFloatReg(reg.index(), val); 25712107SRekai.GonzalezAlberquilla@arm.com setScalarResult(val); 2582315SN/A } 2592315SN/A 2603735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, 26111169Sandreas.hansson@arm.com FloatRegBits val) override 2622315SN/A { 26312106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 26412106SRekai.GonzalezAlberquilla@arm.com assert(reg.isFloatReg()); 26512106SRekai.GonzalezAlberquilla@arm.com thread->setFloatRegBits(reg.index(), val); 26612107SRekai.GonzalezAlberquilla@arm.com setScalarResult(val); 2672315SN/A } 2682315SN/A 26911169Sandreas.hansson@arm.com void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override 2709920Syasuko.eckert@amd.com { 27112106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 27212106SRekai.GonzalezAlberquilla@arm.com assert(reg.isCCReg()); 27312106SRekai.GonzalezAlberquilla@arm.com thread->setCCReg(reg.index(), val); 27412107SRekai.GonzalezAlberquilla@arm.com setScalarResult((uint64_t)val); 2759920Syasuko.eckert@amd.com } 2769920Syasuko.eckert@amd.com 27711169Sandreas.hansson@arm.com bool readPredicate() override { return thread->readPredicate(); } 27811169Sandreas.hansson@arm.com void setPredicate(bool val) override 2798733Sgeoffrey.blake@arm.com { 2808733Sgeoffrey.blake@arm.com thread->setPredicate(val); 2818733Sgeoffrey.blake@arm.com } 2822669Sktlim@umich.edu 28311169Sandreas.hansson@arm.com TheISA::PCState pcState() const override { return thread->pcState(); } 28411169Sandreas.hansson@arm.com void pcState(const TheISA::PCState &val) override 2858733Sgeoffrey.blake@arm.com { 2868733Sgeoffrey.blake@arm.com DPRINTF(Checker, "Changing PC to %s, old PC %s.\n", 2878733Sgeoffrey.blake@arm.com val, thread->pcState()); 2888733Sgeoffrey.blake@arm.com thread->pcState(val); 2898733Sgeoffrey.blake@arm.com } 2908733Sgeoffrey.blake@arm.com Addr instAddr() { return thread->instAddr(); } 2918733Sgeoffrey.blake@arm.com Addr nextInstAddr() { return thread->nextInstAddr(); } 2928733Sgeoffrey.blake@arm.com MicroPC microPC() { return thread->microPC(); } 2938733Sgeoffrey.blake@arm.com ////////////////////////////////////////// 2942315SN/A 29510698Sandreas.hansson@arm.com MiscReg readMiscRegNoEffect(int misc_reg) const 2964172Ssaidi@eecs.umich.edu { 2974172Ssaidi@eecs.umich.edu return thread->readMiscRegNoEffect(misc_reg); 2984172Ssaidi@eecs.umich.edu } 2994172Ssaidi@eecs.umich.edu 30011169Sandreas.hansson@arm.com MiscReg readMiscReg(int misc_reg) override 3012315SN/A { 3022683Sktlim@umich.edu return thread->readMiscReg(misc_reg); 3032315SN/A } 3042315SN/A 3054172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 3062315SN/A { 30710034SGeoffrey.Blake@arm.com DPRINTF(Checker, "Setting misc reg %d with no effect to check later\n", misc_reg); 3084172Ssaidi@eecs.umich.edu miscRegIdxs.push(misc_reg); 3094172Ssaidi@eecs.umich.edu return thread->setMiscRegNoEffect(misc_reg, val); 3102315SN/A } 3112315SN/A 31211169Sandreas.hansson@arm.com void setMiscReg(int misc_reg, const MiscReg &val) override 3132315SN/A { 31410034SGeoffrey.Blake@arm.com DPRINTF(Checker, "Setting misc reg %d with effect to check later\n", misc_reg); 3152315SN/A miscRegIdxs.push(misc_reg); 3162683Sktlim@umich.edu return thread->setMiscReg(misc_reg, val); 3172315SN/A } 3182315SN/A 31911169Sandreas.hansson@arm.com MiscReg readMiscRegOperand(const StaticInst *si, int idx) override 3208733Sgeoffrey.blake@arm.com { 32112106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 32212106SRekai.GonzalezAlberquilla@arm.com assert(reg.isMiscReg()); 32312106SRekai.GonzalezAlberquilla@arm.com return thread->readMiscReg(reg.index()); 3248733Sgeoffrey.blake@arm.com } 3258733Sgeoffrey.blake@arm.com 32611169Sandreas.hansson@arm.com void setMiscRegOperand(const StaticInst *si, int idx, 32711169Sandreas.hansson@arm.com const MiscReg &val) override 3288733Sgeoffrey.blake@arm.com { 32912106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 33012106SRekai.GonzalezAlberquilla@arm.com assert(reg.isMiscReg()); 33112106SRekai.GonzalezAlberquilla@arm.com return this->setMiscReg(reg.index(), val); 3328733Sgeoffrey.blake@arm.com } 3338888Sgeoffrey.blake@arm.com 3348888Sgeoffrey.blake@arm.com#if THE_ISA == MIPS_ISA 33512106SRekai.GonzalezAlberquilla@arm.com MiscReg readRegOtherThread(const RegId& misc_reg, ThreadID tid) override 3368888Sgeoffrey.blake@arm.com { 3378888Sgeoffrey.blake@arm.com panic("MIPS MT not defined for CheckerCPU.\n"); 3388888Sgeoffrey.blake@arm.com return 0; 3398888Sgeoffrey.blake@arm.com } 3408888Sgeoffrey.blake@arm.com 34112106SRekai.GonzalezAlberquilla@arm.com void setRegOtherThread(const RegId& misc_reg, MiscReg val, 34212106SRekai.GonzalezAlberquilla@arm.com ThreadID tid) override 3438888Sgeoffrey.blake@arm.com { 3448888Sgeoffrey.blake@arm.com panic("MIPS MT not defined for CheckerCPU.\n"); 3458888Sgeoffrey.blake@arm.com } 3468888Sgeoffrey.blake@arm.com#endif 3478888Sgeoffrey.blake@arm.com 3488733Sgeoffrey.blake@arm.com ///////////////////////////////////////// 3498733Sgeoffrey.blake@arm.com 3508733Sgeoffrey.blake@arm.com void recordPCChange(const TheISA::PCState &val) 3518733Sgeoffrey.blake@arm.com { 3528733Sgeoffrey.blake@arm.com changedPC = true; 3538733Sgeoffrey.blake@arm.com newPCState = val; 3548733Sgeoffrey.blake@arm.com } 3552315SN/A 35611169Sandreas.hansson@arm.com void demapPage(Addr vaddr, uint64_t asn) override 3575358Sgblack@eecs.umich.edu { 3585358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 3595358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 3605358Sgblack@eecs.umich.edu } 3615358Sgblack@eecs.umich.edu 36210529Smorr@cs.wisc.edu // monitor/mwait funtions 36311169Sandreas.hansson@arm.com void armMonitor(Addr address) override 36411169Sandreas.hansson@arm.com { BaseCPU::armMonitor(0, address); } 36511169Sandreas.hansson@arm.com bool mwait(PacketPtr pkt) override { return BaseCPU::mwait(0, pkt); } 36611169Sandreas.hansson@arm.com void mwaitAtomic(ThreadContext *tc) override 36711148Smitch.hayenga@arm.com { return BaseCPU::mwaitAtomic(0, tc, thread->dtb); } 36811169Sandreas.hansson@arm.com AddressMonitor *getAddrMonitor() override 36911169Sandreas.hansson@arm.com { return BaseCPU::getCpuAddrMonitor(0); } 37010529Smorr@cs.wisc.edu 3715358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 3725358Sgblack@eecs.umich.edu { 3735358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 3745358Sgblack@eecs.umich.edu } 3755358Sgblack@eecs.umich.edu 3765358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 3775358Sgblack@eecs.umich.edu { 3785358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 3795358Sgblack@eecs.umich.edu } 3805358Sgblack@eecs.umich.edu 38111169Sandreas.hansson@arm.com Fault readMem(Addr addr, uint8_t *data, unsigned size, 38211608Snikos.nikoleris@arm.com Request::Flags flags) override; 38311608Snikos.nikoleris@arm.com Fault writeMem(uint8_t *data, unsigned size, Addr addr, 38411608Snikos.nikoleris@arm.com Request::Flags flags, uint64_t *res) override; 3858733Sgeoffrey.blake@arm.com 38611169Sandreas.hansson@arm.com unsigned int readStCondFailures() const override { 38710319SAndreas.Sandberg@ARM.com return thread->readStCondFailures(); 38810319SAndreas.Sandberg@ARM.com } 38910319SAndreas.Sandberg@ARM.com 39011169Sandreas.hansson@arm.com void setStCondFailures(unsigned int sc_failures) override 3918733Sgeoffrey.blake@arm.com {} 3928733Sgeoffrey.blake@arm.com ///////////////////////////////////////////////////// 3938733Sgeoffrey.blake@arm.com 39411169Sandreas.hansson@arm.com Fault hwrei() override { return thread->hwrei(); } 39511169Sandreas.hansson@arm.com bool simPalCheck(int palFunc) override 39611169Sandreas.hansson@arm.com { return thread->simPalCheck(palFunc); } 39711168Sandreas.hansson@arm.com void wakeup(ThreadID tid) override { } 3982315SN/A // Assume that the normal CPU's call to syscall was successful. 3992332SN/A // The checker's state would have already been updated by the syscall. 40011877Sbrandon.potter@amd.com void syscall(int64_t callnum, Fault *fault) override { } 4012315SN/A 4022315SN/A void handleError() 4032315SN/A { 4042315SN/A if (exitOnError) 4052732Sktlim@umich.edu dumpAndExit(); 4062315SN/A } 4072732Sktlim@umich.edu 4088733Sgeoffrey.blake@arm.com bool checkFlags(Request *unverified_req, Addr vAddr, 4098733Sgeoffrey.blake@arm.com Addr pAddr, int flags); 4102315SN/A 4112732Sktlim@umich.edu void dumpAndExit(); 4122732Sktlim@umich.edu 41311169Sandreas.hansson@arm.com ThreadContext *tcBase() override { return tc; } 4142683Sktlim@umich.edu SimpleThread *threadBase() { return thread; } 4152315SN/A 41612107SRekai.GonzalezAlberquilla@arm.com InstResult unverifiedResult; 4172669Sktlim@umich.edu Request *unverifiedReq; 4182679Sktlim@umich.edu uint8_t *unverifiedMemData; 4192315SN/A 4202315SN/A bool changedPC; 4212315SN/A bool willChangePC; 4228733Sgeoffrey.blake@arm.com TheISA::PCState newPCState; 4232315SN/A bool exitOnError; 4242354SN/A bool updateOnError; 4252732Sktlim@umich.edu bool warnOnlyOnLoadError; 4262315SN/A 4272315SN/A InstSeqNum youngestSN; 4282315SN/A}; 4292315SN/A 4302350SN/A/** 4312350SN/A * Templated Checker class. This Checker class is templated on the 4322350SN/A * DynInstPtr of the instruction type that will be verified. Proper 4332350SN/A * template instantiations of the Checker must be placed at the bottom 4342350SN/A * of checker/cpu.cc. 4352350SN/A */ 4368733Sgeoffrey.blake@arm.comtemplate <class Impl> 4372315SN/Aclass Checker : public CheckerCPU 4382315SN/A{ 4398733Sgeoffrey.blake@arm.com private: 4408733Sgeoffrey.blake@arm.com typedef typename Impl::DynInstPtr DynInstPtr; 4418733Sgeoffrey.blake@arm.com 4422315SN/A public: 4432315SN/A Checker(Params *p) 4449023Sgblack@eecs.umich.edu : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL) 4452315SN/A { } 4462315SN/A 4472840Sktlim@umich.edu void switchOut(); 4482315SN/A void takeOverFrom(BaseCPU *oldCPU); 4492315SN/A 45010379Sandreas.hansson@arm.com void advancePC(const Fault &fault); 4518733Sgeoffrey.blake@arm.com 4522732Sktlim@umich.edu void verify(DynInstPtr &inst); 4532315SN/A 4542315SN/A void validateInst(DynInstPtr &inst); 4552315SN/A void validateExecution(DynInstPtr &inst); 4562315SN/A void validateState(); 4572315SN/A 45812107SRekai.GonzalezAlberquilla@arm.com void copyResult(DynInstPtr &inst, const InstResult& mismatch_val, 45912107SRekai.GonzalezAlberquilla@arm.com int start_idx); 4608733Sgeoffrey.blake@arm.com void handlePendingInt(); 4612732Sktlim@umich.edu 4622732Sktlim@umich.edu private: 4632732Sktlim@umich.edu void handleError(DynInstPtr &inst) 4642732Sktlim@umich.edu { 4652360SN/A if (exitOnError) { 4662732Sktlim@umich.edu dumpAndExit(inst); 4672360SN/A } else if (updateOnError) { 4682354SN/A updateThisCycle = true; 4692360SN/A } 4702732Sktlim@umich.edu } 4712732Sktlim@umich.edu 4722732Sktlim@umich.edu void dumpAndExit(DynInstPtr &inst); 4732732Sktlim@umich.edu 4742354SN/A bool updateThisCycle; 4752354SN/A 4762354SN/A DynInstPtr unverifiedInst; 4772354SN/A 4782315SN/A std::list<DynInstPtr> instList; 4792315SN/A typedef typename std::list<DynInstPtr>::iterator InstListIt; 4802315SN/A void dumpInsts(); 4812315SN/A}; 4822315SN/A 4832315SN/A#endif // __CPU_CHECKER_CPU_HH__ 484