cpu.hh revision 12106
12315SN/A/* 28733Sgeoffrey.blake@arm.com * Copyright (c) 2011 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48733Sgeoffrey.blake@arm.com * All rights reserved 58733Sgeoffrey.blake@arm.com * 68733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 78733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 88733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 98733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 108733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 118733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 128733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 138733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 148733Sgeoffrey.blake@arm.com * 152332SN/A * Copyright (c) 2006 The Regents of The University of Michigan 162315SN/A * All rights reserved. 172315SN/A * 182315SN/A * Redistribution and use in source and binary forms, with or without 192315SN/A * modification, are permitted provided that the following conditions are 202315SN/A * met: redistributions of source code must retain the above copyright 212315SN/A * notice, this list of conditions and the following disclaimer; 222315SN/A * redistributions in binary form must reproduce the above copyright 232315SN/A * notice, this list of conditions and the following disclaimer in the 242315SN/A * documentation and/or other materials provided with the distribution; 252315SN/A * neither the name of the copyright holders nor the names of its 262315SN/A * contributors may be used to endorse or promote products derived from 272315SN/A * this software without specific prior written permission. 282315SN/A * 292315SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302315SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312315SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322315SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332315SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342315SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352315SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362315SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372315SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382315SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392315SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402689Sktlim@umich.edu * 412689Sktlim@umich.edu * Authors: Kevin Lim 422315SN/A */ 432315SN/A 442315SN/A#ifndef __CPU_CHECKER_CPU_HH__ 452315SN/A#define __CPU_CHECKER_CPU_HH__ 462315SN/A 472315SN/A#include <list> 488229Snate@binkert.org#include <map> 492315SN/A#include <queue> 502315SN/A 512669Sktlim@umich.edu#include "arch/types.hh" 522315SN/A#include "base/statistics.hh" 532315SN/A#include "cpu/base.hh" 542315SN/A#include "cpu/base_dyn_inst.hh" 5510319SAndreas.Sandberg@ARM.com#include "cpu/exec_context.hh" 568229Snate@binkert.org#include "cpu/pc_event.hh" 572683Sktlim@umich.edu#include "cpu/simple_thread.hh" 582315SN/A#include "cpu/static_inst.hh" 598733Sgeoffrey.blake@arm.com#include "debug/Checker.hh" 6011608Snikos.nikoleris@arm.com#include "mem/request.hh" 618733Sgeoffrey.blake@arm.com#include "params/CheckerCPU.hh" 622315SN/A#include "sim/eventq.hh" 632315SN/A 642315SN/A// forward declarations 653468Sgblack@eecs.umich.edunamespace TheISA 663468Sgblack@eecs.umich.edu{ 676022Sgblack@eecs.umich.edu class TLB; 683468Sgblack@eecs.umich.edu} 692315SN/A 702315SN/Atemplate <class> 712315SN/Aclass BaseDynInst; 722680Sktlim@umich.educlass ThreadContext; 732669Sktlim@umich.educlass Request; 742315SN/A 752350SN/A/** 762350SN/A * CheckerCPU class. Dynamically verifies instructions as they are 772350SN/A * completed by making sure that the instruction and its results match 782350SN/A * the independent execution of the benchmark inside the checker. The 792350SN/A * checker verifies instructions in order, regardless of the order in 802350SN/A * which instructions complete. There are certain results that can 812350SN/A * not be verified, specifically the result of a store conditional or 822350SN/A * the values of uncached accesses. In these cases, and with 832350SN/A * instructions marked as "IsUnverifiable", the checker assumes that 842350SN/A * the value from the main CPU's execution is correct and simply 852680Sktlim@umich.edu * copies that value. It provides a CheckerThreadContext (see 862683Sktlim@umich.edu * checker/thread_context.hh) that provides hooks for updating the 872680Sktlim@umich.edu * Checker's state through any ThreadContext accesses. This allows the 882350SN/A * checker to be able to correctly verify instructions, even with 892680Sktlim@umich.edu * external accesses to the ThreadContext that change state. 902350SN/A */ 9110319SAndreas.Sandberg@ARM.comclass CheckerCPU : public BaseCPU, public ExecContext 922315SN/A{ 932315SN/A protected: 942315SN/A typedef TheISA::MachInst MachInst; 952669Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 962669Sktlim@umich.edu typedef TheISA::FloatRegBits FloatRegBits; 972315SN/A typedef TheISA::MiscReg MiscReg; 988832SAli.Saidi@ARM.com 998832SAli.Saidi@ARM.com /** id attached to all issued requests */ 1008832SAli.Saidi@ARM.com MasterID masterId; 1012315SN/A public: 10211169Sandreas.hansson@arm.com void init() override; 1032315SN/A 1045529Snate@binkert.org typedef CheckerCPUParams Params; 1052315SN/A CheckerCPU(Params *p); 1062315SN/A virtual ~CheckerCPU(); 1072315SN/A 1082315SN/A void setSystem(System *system); 1092315SN/A 1109608Sandreas.hansson@arm.com void setIcachePort(MasterPort *icache_port); 1112679Sktlim@umich.edu 1129608Sandreas.hansson@arm.com void setDcachePort(MasterPort *dcache_port); 1132679Sktlim@umich.edu 11411169Sandreas.hansson@arm.com MasterPort &getDataPort() override 1158887Sgeoffrey.blake@arm.com { 1169176Sandreas.hansson@arm.com // the checker does not have ports on its own so return the 1179176Sandreas.hansson@arm.com // data port of the actual CPU core 1189176Sandreas.hansson@arm.com assert(dcachePort); 1198887Sgeoffrey.blake@arm.com return *dcachePort; 1208887Sgeoffrey.blake@arm.com } 1218887Sgeoffrey.blake@arm.com 12211169Sandreas.hansson@arm.com MasterPort &getInstPort() override 1238887Sgeoffrey.blake@arm.com { 1249176Sandreas.hansson@arm.com // the checker does not have ports on its own so return the 1259176Sandreas.hansson@arm.com // data port of the actual CPU core 1269176Sandreas.hansson@arm.com assert(icachePort); 1278887Sgeoffrey.blake@arm.com return *icachePort; 1288887Sgeoffrey.blake@arm.com } 1292679Sktlim@umich.edu 1309176Sandreas.hansson@arm.com protected: 1319176Sandreas.hansson@arm.com 1329176Sandreas.hansson@arm.com std::vector<Process*> workload; 1339176Sandreas.hansson@arm.com 1349176Sandreas.hansson@arm.com System *systemPtr; 1359176Sandreas.hansson@arm.com 1369608Sandreas.hansson@arm.com MasterPort *icachePort; 1379608Sandreas.hansson@arm.com MasterPort *dcachePort; 1382315SN/A 1392680Sktlim@umich.edu ThreadContext *tc; 1402315SN/A 1416022Sgblack@eecs.umich.edu TheISA::TLB *itb; 1426022Sgblack@eecs.umich.edu TheISA::TLB *dtb; 1432315SN/A 1442315SN/A Addr dbg_vtophys(Addr addr); 1452315SN/A 1462315SN/A union Result { 1472315SN/A uint64_t integer; 1482315SN/A double dbl; 1498733Sgeoffrey.blake@arm.com void set(uint64_t i) { integer = i; } 1508733Sgeoffrey.blake@arm.com void set(double d) { dbl = d; } 1518733Sgeoffrey.blake@arm.com void get(uint64_t& i) { i = integer; } 1528733Sgeoffrey.blake@arm.com void get(double& d) { d = dbl; } 1532315SN/A }; 1542315SN/A 1558733Sgeoffrey.blake@arm.com // ISAs like ARM can have multiple destination registers to check, 1568733Sgeoffrey.blake@arm.com // keep them all in a std::queue 1578733Sgeoffrey.blake@arm.com std::queue<Result> result; 1582315SN/A 1592679Sktlim@umich.edu // Pointer to the one memory request. 1602679Sktlim@umich.edu RequestPtr memReq; 1612315SN/A 1622315SN/A StaticInstPtr curStaticInst; 1638733Sgeoffrey.blake@arm.com StaticInstPtr curMacroStaticInst; 1642315SN/A 1652315SN/A // number of simulated instructions 1662315SN/A Counter numInst; 1672315SN/A Counter startNumInst; 1682315SN/A 1692315SN/A std::queue<int> miscRegIdxs; 1702315SN/A 1719176Sandreas.hansson@arm.com public: 1729176Sandreas.hansson@arm.com 1739176Sandreas.hansson@arm.com // Primary thread being run. 1749176Sandreas.hansson@arm.com SimpleThread *thread; 1759176Sandreas.hansson@arm.com 1768733Sgeoffrey.blake@arm.com TheISA::TLB* getITBPtr() { return itb; } 1778733Sgeoffrey.blake@arm.com TheISA::TLB* getDTBPtr() { return dtb; } 1788733Sgeoffrey.blake@arm.com 17911169Sandreas.hansson@arm.com virtual Counter totalInsts() const override 1808887Sgeoffrey.blake@arm.com { 1818887Sgeoffrey.blake@arm.com return 0; 1828887Sgeoffrey.blake@arm.com } 1838887Sgeoffrey.blake@arm.com 18411169Sandreas.hansson@arm.com virtual Counter totalOps() const override 1852315SN/A { 1862930Sktlim@umich.edu return 0; 1872315SN/A } 1882315SN/A 1892315SN/A // number of simulated loads 1902315SN/A Counter numLoad; 1912315SN/A Counter startNumLoad; 1922315SN/A 19311168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 19411168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 1952315SN/A 1962315SN/A // These functions are only used in CPU models that split 1972315SN/A // effective address computation from the actual memory access. 19811169Sandreas.hansson@arm.com void setEA(Addr EA) override 19911169Sandreas.hansson@arm.com { panic("CheckerCPU::setEA() not implemented\n"); } 20011169Sandreas.hansson@arm.com Addr getEA() const override 20111169Sandreas.hansson@arm.com { panic("CheckerCPU::getEA() not implemented\n"); } 2022315SN/A 2032315SN/A // The register accessor methods provide the index of the 2042315SN/A // instruction's operand (e.g., 0 or 1), not the architectural 2052315SN/A // register index, to simplify the implementation of register 2062315SN/A // renaming. We find the architectural register index by indexing 2072315SN/A // into the instruction's own operand index table. Note that a 2082315SN/A // raw pointer to the StaticInst is provided instead of a 2092315SN/A // ref-counted StaticInstPtr to redice overhead. This is fine as 2102315SN/A // long as these methods don't copy the pointer into any long-term 2112315SN/A // storage (which is pretty hard to imagine they would have reason 2122315SN/A // to do). 2132315SN/A 21411169Sandreas.hansson@arm.com IntReg readIntRegOperand(const StaticInst *si, int idx) override 2152315SN/A { 21612106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 21712106SRekai.GonzalezAlberquilla@arm.com assert(reg.isIntReg()); 21812106SRekai.GonzalezAlberquilla@arm.com return thread->readIntReg(reg.index()); 2192315SN/A } 2202315SN/A 22111169Sandreas.hansson@arm.com FloatReg readFloatRegOperand(const StaticInst *si, int idx) override 2222315SN/A { 22312106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 22412106SRekai.GonzalezAlberquilla@arm.com assert(reg.isFloatReg()); 22512106SRekai.GonzalezAlberquilla@arm.com return thread->readFloatReg(reg.index()); 2262315SN/A } 2272315SN/A 22811169Sandreas.hansson@arm.com FloatRegBits readFloatRegOperandBits(const StaticInst *si, 22911169Sandreas.hansson@arm.com int idx) override 2302669Sktlim@umich.edu { 23112106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 23212106SRekai.GonzalezAlberquilla@arm.com assert(reg.isFloatReg()); 23312106SRekai.GonzalezAlberquilla@arm.com return thread->readFloatRegBits(reg.index()); 2342315SN/A } 2352315SN/A 23611169Sandreas.hansson@arm.com CCReg readCCRegOperand(const StaticInst *si, int idx) override 2379920Syasuko.eckert@amd.com { 23812106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 23912106SRekai.GonzalezAlberquilla@arm.com assert(reg.isCCReg()); 24012106SRekai.GonzalezAlberquilla@arm.com return thread->readCCReg(reg.index()); 2419920Syasuko.eckert@amd.com } 2429920Syasuko.eckert@amd.com 2438733Sgeoffrey.blake@arm.com template <class T> 2448733Sgeoffrey.blake@arm.com void setResult(T t) 2458733Sgeoffrey.blake@arm.com { 2468733Sgeoffrey.blake@arm.com Result instRes; 2478733Sgeoffrey.blake@arm.com instRes.set(t); 2488733Sgeoffrey.blake@arm.com result.push(instRes); 2498733Sgeoffrey.blake@arm.com } 2508733Sgeoffrey.blake@arm.com 25111169Sandreas.hansson@arm.com void setIntRegOperand(const StaticInst *si, int idx, 25211169Sandreas.hansson@arm.com IntReg val) override 2532315SN/A { 25412106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 25512106SRekai.GonzalezAlberquilla@arm.com assert(reg.isIntReg()); 25612106SRekai.GonzalezAlberquilla@arm.com thread->setIntReg(reg.index(), val); 2578733Sgeoffrey.blake@arm.com setResult<uint64_t>(val); 2582315SN/A } 2592315SN/A 26011169Sandreas.hansson@arm.com void setFloatRegOperand(const StaticInst *si, int idx, 26111169Sandreas.hansson@arm.com FloatReg val) override 2622669Sktlim@umich.edu { 26312106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 26412106SRekai.GonzalezAlberquilla@arm.com assert(reg.isFloatReg()); 26512106SRekai.GonzalezAlberquilla@arm.com thread->setFloatReg(reg.index(), val); 2668733Sgeoffrey.blake@arm.com setResult<double>(val); 2672315SN/A } 2682315SN/A 2693735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, 27011169Sandreas.hansson@arm.com FloatRegBits val) override 2712315SN/A { 27212106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 27312106SRekai.GonzalezAlberquilla@arm.com assert(reg.isFloatReg()); 27412106SRekai.GonzalezAlberquilla@arm.com thread->setFloatRegBits(reg.index(), val); 2758733Sgeoffrey.blake@arm.com setResult<uint64_t>(val); 2762315SN/A } 2772315SN/A 27811169Sandreas.hansson@arm.com void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override 2799920Syasuko.eckert@amd.com { 28012106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 28112106SRekai.GonzalezAlberquilla@arm.com assert(reg.isCCReg()); 28212106SRekai.GonzalezAlberquilla@arm.com thread->setCCReg(reg.index(), val); 2839920Syasuko.eckert@amd.com setResult<uint64_t>(val); 2849920Syasuko.eckert@amd.com } 2859920Syasuko.eckert@amd.com 28611169Sandreas.hansson@arm.com bool readPredicate() override { return thread->readPredicate(); } 28711169Sandreas.hansson@arm.com void setPredicate(bool val) override 2888733Sgeoffrey.blake@arm.com { 2898733Sgeoffrey.blake@arm.com thread->setPredicate(val); 2908733Sgeoffrey.blake@arm.com } 2912669Sktlim@umich.edu 29211169Sandreas.hansson@arm.com TheISA::PCState pcState() const override { return thread->pcState(); } 29311169Sandreas.hansson@arm.com void pcState(const TheISA::PCState &val) override 2948733Sgeoffrey.blake@arm.com { 2958733Sgeoffrey.blake@arm.com DPRINTF(Checker, "Changing PC to %s, old PC %s.\n", 2968733Sgeoffrey.blake@arm.com val, thread->pcState()); 2978733Sgeoffrey.blake@arm.com thread->pcState(val); 2988733Sgeoffrey.blake@arm.com } 2998733Sgeoffrey.blake@arm.com Addr instAddr() { return thread->instAddr(); } 3008733Sgeoffrey.blake@arm.com Addr nextInstAddr() { return thread->nextInstAddr(); } 3018733Sgeoffrey.blake@arm.com MicroPC microPC() { return thread->microPC(); } 3028733Sgeoffrey.blake@arm.com ////////////////////////////////////////// 3032315SN/A 30410698Sandreas.hansson@arm.com MiscReg readMiscRegNoEffect(int misc_reg) const 3054172Ssaidi@eecs.umich.edu { 3064172Ssaidi@eecs.umich.edu return thread->readMiscRegNoEffect(misc_reg); 3074172Ssaidi@eecs.umich.edu } 3084172Ssaidi@eecs.umich.edu 30911169Sandreas.hansson@arm.com MiscReg readMiscReg(int misc_reg) override 3102315SN/A { 3112683Sktlim@umich.edu return thread->readMiscReg(misc_reg); 3122315SN/A } 3132315SN/A 3144172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 3152315SN/A { 31610034SGeoffrey.Blake@arm.com DPRINTF(Checker, "Setting misc reg %d with no effect to check later\n", misc_reg); 3174172Ssaidi@eecs.umich.edu miscRegIdxs.push(misc_reg); 3184172Ssaidi@eecs.umich.edu return thread->setMiscRegNoEffect(misc_reg, val); 3192315SN/A } 3202315SN/A 32111169Sandreas.hansson@arm.com void setMiscReg(int misc_reg, const MiscReg &val) override 3222315SN/A { 32310034SGeoffrey.Blake@arm.com DPRINTF(Checker, "Setting misc reg %d with effect to check later\n", misc_reg); 3242315SN/A miscRegIdxs.push(misc_reg); 3252683Sktlim@umich.edu return thread->setMiscReg(misc_reg, val); 3262315SN/A } 3272315SN/A 32811169Sandreas.hansson@arm.com MiscReg readMiscRegOperand(const StaticInst *si, int idx) override 3298733Sgeoffrey.blake@arm.com { 33012106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->srcRegIdx(idx); 33112106SRekai.GonzalezAlberquilla@arm.com assert(reg.isMiscReg()); 33212106SRekai.GonzalezAlberquilla@arm.com return thread->readMiscReg(reg.index()); 3338733Sgeoffrey.blake@arm.com } 3348733Sgeoffrey.blake@arm.com 33511169Sandreas.hansson@arm.com void setMiscRegOperand(const StaticInst *si, int idx, 33611169Sandreas.hansson@arm.com const MiscReg &val) override 3378733Sgeoffrey.blake@arm.com { 33812106SRekai.GonzalezAlberquilla@arm.com const RegId& reg = si->destRegIdx(idx); 33912106SRekai.GonzalezAlberquilla@arm.com assert(reg.isMiscReg()); 34012106SRekai.GonzalezAlberquilla@arm.com return this->setMiscReg(reg.index(), val); 3418733Sgeoffrey.blake@arm.com } 3428888Sgeoffrey.blake@arm.com 3438888Sgeoffrey.blake@arm.com#if THE_ISA == MIPS_ISA 34412106SRekai.GonzalezAlberquilla@arm.com MiscReg readRegOtherThread(const RegId& misc_reg, ThreadID tid) override 3458888Sgeoffrey.blake@arm.com { 3468888Sgeoffrey.blake@arm.com panic("MIPS MT not defined for CheckerCPU.\n"); 3478888Sgeoffrey.blake@arm.com return 0; 3488888Sgeoffrey.blake@arm.com } 3498888Sgeoffrey.blake@arm.com 35012106SRekai.GonzalezAlberquilla@arm.com void setRegOtherThread(const RegId& misc_reg, MiscReg val, 35112106SRekai.GonzalezAlberquilla@arm.com ThreadID tid) override 3528888Sgeoffrey.blake@arm.com { 3538888Sgeoffrey.blake@arm.com panic("MIPS MT not defined for CheckerCPU.\n"); 3548888Sgeoffrey.blake@arm.com } 3558888Sgeoffrey.blake@arm.com#endif 3568888Sgeoffrey.blake@arm.com 3578733Sgeoffrey.blake@arm.com ///////////////////////////////////////// 3588733Sgeoffrey.blake@arm.com 3598733Sgeoffrey.blake@arm.com void recordPCChange(const TheISA::PCState &val) 3608733Sgeoffrey.blake@arm.com { 3618733Sgeoffrey.blake@arm.com changedPC = true; 3628733Sgeoffrey.blake@arm.com newPCState = val; 3638733Sgeoffrey.blake@arm.com } 3642315SN/A 36511169Sandreas.hansson@arm.com void demapPage(Addr vaddr, uint64_t asn) override 3665358Sgblack@eecs.umich.edu { 3675358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 3685358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 3695358Sgblack@eecs.umich.edu } 3705358Sgblack@eecs.umich.edu 37110529Smorr@cs.wisc.edu // monitor/mwait funtions 37211169Sandreas.hansson@arm.com void armMonitor(Addr address) override 37311169Sandreas.hansson@arm.com { BaseCPU::armMonitor(0, address); } 37411169Sandreas.hansson@arm.com bool mwait(PacketPtr pkt) override { return BaseCPU::mwait(0, pkt); } 37511169Sandreas.hansson@arm.com void mwaitAtomic(ThreadContext *tc) override 37611148Smitch.hayenga@arm.com { return BaseCPU::mwaitAtomic(0, tc, thread->dtb); } 37711169Sandreas.hansson@arm.com AddressMonitor *getAddrMonitor() override 37811169Sandreas.hansson@arm.com { return BaseCPU::getCpuAddrMonitor(0); } 37910529Smorr@cs.wisc.edu 3805358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 3815358Sgblack@eecs.umich.edu { 3825358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 3835358Sgblack@eecs.umich.edu } 3845358Sgblack@eecs.umich.edu 3855358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 3865358Sgblack@eecs.umich.edu { 3875358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 3885358Sgblack@eecs.umich.edu } 3895358Sgblack@eecs.umich.edu 39011169Sandreas.hansson@arm.com Fault readMem(Addr addr, uint8_t *data, unsigned size, 39111608Snikos.nikoleris@arm.com Request::Flags flags) override; 39211608Snikos.nikoleris@arm.com Fault writeMem(uint8_t *data, unsigned size, Addr addr, 39311608Snikos.nikoleris@arm.com Request::Flags flags, uint64_t *res) override; 3948733Sgeoffrey.blake@arm.com 39511169Sandreas.hansson@arm.com unsigned int readStCondFailures() const override { 39610319SAndreas.Sandberg@ARM.com return thread->readStCondFailures(); 39710319SAndreas.Sandberg@ARM.com } 39810319SAndreas.Sandberg@ARM.com 39911169Sandreas.hansson@arm.com void setStCondFailures(unsigned int sc_failures) override 4008733Sgeoffrey.blake@arm.com {} 4018733Sgeoffrey.blake@arm.com ///////////////////////////////////////////////////// 4028733Sgeoffrey.blake@arm.com 40311169Sandreas.hansson@arm.com Fault hwrei() override { return thread->hwrei(); } 40411169Sandreas.hansson@arm.com bool simPalCheck(int palFunc) override 40511169Sandreas.hansson@arm.com { return thread->simPalCheck(palFunc); } 40611168Sandreas.hansson@arm.com void wakeup(ThreadID tid) override { } 4072315SN/A // Assume that the normal CPU's call to syscall was successful. 4082332SN/A // The checker's state would have already been updated by the syscall. 40911877Sbrandon.potter@amd.com void syscall(int64_t callnum, Fault *fault) override { } 4102315SN/A 4112315SN/A void handleError() 4122315SN/A { 4132315SN/A if (exitOnError) 4142732Sktlim@umich.edu dumpAndExit(); 4152315SN/A } 4162732Sktlim@umich.edu 4178733Sgeoffrey.blake@arm.com bool checkFlags(Request *unverified_req, Addr vAddr, 4188733Sgeoffrey.blake@arm.com Addr pAddr, int flags); 4192315SN/A 4202732Sktlim@umich.edu void dumpAndExit(); 4212732Sktlim@umich.edu 42211169Sandreas.hansson@arm.com ThreadContext *tcBase() override { return tc; } 4232683Sktlim@umich.edu SimpleThread *threadBase() { return thread; } 4242315SN/A 4252315SN/A Result unverifiedResult; 4262669Sktlim@umich.edu Request *unverifiedReq; 4272679Sktlim@umich.edu uint8_t *unverifiedMemData; 4282315SN/A 4292315SN/A bool changedPC; 4302315SN/A bool willChangePC; 4318733Sgeoffrey.blake@arm.com TheISA::PCState newPCState; 4322315SN/A bool exitOnError; 4332354SN/A bool updateOnError; 4342732Sktlim@umich.edu bool warnOnlyOnLoadError; 4352315SN/A 4362315SN/A InstSeqNum youngestSN; 4372315SN/A}; 4382315SN/A 4392350SN/A/** 4402350SN/A * Templated Checker class. This Checker class is templated on the 4412350SN/A * DynInstPtr of the instruction type that will be verified. Proper 4422350SN/A * template instantiations of the Checker must be placed at the bottom 4432350SN/A * of checker/cpu.cc. 4442350SN/A */ 4458733Sgeoffrey.blake@arm.comtemplate <class Impl> 4462315SN/Aclass Checker : public CheckerCPU 4472315SN/A{ 4488733Sgeoffrey.blake@arm.com private: 4498733Sgeoffrey.blake@arm.com typedef typename Impl::DynInstPtr DynInstPtr; 4508733Sgeoffrey.blake@arm.com 4512315SN/A public: 4522315SN/A Checker(Params *p) 4539023Sgblack@eecs.umich.edu : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL) 4542315SN/A { } 4552315SN/A 4562840Sktlim@umich.edu void switchOut(); 4572315SN/A void takeOverFrom(BaseCPU *oldCPU); 4582315SN/A 45910379Sandreas.hansson@arm.com void advancePC(const Fault &fault); 4608733Sgeoffrey.blake@arm.com 4612732Sktlim@umich.edu void verify(DynInstPtr &inst); 4622315SN/A 4632315SN/A void validateInst(DynInstPtr &inst); 4642315SN/A void validateExecution(DynInstPtr &inst); 4652315SN/A void validateState(); 4662315SN/A 46710935Snilay@cs.wisc.edu void copyResult(DynInstPtr &inst, uint64_t mismatch_val, int start_idx); 4688733Sgeoffrey.blake@arm.com void handlePendingInt(); 4692732Sktlim@umich.edu 4702732Sktlim@umich.edu private: 4712732Sktlim@umich.edu void handleError(DynInstPtr &inst) 4722732Sktlim@umich.edu { 4732360SN/A if (exitOnError) { 4742732Sktlim@umich.edu dumpAndExit(inst); 4752360SN/A } else if (updateOnError) { 4762354SN/A updateThisCycle = true; 4772360SN/A } 4782732Sktlim@umich.edu } 4792732Sktlim@umich.edu 4802732Sktlim@umich.edu void dumpAndExit(DynInstPtr &inst); 4812732Sktlim@umich.edu 4822354SN/A bool updateThisCycle; 4832354SN/A 4842354SN/A DynInstPtr unverifiedInst; 4852354SN/A 4862315SN/A std::list<DynInstPtr> instList; 4872315SN/A typedef typename std::list<DynInstPtr>::iterator InstListIt; 4882315SN/A void dumpInsts(); 4892315SN/A}; 4902315SN/A 4912315SN/A#endif // __CPU_CHECKER_CPU_HH__ 492