cpu.hh revision 11877
12315SN/A/* 28733Sgeoffrey.blake@arm.com * Copyright (c) 2011 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48733Sgeoffrey.blake@arm.com * All rights reserved 58733Sgeoffrey.blake@arm.com * 68733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 78733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 88733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 98733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 108733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 118733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 128733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 138733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 148733Sgeoffrey.blake@arm.com * 152332SN/A * Copyright (c) 2006 The Regents of The University of Michigan 162315SN/A * All rights reserved. 172315SN/A * 182315SN/A * Redistribution and use in source and binary forms, with or without 192315SN/A * modification, are permitted provided that the following conditions are 202315SN/A * met: redistributions of source code must retain the above copyright 212315SN/A * notice, this list of conditions and the following disclaimer; 222315SN/A * redistributions in binary form must reproduce the above copyright 232315SN/A * notice, this list of conditions and the following disclaimer in the 242315SN/A * documentation and/or other materials provided with the distribution; 252315SN/A * neither the name of the copyright holders nor the names of its 262315SN/A * contributors may be used to endorse or promote products derived from 272315SN/A * this software without specific prior written permission. 282315SN/A * 292315SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302315SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312315SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322315SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332315SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342315SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352315SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362315SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372315SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382315SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392315SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402689Sktlim@umich.edu * 412689Sktlim@umich.edu * Authors: Kevin Lim 422315SN/A */ 432315SN/A 442315SN/A#ifndef __CPU_CHECKER_CPU_HH__ 452315SN/A#define __CPU_CHECKER_CPU_HH__ 462315SN/A 472315SN/A#include <list> 488229Snate@binkert.org#include <map> 492315SN/A#include <queue> 502315SN/A 512669Sktlim@umich.edu#include "arch/types.hh" 522315SN/A#include "base/statistics.hh" 532315SN/A#include "cpu/base.hh" 542315SN/A#include "cpu/base_dyn_inst.hh" 5510319SAndreas.Sandberg@ARM.com#include "cpu/exec_context.hh" 568229Snate@binkert.org#include "cpu/pc_event.hh" 572683Sktlim@umich.edu#include "cpu/simple_thread.hh" 582315SN/A#include "cpu/static_inst.hh" 598733Sgeoffrey.blake@arm.com#include "debug/Checker.hh" 6011608Snikos.nikoleris@arm.com#include "mem/request.hh" 618733Sgeoffrey.blake@arm.com#include "params/CheckerCPU.hh" 622315SN/A#include "sim/eventq.hh" 632315SN/A 642315SN/A// forward declarations 653468Sgblack@eecs.umich.edunamespace TheISA 663468Sgblack@eecs.umich.edu{ 676022Sgblack@eecs.umich.edu class TLB; 683468Sgblack@eecs.umich.edu} 692315SN/A 702315SN/Atemplate <class> 712315SN/Aclass BaseDynInst; 722680Sktlim@umich.educlass ThreadContext; 732669Sktlim@umich.educlass Request; 742315SN/A 752350SN/A/** 762350SN/A * CheckerCPU class. Dynamically verifies instructions as they are 772350SN/A * completed by making sure that the instruction and its results match 782350SN/A * the independent execution of the benchmark inside the checker. The 792350SN/A * checker verifies instructions in order, regardless of the order in 802350SN/A * which instructions complete. There are certain results that can 812350SN/A * not be verified, specifically the result of a store conditional or 822350SN/A * the values of uncached accesses. In these cases, and with 832350SN/A * instructions marked as "IsUnverifiable", the checker assumes that 842350SN/A * the value from the main CPU's execution is correct and simply 852680Sktlim@umich.edu * copies that value. It provides a CheckerThreadContext (see 862683Sktlim@umich.edu * checker/thread_context.hh) that provides hooks for updating the 872680Sktlim@umich.edu * Checker's state through any ThreadContext accesses. This allows the 882350SN/A * checker to be able to correctly verify instructions, even with 892680Sktlim@umich.edu * external accesses to the ThreadContext that change state. 902350SN/A */ 9110319SAndreas.Sandberg@ARM.comclass CheckerCPU : public BaseCPU, public ExecContext 922315SN/A{ 932315SN/A protected: 942315SN/A typedef TheISA::MachInst MachInst; 952669Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 962669Sktlim@umich.edu typedef TheISA::FloatRegBits FloatRegBits; 972315SN/A typedef TheISA::MiscReg MiscReg; 988832SAli.Saidi@ARM.com 998832SAli.Saidi@ARM.com /** id attached to all issued requests */ 1008832SAli.Saidi@ARM.com MasterID masterId; 1012315SN/A public: 10211169Sandreas.hansson@arm.com void init() override; 1032315SN/A 1045529Snate@binkert.org typedef CheckerCPUParams Params; 1052315SN/A CheckerCPU(Params *p); 1062315SN/A virtual ~CheckerCPU(); 1072315SN/A 1082315SN/A void setSystem(System *system); 1092315SN/A 1109608Sandreas.hansson@arm.com void setIcachePort(MasterPort *icache_port); 1112679Sktlim@umich.edu 1129608Sandreas.hansson@arm.com void setDcachePort(MasterPort *dcache_port); 1132679Sktlim@umich.edu 11411169Sandreas.hansson@arm.com MasterPort &getDataPort() override 1158887Sgeoffrey.blake@arm.com { 1169176Sandreas.hansson@arm.com // the checker does not have ports on its own so return the 1179176Sandreas.hansson@arm.com // data port of the actual CPU core 1189176Sandreas.hansson@arm.com assert(dcachePort); 1198887Sgeoffrey.blake@arm.com return *dcachePort; 1208887Sgeoffrey.blake@arm.com } 1218887Sgeoffrey.blake@arm.com 12211169Sandreas.hansson@arm.com MasterPort &getInstPort() override 1238887Sgeoffrey.blake@arm.com { 1249176Sandreas.hansson@arm.com // the checker does not have ports on its own so return the 1259176Sandreas.hansson@arm.com // data port of the actual CPU core 1269176Sandreas.hansson@arm.com assert(icachePort); 1278887Sgeoffrey.blake@arm.com return *icachePort; 1288887Sgeoffrey.blake@arm.com } 1292679Sktlim@umich.edu 1309176Sandreas.hansson@arm.com protected: 1319176Sandreas.hansson@arm.com 1329176Sandreas.hansson@arm.com std::vector<Process*> workload; 1339176Sandreas.hansson@arm.com 1349176Sandreas.hansson@arm.com System *systemPtr; 1359176Sandreas.hansson@arm.com 1369608Sandreas.hansson@arm.com MasterPort *icachePort; 1379608Sandreas.hansson@arm.com MasterPort *dcachePort; 1382315SN/A 1392680Sktlim@umich.edu ThreadContext *tc; 1402315SN/A 1416022Sgblack@eecs.umich.edu TheISA::TLB *itb; 1426022Sgblack@eecs.umich.edu TheISA::TLB *dtb; 1432315SN/A 1442315SN/A Addr dbg_vtophys(Addr addr); 1452315SN/A 1462315SN/A union Result { 1472315SN/A uint64_t integer; 1482315SN/A double dbl; 1498733Sgeoffrey.blake@arm.com void set(uint64_t i) { integer = i; } 1508733Sgeoffrey.blake@arm.com void set(double d) { dbl = d; } 1518733Sgeoffrey.blake@arm.com void get(uint64_t& i) { i = integer; } 1528733Sgeoffrey.blake@arm.com void get(double& d) { d = dbl; } 1532315SN/A }; 1542315SN/A 1558733Sgeoffrey.blake@arm.com // ISAs like ARM can have multiple destination registers to check, 1568733Sgeoffrey.blake@arm.com // keep them all in a std::queue 1578733Sgeoffrey.blake@arm.com std::queue<Result> result; 1582315SN/A 1592679Sktlim@umich.edu // Pointer to the one memory request. 1602679Sktlim@umich.edu RequestPtr memReq; 1612315SN/A 1622315SN/A StaticInstPtr curStaticInst; 1638733Sgeoffrey.blake@arm.com StaticInstPtr curMacroStaticInst; 1642315SN/A 1652315SN/A // number of simulated instructions 1662315SN/A Counter numInst; 1672315SN/A Counter startNumInst; 1682315SN/A 1692315SN/A std::queue<int> miscRegIdxs; 1702315SN/A 1719176Sandreas.hansson@arm.com public: 1729176Sandreas.hansson@arm.com 1739176Sandreas.hansson@arm.com // Primary thread being run. 1749176Sandreas.hansson@arm.com SimpleThread *thread; 1759176Sandreas.hansson@arm.com 1768733Sgeoffrey.blake@arm.com TheISA::TLB* getITBPtr() { return itb; } 1778733Sgeoffrey.blake@arm.com TheISA::TLB* getDTBPtr() { return dtb; } 1788733Sgeoffrey.blake@arm.com 17911169Sandreas.hansson@arm.com virtual Counter totalInsts() const override 1808887Sgeoffrey.blake@arm.com { 1818887Sgeoffrey.blake@arm.com return 0; 1828887Sgeoffrey.blake@arm.com } 1838887Sgeoffrey.blake@arm.com 18411169Sandreas.hansson@arm.com virtual Counter totalOps() const override 1852315SN/A { 1862930Sktlim@umich.edu return 0; 1872315SN/A } 1882315SN/A 1892315SN/A // number of simulated loads 1902315SN/A Counter numLoad; 1912315SN/A Counter startNumLoad; 1922315SN/A 19311168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 19411168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 1952315SN/A 1962315SN/A // These functions are only used in CPU models that split 1972315SN/A // effective address computation from the actual memory access. 19811169Sandreas.hansson@arm.com void setEA(Addr EA) override 19911169Sandreas.hansson@arm.com { panic("CheckerCPU::setEA() not implemented\n"); } 20011169Sandreas.hansson@arm.com Addr getEA() const override 20111169Sandreas.hansson@arm.com { panic("CheckerCPU::getEA() not implemented\n"); } 2022315SN/A 2032315SN/A // The register accessor methods provide the index of the 2042315SN/A // instruction's operand (e.g., 0 or 1), not the architectural 2052315SN/A // register index, to simplify the implementation of register 2062315SN/A // renaming. We find the architectural register index by indexing 2072315SN/A // into the instruction's own operand index table. Note that a 2082315SN/A // raw pointer to the StaticInst is provided instead of a 2092315SN/A // ref-counted StaticInstPtr to redice overhead. This is fine as 2102315SN/A // long as these methods don't copy the pointer into any long-term 2112315SN/A // storage (which is pretty hard to imagine they would have reason 2122315SN/A // to do). 2132315SN/A 21411169Sandreas.hansson@arm.com IntReg readIntRegOperand(const StaticInst *si, int idx) override 2152315SN/A { 2162683Sktlim@umich.edu return thread->readIntReg(si->srcRegIdx(idx)); 2172315SN/A } 2182315SN/A 21911169Sandreas.hansson@arm.com FloatReg readFloatRegOperand(const StaticInst *si, int idx) override 2202315SN/A { 2219918Ssteve.reinhardt@amd.com int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base; 2222683Sktlim@umich.edu return thread->readFloatReg(reg_idx); 2232315SN/A } 2242315SN/A 22511169Sandreas.hansson@arm.com FloatRegBits readFloatRegOperandBits(const StaticInst *si, 22611169Sandreas.hansson@arm.com int idx) override 2272669Sktlim@umich.edu { 2289918Ssteve.reinhardt@amd.com int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base; 2292683Sktlim@umich.edu return thread->readFloatRegBits(reg_idx); 2302315SN/A } 2312315SN/A 23211169Sandreas.hansson@arm.com CCReg readCCRegOperand(const StaticInst *si, int idx) override 2339920Syasuko.eckert@amd.com { 2349920Syasuko.eckert@amd.com int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base; 2359920Syasuko.eckert@amd.com return thread->readCCReg(reg_idx); 2369920Syasuko.eckert@amd.com } 2379920Syasuko.eckert@amd.com 2388733Sgeoffrey.blake@arm.com template <class T> 2398733Sgeoffrey.blake@arm.com void setResult(T t) 2408733Sgeoffrey.blake@arm.com { 2418733Sgeoffrey.blake@arm.com Result instRes; 2428733Sgeoffrey.blake@arm.com instRes.set(t); 2438733Sgeoffrey.blake@arm.com result.push(instRes); 2448733Sgeoffrey.blake@arm.com } 2458733Sgeoffrey.blake@arm.com 24611169Sandreas.hansson@arm.com void setIntRegOperand(const StaticInst *si, int idx, 24711169Sandreas.hansson@arm.com IntReg val) override 2482315SN/A { 2492683Sktlim@umich.edu thread->setIntReg(si->destRegIdx(idx), val); 2508733Sgeoffrey.blake@arm.com setResult<uint64_t>(val); 2512315SN/A } 2522315SN/A 25311169Sandreas.hansson@arm.com void setFloatRegOperand(const StaticInst *si, int idx, 25411169Sandreas.hansson@arm.com FloatReg val) override 2552669Sktlim@umich.edu { 2569918Ssteve.reinhardt@amd.com int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base; 2572683Sktlim@umich.edu thread->setFloatReg(reg_idx, val); 2588733Sgeoffrey.blake@arm.com setResult<double>(val); 2592315SN/A } 2602315SN/A 2613735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, 26211169Sandreas.hansson@arm.com FloatRegBits val) override 2632315SN/A { 2649918Ssteve.reinhardt@amd.com int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base; 2652683Sktlim@umich.edu thread->setFloatRegBits(reg_idx, val); 2668733Sgeoffrey.blake@arm.com setResult<uint64_t>(val); 2672315SN/A } 2682315SN/A 26911169Sandreas.hansson@arm.com void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override 2709920Syasuko.eckert@amd.com { 2719920Syasuko.eckert@amd.com int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base; 2729920Syasuko.eckert@amd.com thread->setCCReg(reg_idx, val); 2739920Syasuko.eckert@amd.com setResult<uint64_t>(val); 2749920Syasuko.eckert@amd.com } 2759920Syasuko.eckert@amd.com 27611169Sandreas.hansson@arm.com bool readPredicate() override { return thread->readPredicate(); } 27711169Sandreas.hansson@arm.com void setPredicate(bool val) override 2788733Sgeoffrey.blake@arm.com { 2798733Sgeoffrey.blake@arm.com thread->setPredicate(val); 2808733Sgeoffrey.blake@arm.com } 2812669Sktlim@umich.edu 28211169Sandreas.hansson@arm.com TheISA::PCState pcState() const override { return thread->pcState(); } 28311169Sandreas.hansson@arm.com void pcState(const TheISA::PCState &val) override 2848733Sgeoffrey.blake@arm.com { 2858733Sgeoffrey.blake@arm.com DPRINTF(Checker, "Changing PC to %s, old PC %s.\n", 2868733Sgeoffrey.blake@arm.com val, thread->pcState()); 2878733Sgeoffrey.blake@arm.com thread->pcState(val); 2888733Sgeoffrey.blake@arm.com } 2898733Sgeoffrey.blake@arm.com Addr instAddr() { return thread->instAddr(); } 2908733Sgeoffrey.blake@arm.com Addr nextInstAddr() { return thread->nextInstAddr(); } 2918733Sgeoffrey.blake@arm.com MicroPC microPC() { return thread->microPC(); } 2928733Sgeoffrey.blake@arm.com ////////////////////////////////////////// 2932315SN/A 29410698Sandreas.hansson@arm.com MiscReg readMiscRegNoEffect(int misc_reg) const 2954172Ssaidi@eecs.umich.edu { 2964172Ssaidi@eecs.umich.edu return thread->readMiscRegNoEffect(misc_reg); 2974172Ssaidi@eecs.umich.edu } 2984172Ssaidi@eecs.umich.edu 29911169Sandreas.hansson@arm.com MiscReg readMiscReg(int misc_reg) override 3002315SN/A { 3012683Sktlim@umich.edu return thread->readMiscReg(misc_reg); 3022315SN/A } 3032315SN/A 3044172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 3052315SN/A { 30610034SGeoffrey.Blake@arm.com DPRINTF(Checker, "Setting misc reg %d with no effect to check later\n", misc_reg); 3074172Ssaidi@eecs.umich.edu miscRegIdxs.push(misc_reg); 3084172Ssaidi@eecs.umich.edu return thread->setMiscRegNoEffect(misc_reg, val); 3092315SN/A } 3102315SN/A 31111169Sandreas.hansson@arm.com void setMiscReg(int misc_reg, const MiscReg &val) override 3122315SN/A { 31310034SGeoffrey.Blake@arm.com DPRINTF(Checker, "Setting misc reg %d with effect to check later\n", misc_reg); 3142315SN/A miscRegIdxs.push(misc_reg); 3152683Sktlim@umich.edu return thread->setMiscReg(misc_reg, val); 3162315SN/A } 3172315SN/A 31811169Sandreas.hansson@arm.com MiscReg readMiscRegOperand(const StaticInst *si, int idx) override 3198733Sgeoffrey.blake@arm.com { 3209918Ssteve.reinhardt@amd.com int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base; 3218733Sgeoffrey.blake@arm.com return thread->readMiscReg(reg_idx); 3228733Sgeoffrey.blake@arm.com } 3238733Sgeoffrey.blake@arm.com 32411169Sandreas.hansson@arm.com void setMiscRegOperand(const StaticInst *si, int idx, 32511169Sandreas.hansson@arm.com const MiscReg &val) override 3268733Sgeoffrey.blake@arm.com { 3279918Ssteve.reinhardt@amd.com int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base; 32810034SGeoffrey.Blake@arm.com return this->setMiscReg(reg_idx, val); 3298733Sgeoffrey.blake@arm.com } 3308888Sgeoffrey.blake@arm.com 3318888Sgeoffrey.blake@arm.com#if THE_ISA == MIPS_ISA 33211347Sandreas.hansson@arm.com MiscReg readRegOtherThread(int misc_reg, ThreadID tid) override 3338888Sgeoffrey.blake@arm.com { 3348888Sgeoffrey.blake@arm.com panic("MIPS MT not defined for CheckerCPU.\n"); 3358888Sgeoffrey.blake@arm.com return 0; 3368888Sgeoffrey.blake@arm.com } 3378888Sgeoffrey.blake@arm.com 33811347Sandreas.hansson@arm.com void setRegOtherThread(int misc_reg, MiscReg val, ThreadID tid) override 3398888Sgeoffrey.blake@arm.com { 3408888Sgeoffrey.blake@arm.com panic("MIPS MT not defined for CheckerCPU.\n"); 3418888Sgeoffrey.blake@arm.com } 3428888Sgeoffrey.blake@arm.com#endif 3438888Sgeoffrey.blake@arm.com 3448733Sgeoffrey.blake@arm.com ///////////////////////////////////////// 3458733Sgeoffrey.blake@arm.com 3468733Sgeoffrey.blake@arm.com void recordPCChange(const TheISA::PCState &val) 3478733Sgeoffrey.blake@arm.com { 3488733Sgeoffrey.blake@arm.com changedPC = true; 3498733Sgeoffrey.blake@arm.com newPCState = val; 3508733Sgeoffrey.blake@arm.com } 3512315SN/A 35211169Sandreas.hansson@arm.com void demapPage(Addr vaddr, uint64_t asn) override 3535358Sgblack@eecs.umich.edu { 3545358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 3555358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 3565358Sgblack@eecs.umich.edu } 3575358Sgblack@eecs.umich.edu 35810529Smorr@cs.wisc.edu // monitor/mwait funtions 35911169Sandreas.hansson@arm.com void armMonitor(Addr address) override 36011169Sandreas.hansson@arm.com { BaseCPU::armMonitor(0, address); } 36111169Sandreas.hansson@arm.com bool mwait(PacketPtr pkt) override { return BaseCPU::mwait(0, pkt); } 36211169Sandreas.hansson@arm.com void mwaitAtomic(ThreadContext *tc) override 36311148Smitch.hayenga@arm.com { return BaseCPU::mwaitAtomic(0, tc, thread->dtb); } 36411169Sandreas.hansson@arm.com AddressMonitor *getAddrMonitor() override 36511169Sandreas.hansson@arm.com { return BaseCPU::getCpuAddrMonitor(0); } 36610529Smorr@cs.wisc.edu 3675358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 3685358Sgblack@eecs.umich.edu { 3695358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 3705358Sgblack@eecs.umich.edu } 3715358Sgblack@eecs.umich.edu 3725358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 3735358Sgblack@eecs.umich.edu { 3745358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 3755358Sgblack@eecs.umich.edu } 3765358Sgblack@eecs.umich.edu 37711169Sandreas.hansson@arm.com Fault readMem(Addr addr, uint8_t *data, unsigned size, 37811608Snikos.nikoleris@arm.com Request::Flags flags) override; 37911608Snikos.nikoleris@arm.com Fault writeMem(uint8_t *data, unsigned size, Addr addr, 38011608Snikos.nikoleris@arm.com Request::Flags flags, uint64_t *res) override; 3818733Sgeoffrey.blake@arm.com 38211169Sandreas.hansson@arm.com unsigned int readStCondFailures() const override { 38310319SAndreas.Sandberg@ARM.com return thread->readStCondFailures(); 38410319SAndreas.Sandberg@ARM.com } 38510319SAndreas.Sandberg@ARM.com 38611169Sandreas.hansson@arm.com void setStCondFailures(unsigned int sc_failures) override 3878733Sgeoffrey.blake@arm.com {} 3888733Sgeoffrey.blake@arm.com ///////////////////////////////////////////////////// 3898733Sgeoffrey.blake@arm.com 39011169Sandreas.hansson@arm.com Fault hwrei() override { return thread->hwrei(); } 39111169Sandreas.hansson@arm.com bool simPalCheck(int palFunc) override 39211169Sandreas.hansson@arm.com { return thread->simPalCheck(palFunc); } 39311168Sandreas.hansson@arm.com void wakeup(ThreadID tid) override { } 3942315SN/A // Assume that the normal CPU's call to syscall was successful. 3952332SN/A // The checker's state would have already been updated by the syscall. 39611877Sbrandon.potter@amd.com void syscall(int64_t callnum, Fault *fault) override { } 3972315SN/A 3982315SN/A void handleError() 3992315SN/A { 4002315SN/A if (exitOnError) 4012732Sktlim@umich.edu dumpAndExit(); 4022315SN/A } 4032732Sktlim@umich.edu 4048733Sgeoffrey.blake@arm.com bool checkFlags(Request *unverified_req, Addr vAddr, 4058733Sgeoffrey.blake@arm.com Addr pAddr, int flags); 4062315SN/A 4072732Sktlim@umich.edu void dumpAndExit(); 4082732Sktlim@umich.edu 40911169Sandreas.hansson@arm.com ThreadContext *tcBase() override { return tc; } 4102683Sktlim@umich.edu SimpleThread *threadBase() { return thread; } 4112315SN/A 4122315SN/A Result unverifiedResult; 4132669Sktlim@umich.edu Request *unverifiedReq; 4142679Sktlim@umich.edu uint8_t *unverifiedMemData; 4152315SN/A 4162315SN/A bool changedPC; 4172315SN/A bool willChangePC; 4188733Sgeoffrey.blake@arm.com TheISA::PCState newPCState; 4192315SN/A bool exitOnError; 4202354SN/A bool updateOnError; 4212732Sktlim@umich.edu bool warnOnlyOnLoadError; 4222315SN/A 4232315SN/A InstSeqNum youngestSN; 4242315SN/A}; 4252315SN/A 4262350SN/A/** 4272350SN/A * Templated Checker class. This Checker class is templated on the 4282350SN/A * DynInstPtr of the instruction type that will be verified. Proper 4292350SN/A * template instantiations of the Checker must be placed at the bottom 4302350SN/A * of checker/cpu.cc. 4312350SN/A */ 4328733Sgeoffrey.blake@arm.comtemplate <class Impl> 4332315SN/Aclass Checker : public CheckerCPU 4342315SN/A{ 4358733Sgeoffrey.blake@arm.com private: 4368733Sgeoffrey.blake@arm.com typedef typename Impl::DynInstPtr DynInstPtr; 4378733Sgeoffrey.blake@arm.com 4382315SN/A public: 4392315SN/A Checker(Params *p) 4409023Sgblack@eecs.umich.edu : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL) 4412315SN/A { } 4422315SN/A 4432840Sktlim@umich.edu void switchOut(); 4442315SN/A void takeOverFrom(BaseCPU *oldCPU); 4452315SN/A 44610379Sandreas.hansson@arm.com void advancePC(const Fault &fault); 4478733Sgeoffrey.blake@arm.com 4482732Sktlim@umich.edu void verify(DynInstPtr &inst); 4492315SN/A 4502315SN/A void validateInst(DynInstPtr &inst); 4512315SN/A void validateExecution(DynInstPtr &inst); 4522315SN/A void validateState(); 4532315SN/A 45410935Snilay@cs.wisc.edu void copyResult(DynInstPtr &inst, uint64_t mismatch_val, int start_idx); 4558733Sgeoffrey.blake@arm.com void handlePendingInt(); 4562732Sktlim@umich.edu 4572732Sktlim@umich.edu private: 4582732Sktlim@umich.edu void handleError(DynInstPtr &inst) 4592732Sktlim@umich.edu { 4602360SN/A if (exitOnError) { 4612732Sktlim@umich.edu dumpAndExit(inst); 4622360SN/A } else if (updateOnError) { 4632354SN/A updateThisCycle = true; 4642360SN/A } 4652732Sktlim@umich.edu } 4662732Sktlim@umich.edu 4672732Sktlim@umich.edu void dumpAndExit(DynInstPtr &inst); 4682732Sktlim@umich.edu 4692354SN/A bool updateThisCycle; 4702354SN/A 4712354SN/A DynInstPtr unverifiedInst; 4722354SN/A 4732315SN/A std::list<DynInstPtr> instList; 4742315SN/A typedef typename std::list<DynInstPtr>::iterator InstListIt; 4752315SN/A void dumpInsts(); 4762315SN/A}; 4772315SN/A 4782315SN/A#endif // __CPU_CHECKER_CPU_HH__ 479