cpu.hh revision 11169
12315SN/A/* 28733Sgeoffrey.blake@arm.com * Copyright (c) 2011 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48733Sgeoffrey.blake@arm.com * All rights reserved 58733Sgeoffrey.blake@arm.com * 68733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 78733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 88733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 98733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 108733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 118733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 128733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 138733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 148733Sgeoffrey.blake@arm.com * 152332SN/A * Copyright (c) 2006 The Regents of The University of Michigan 162315SN/A * All rights reserved. 172315SN/A * 182315SN/A * Redistribution and use in source and binary forms, with or without 192315SN/A * modification, are permitted provided that the following conditions are 202315SN/A * met: redistributions of source code must retain the above copyright 212315SN/A * notice, this list of conditions and the following disclaimer; 222315SN/A * redistributions in binary form must reproduce the above copyright 232315SN/A * notice, this list of conditions and the following disclaimer in the 242315SN/A * documentation and/or other materials provided with the distribution; 252315SN/A * neither the name of the copyright holders nor the names of its 262315SN/A * contributors may be used to endorse or promote products derived from 272315SN/A * this software without specific prior written permission. 282315SN/A * 292315SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302315SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312315SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322315SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332315SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342315SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352315SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362315SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372315SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382315SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392315SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402689Sktlim@umich.edu * 412689Sktlim@umich.edu * Authors: Kevin Lim 422315SN/A */ 432315SN/A 442315SN/A#ifndef __CPU_CHECKER_CPU_HH__ 452315SN/A#define __CPU_CHECKER_CPU_HH__ 462315SN/A 472315SN/A#include <list> 488229Snate@binkert.org#include <map> 492315SN/A#include <queue> 502315SN/A 512669Sktlim@umich.edu#include "arch/types.hh" 522315SN/A#include "base/statistics.hh" 532315SN/A#include "cpu/base.hh" 542315SN/A#include "cpu/base_dyn_inst.hh" 5510319SAndreas.Sandberg@ARM.com#include "cpu/exec_context.hh" 568229Snate@binkert.org#include "cpu/pc_event.hh" 572683Sktlim@umich.edu#include "cpu/simple_thread.hh" 582315SN/A#include "cpu/static_inst.hh" 598733Sgeoffrey.blake@arm.com#include "debug/Checker.hh" 608733Sgeoffrey.blake@arm.com#include "params/CheckerCPU.hh" 612315SN/A#include "sim/eventq.hh" 622315SN/A 632315SN/A// forward declarations 643468Sgblack@eecs.umich.edunamespace TheISA 653468Sgblack@eecs.umich.edu{ 666022Sgblack@eecs.umich.edu class TLB; 673468Sgblack@eecs.umich.edu} 682315SN/A 692315SN/Atemplate <class> 702315SN/Aclass BaseDynInst; 712680Sktlim@umich.educlass ThreadContext; 722669Sktlim@umich.educlass Request; 732315SN/A 742350SN/A/** 752350SN/A * CheckerCPU class. Dynamically verifies instructions as they are 762350SN/A * completed by making sure that the instruction and its results match 772350SN/A * the independent execution of the benchmark inside the checker. The 782350SN/A * checker verifies instructions in order, regardless of the order in 792350SN/A * which instructions complete. There are certain results that can 802350SN/A * not be verified, specifically the result of a store conditional or 812350SN/A * the values of uncached accesses. In these cases, and with 822350SN/A * instructions marked as "IsUnverifiable", the checker assumes that 832350SN/A * the value from the main CPU's execution is correct and simply 842680Sktlim@umich.edu * copies that value. It provides a CheckerThreadContext (see 852683Sktlim@umich.edu * checker/thread_context.hh) that provides hooks for updating the 862680Sktlim@umich.edu * Checker's state through any ThreadContext accesses. This allows the 872350SN/A * checker to be able to correctly verify instructions, even with 882680Sktlim@umich.edu * external accesses to the ThreadContext that change state. 892350SN/A */ 9010319SAndreas.Sandberg@ARM.comclass CheckerCPU : public BaseCPU, public ExecContext 912315SN/A{ 922315SN/A protected: 932315SN/A typedef TheISA::MachInst MachInst; 942669Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 952669Sktlim@umich.edu typedef TheISA::FloatRegBits FloatRegBits; 962315SN/A typedef TheISA::MiscReg MiscReg; 978832SAli.Saidi@ARM.com 988832SAli.Saidi@ARM.com /** id attached to all issued requests */ 998832SAli.Saidi@ARM.com MasterID masterId; 1002315SN/A public: 10111169Sandreas.hansson@arm.com void init() override; 1022315SN/A 1035529Snate@binkert.org typedef CheckerCPUParams Params; 1042315SN/A CheckerCPU(Params *p); 1052315SN/A virtual ~CheckerCPU(); 1062315SN/A 1072315SN/A void setSystem(System *system); 1082315SN/A 1099608Sandreas.hansson@arm.com void setIcachePort(MasterPort *icache_port); 1102679Sktlim@umich.edu 1119608Sandreas.hansson@arm.com void setDcachePort(MasterPort *dcache_port); 1122679Sktlim@umich.edu 11311169Sandreas.hansson@arm.com MasterPort &getDataPort() override 1148887Sgeoffrey.blake@arm.com { 1159176Sandreas.hansson@arm.com // the checker does not have ports on its own so return the 1169176Sandreas.hansson@arm.com // data port of the actual CPU core 1179176Sandreas.hansson@arm.com assert(dcachePort); 1188887Sgeoffrey.blake@arm.com return *dcachePort; 1198887Sgeoffrey.blake@arm.com } 1208887Sgeoffrey.blake@arm.com 12111169Sandreas.hansson@arm.com MasterPort &getInstPort() override 1228887Sgeoffrey.blake@arm.com { 1239176Sandreas.hansson@arm.com // the checker does not have ports on its own so return the 1249176Sandreas.hansson@arm.com // data port of the actual CPU core 1259176Sandreas.hansson@arm.com assert(icachePort); 1268887Sgeoffrey.blake@arm.com return *icachePort; 1278887Sgeoffrey.blake@arm.com } 1282679Sktlim@umich.edu 1299176Sandreas.hansson@arm.com protected: 1309176Sandreas.hansson@arm.com 1319176Sandreas.hansson@arm.com std::vector<Process*> workload; 1329176Sandreas.hansson@arm.com 1339176Sandreas.hansson@arm.com System *systemPtr; 1349176Sandreas.hansson@arm.com 1359608Sandreas.hansson@arm.com MasterPort *icachePort; 1369608Sandreas.hansson@arm.com MasterPort *dcachePort; 1372315SN/A 1382680Sktlim@umich.edu ThreadContext *tc; 1392315SN/A 1406022Sgblack@eecs.umich.edu TheISA::TLB *itb; 1416022Sgblack@eecs.umich.edu TheISA::TLB *dtb; 1422315SN/A 1432315SN/A Addr dbg_vtophys(Addr addr); 1442315SN/A 1452315SN/A union Result { 1462315SN/A uint64_t integer; 1472315SN/A double dbl; 1488733Sgeoffrey.blake@arm.com void set(uint64_t i) { integer = i; } 1498733Sgeoffrey.blake@arm.com void set(double d) { dbl = d; } 1508733Sgeoffrey.blake@arm.com void get(uint64_t& i) { i = integer; } 1518733Sgeoffrey.blake@arm.com void get(double& d) { d = dbl; } 1522315SN/A }; 1532315SN/A 1548733Sgeoffrey.blake@arm.com // ISAs like ARM can have multiple destination registers to check, 1558733Sgeoffrey.blake@arm.com // keep them all in a std::queue 1568733Sgeoffrey.blake@arm.com std::queue<Result> result; 1572315SN/A 1582679Sktlim@umich.edu // Pointer to the one memory request. 1592679Sktlim@umich.edu RequestPtr memReq; 1602315SN/A 1612315SN/A StaticInstPtr curStaticInst; 1628733Sgeoffrey.blake@arm.com StaticInstPtr curMacroStaticInst; 1632315SN/A 1642315SN/A // number of simulated instructions 1652315SN/A Counter numInst; 1662315SN/A Counter startNumInst; 1672315SN/A 1682315SN/A std::queue<int> miscRegIdxs; 1692315SN/A 1709176Sandreas.hansson@arm.com public: 1719176Sandreas.hansson@arm.com 1729176Sandreas.hansson@arm.com // Primary thread being run. 1739176Sandreas.hansson@arm.com SimpleThread *thread; 1749176Sandreas.hansson@arm.com 1758733Sgeoffrey.blake@arm.com TheISA::TLB* getITBPtr() { return itb; } 1768733Sgeoffrey.blake@arm.com TheISA::TLB* getDTBPtr() { return dtb; } 1778733Sgeoffrey.blake@arm.com 17811169Sandreas.hansson@arm.com virtual Counter totalInsts() const override 1798887Sgeoffrey.blake@arm.com { 1808887Sgeoffrey.blake@arm.com return 0; 1818887Sgeoffrey.blake@arm.com } 1828887Sgeoffrey.blake@arm.com 18311169Sandreas.hansson@arm.com virtual Counter totalOps() const override 1842315SN/A { 1852930Sktlim@umich.edu return 0; 1862315SN/A } 1872315SN/A 1882315SN/A // number of simulated loads 1892315SN/A Counter numLoad; 1902315SN/A Counter startNumLoad; 1912315SN/A 19211168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 19311168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 1942315SN/A 1952315SN/A // These functions are only used in CPU models that split 1962315SN/A // effective address computation from the actual memory access. 19711169Sandreas.hansson@arm.com void setEA(Addr EA) override 19811169Sandreas.hansson@arm.com { panic("CheckerCPU::setEA() not implemented\n"); } 19911169Sandreas.hansson@arm.com Addr getEA() const override 20011169Sandreas.hansson@arm.com { panic("CheckerCPU::getEA() not implemented\n"); } 2012315SN/A 2022315SN/A // The register accessor methods provide the index of the 2032315SN/A // instruction's operand (e.g., 0 or 1), not the architectural 2042315SN/A // register index, to simplify the implementation of register 2052315SN/A // renaming. We find the architectural register index by indexing 2062315SN/A // into the instruction's own operand index table. Note that a 2072315SN/A // raw pointer to the StaticInst is provided instead of a 2082315SN/A // ref-counted StaticInstPtr to redice overhead. This is fine as 2092315SN/A // long as these methods don't copy the pointer into any long-term 2102315SN/A // storage (which is pretty hard to imagine they would have reason 2112315SN/A // to do). 2122315SN/A 21311169Sandreas.hansson@arm.com IntReg readIntRegOperand(const StaticInst *si, int idx) override 2142315SN/A { 2152683Sktlim@umich.edu return thread->readIntReg(si->srcRegIdx(idx)); 2162315SN/A } 2172315SN/A 21811169Sandreas.hansson@arm.com FloatReg readFloatRegOperand(const StaticInst *si, int idx) override 2192315SN/A { 2209918Ssteve.reinhardt@amd.com int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base; 2212683Sktlim@umich.edu return thread->readFloatReg(reg_idx); 2222315SN/A } 2232315SN/A 22411169Sandreas.hansson@arm.com FloatRegBits readFloatRegOperandBits(const StaticInst *si, 22511169Sandreas.hansson@arm.com int idx) override 2262669Sktlim@umich.edu { 2279918Ssteve.reinhardt@amd.com int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base; 2282683Sktlim@umich.edu return thread->readFloatRegBits(reg_idx); 2292315SN/A } 2302315SN/A 23111169Sandreas.hansson@arm.com CCReg readCCRegOperand(const StaticInst *si, int idx) override 2329920Syasuko.eckert@amd.com { 2339920Syasuko.eckert@amd.com int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base; 2349920Syasuko.eckert@amd.com return thread->readCCReg(reg_idx); 2359920Syasuko.eckert@amd.com } 2369920Syasuko.eckert@amd.com 2378733Sgeoffrey.blake@arm.com template <class T> 2388733Sgeoffrey.blake@arm.com void setResult(T t) 2398733Sgeoffrey.blake@arm.com { 2408733Sgeoffrey.blake@arm.com Result instRes; 2418733Sgeoffrey.blake@arm.com instRes.set(t); 2428733Sgeoffrey.blake@arm.com result.push(instRes); 2438733Sgeoffrey.blake@arm.com } 2448733Sgeoffrey.blake@arm.com 24511169Sandreas.hansson@arm.com void setIntRegOperand(const StaticInst *si, int idx, 24611169Sandreas.hansson@arm.com IntReg val) override 2472315SN/A { 2482683Sktlim@umich.edu thread->setIntReg(si->destRegIdx(idx), val); 2498733Sgeoffrey.blake@arm.com setResult<uint64_t>(val); 2502315SN/A } 2512315SN/A 25211169Sandreas.hansson@arm.com void setFloatRegOperand(const StaticInst *si, int idx, 25311169Sandreas.hansson@arm.com FloatReg val) override 2542669Sktlim@umich.edu { 2559918Ssteve.reinhardt@amd.com int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base; 2562683Sktlim@umich.edu thread->setFloatReg(reg_idx, val); 2578733Sgeoffrey.blake@arm.com setResult<double>(val); 2582315SN/A } 2592315SN/A 2603735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, 26111169Sandreas.hansson@arm.com FloatRegBits val) override 2622315SN/A { 2639918Ssteve.reinhardt@amd.com int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base; 2642683Sktlim@umich.edu thread->setFloatRegBits(reg_idx, val); 2658733Sgeoffrey.blake@arm.com setResult<uint64_t>(val); 2662315SN/A } 2672315SN/A 26811169Sandreas.hansson@arm.com void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override 2699920Syasuko.eckert@amd.com { 2709920Syasuko.eckert@amd.com int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base; 2719920Syasuko.eckert@amd.com thread->setCCReg(reg_idx, val); 2729920Syasuko.eckert@amd.com setResult<uint64_t>(val); 2739920Syasuko.eckert@amd.com } 2749920Syasuko.eckert@amd.com 27511169Sandreas.hansson@arm.com bool readPredicate() override { return thread->readPredicate(); } 27611169Sandreas.hansson@arm.com void setPredicate(bool val) override 2778733Sgeoffrey.blake@arm.com { 2788733Sgeoffrey.blake@arm.com thread->setPredicate(val); 2798733Sgeoffrey.blake@arm.com } 2802669Sktlim@umich.edu 28111169Sandreas.hansson@arm.com TheISA::PCState pcState() const override { return thread->pcState(); } 28211169Sandreas.hansson@arm.com void pcState(const TheISA::PCState &val) override 2838733Sgeoffrey.blake@arm.com { 2848733Sgeoffrey.blake@arm.com DPRINTF(Checker, "Changing PC to %s, old PC %s.\n", 2858733Sgeoffrey.blake@arm.com val, thread->pcState()); 2868733Sgeoffrey.blake@arm.com thread->pcState(val); 2878733Sgeoffrey.blake@arm.com } 2888733Sgeoffrey.blake@arm.com Addr instAddr() { return thread->instAddr(); } 2898733Sgeoffrey.blake@arm.com Addr nextInstAddr() { return thread->nextInstAddr(); } 2908733Sgeoffrey.blake@arm.com MicroPC microPC() { return thread->microPC(); } 2918733Sgeoffrey.blake@arm.com ////////////////////////////////////////// 2922315SN/A 29310698Sandreas.hansson@arm.com MiscReg readMiscRegNoEffect(int misc_reg) const 2944172Ssaidi@eecs.umich.edu { 2954172Ssaidi@eecs.umich.edu return thread->readMiscRegNoEffect(misc_reg); 2964172Ssaidi@eecs.umich.edu } 2974172Ssaidi@eecs.umich.edu 29811169Sandreas.hansson@arm.com MiscReg readMiscReg(int misc_reg) override 2992315SN/A { 3002683Sktlim@umich.edu return thread->readMiscReg(misc_reg); 3012315SN/A } 3022315SN/A 3034172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 3042315SN/A { 30510034SGeoffrey.Blake@arm.com DPRINTF(Checker, "Setting misc reg %d with no effect to check later\n", misc_reg); 3064172Ssaidi@eecs.umich.edu miscRegIdxs.push(misc_reg); 3074172Ssaidi@eecs.umich.edu return thread->setMiscRegNoEffect(misc_reg, val); 3082315SN/A } 3092315SN/A 31011169Sandreas.hansson@arm.com void setMiscReg(int misc_reg, const MiscReg &val) override 3112315SN/A { 31210034SGeoffrey.Blake@arm.com DPRINTF(Checker, "Setting misc reg %d with effect to check later\n", misc_reg); 3132315SN/A miscRegIdxs.push(misc_reg); 3142683Sktlim@umich.edu return thread->setMiscReg(misc_reg, val); 3152315SN/A } 3162315SN/A 31711169Sandreas.hansson@arm.com MiscReg readMiscRegOperand(const StaticInst *si, int idx) override 3188733Sgeoffrey.blake@arm.com { 3199918Ssteve.reinhardt@amd.com int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base; 3208733Sgeoffrey.blake@arm.com return thread->readMiscReg(reg_idx); 3218733Sgeoffrey.blake@arm.com } 3228733Sgeoffrey.blake@arm.com 32311169Sandreas.hansson@arm.com void setMiscRegOperand(const StaticInst *si, int idx, 32411169Sandreas.hansson@arm.com const MiscReg &val) override 3258733Sgeoffrey.blake@arm.com { 3269918Ssteve.reinhardt@amd.com int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base; 32710034SGeoffrey.Blake@arm.com return this->setMiscReg(reg_idx, val); 3288733Sgeoffrey.blake@arm.com } 3298888Sgeoffrey.blake@arm.com 3308888Sgeoffrey.blake@arm.com#if THE_ISA == MIPS_ISA 33110319SAndreas.Sandberg@ARM.com MiscReg readRegOtherThread(int misc_reg, ThreadID tid) 3328888Sgeoffrey.blake@arm.com { 3338888Sgeoffrey.blake@arm.com panic("MIPS MT not defined for CheckerCPU.\n"); 3348888Sgeoffrey.blake@arm.com return 0; 3358888Sgeoffrey.blake@arm.com } 3368888Sgeoffrey.blake@arm.com 33710319SAndreas.Sandberg@ARM.com void setRegOtherThread(int misc_reg, MiscReg val, ThreadID tid) 3388888Sgeoffrey.blake@arm.com { 3398888Sgeoffrey.blake@arm.com panic("MIPS MT not defined for CheckerCPU.\n"); 3408888Sgeoffrey.blake@arm.com } 3418888Sgeoffrey.blake@arm.com#endif 3428888Sgeoffrey.blake@arm.com 3438733Sgeoffrey.blake@arm.com ///////////////////////////////////////// 3448733Sgeoffrey.blake@arm.com 3458733Sgeoffrey.blake@arm.com void recordPCChange(const TheISA::PCState &val) 3468733Sgeoffrey.blake@arm.com { 3478733Sgeoffrey.blake@arm.com changedPC = true; 3488733Sgeoffrey.blake@arm.com newPCState = val; 3498733Sgeoffrey.blake@arm.com } 3502315SN/A 35111169Sandreas.hansson@arm.com void demapPage(Addr vaddr, uint64_t asn) override 3525358Sgblack@eecs.umich.edu { 3535358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 3545358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 3555358Sgblack@eecs.umich.edu } 3565358Sgblack@eecs.umich.edu 35710529Smorr@cs.wisc.edu // monitor/mwait funtions 35811169Sandreas.hansson@arm.com void armMonitor(Addr address) override 35911169Sandreas.hansson@arm.com { BaseCPU::armMonitor(0, address); } 36011169Sandreas.hansson@arm.com bool mwait(PacketPtr pkt) override { return BaseCPU::mwait(0, pkt); } 36111169Sandreas.hansson@arm.com void mwaitAtomic(ThreadContext *tc) override 36211148Smitch.hayenga@arm.com { return BaseCPU::mwaitAtomic(0, tc, thread->dtb); } 36311169Sandreas.hansson@arm.com AddressMonitor *getAddrMonitor() override 36411169Sandreas.hansson@arm.com { return BaseCPU::getCpuAddrMonitor(0); } 36510529Smorr@cs.wisc.edu 3665358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 3675358Sgblack@eecs.umich.edu { 3685358Sgblack@eecs.umich.edu this->itb->demapPage(vaddr, asn); 3695358Sgblack@eecs.umich.edu } 3705358Sgblack@eecs.umich.edu 3715358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 3725358Sgblack@eecs.umich.edu { 3735358Sgblack@eecs.umich.edu this->dtb->demapPage(vaddr, asn); 3745358Sgblack@eecs.umich.edu } 3755358Sgblack@eecs.umich.edu 37611169Sandreas.hansson@arm.com Fault readMem(Addr addr, uint8_t *data, unsigned size, 37711169Sandreas.hansson@arm.com unsigned flags) override; 3788733Sgeoffrey.blake@arm.com Fault writeMem(uint8_t *data, unsigned size, 37911169Sandreas.hansson@arm.com Addr addr, unsigned flags, uint64_t *res) override; 3808733Sgeoffrey.blake@arm.com 38111169Sandreas.hansson@arm.com unsigned int readStCondFailures() const override { 38210319SAndreas.Sandberg@ARM.com return thread->readStCondFailures(); 38310319SAndreas.Sandberg@ARM.com } 38410319SAndreas.Sandberg@ARM.com 38511169Sandreas.hansson@arm.com void setStCondFailures(unsigned int sc_failures) override 3868733Sgeoffrey.blake@arm.com {} 3878733Sgeoffrey.blake@arm.com ///////////////////////////////////////////////////// 3888733Sgeoffrey.blake@arm.com 38911169Sandreas.hansson@arm.com Fault hwrei() override { return thread->hwrei(); } 39011169Sandreas.hansson@arm.com bool simPalCheck(int palFunc) override 39111169Sandreas.hansson@arm.com { return thread->simPalCheck(palFunc); } 39211168Sandreas.hansson@arm.com void wakeup(ThreadID tid) override { } 3932315SN/A // Assume that the normal CPU's call to syscall was successful. 3942332SN/A // The checker's state would have already been updated by the syscall. 39511169Sandreas.hansson@arm.com void syscall(int64_t callnum) override { } 3962315SN/A 3972315SN/A void handleError() 3982315SN/A { 3992315SN/A if (exitOnError) 4002732Sktlim@umich.edu dumpAndExit(); 4012315SN/A } 4022732Sktlim@umich.edu 4038733Sgeoffrey.blake@arm.com bool checkFlags(Request *unverified_req, Addr vAddr, 4048733Sgeoffrey.blake@arm.com Addr pAddr, int flags); 4052315SN/A 4062732Sktlim@umich.edu void dumpAndExit(); 4072732Sktlim@umich.edu 40811169Sandreas.hansson@arm.com ThreadContext *tcBase() override { return tc; } 4092683Sktlim@umich.edu SimpleThread *threadBase() { return thread; } 4102315SN/A 4112315SN/A Result unverifiedResult; 4122669Sktlim@umich.edu Request *unverifiedReq; 4132679Sktlim@umich.edu uint8_t *unverifiedMemData; 4142315SN/A 4152315SN/A bool changedPC; 4162315SN/A bool willChangePC; 4178733Sgeoffrey.blake@arm.com TheISA::PCState newPCState; 4182315SN/A bool exitOnError; 4192354SN/A bool updateOnError; 4202732Sktlim@umich.edu bool warnOnlyOnLoadError; 4212315SN/A 4222315SN/A InstSeqNum youngestSN; 4232315SN/A}; 4242315SN/A 4252350SN/A/** 4262350SN/A * Templated Checker class. This Checker class is templated on the 4272350SN/A * DynInstPtr of the instruction type that will be verified. Proper 4282350SN/A * template instantiations of the Checker must be placed at the bottom 4292350SN/A * of checker/cpu.cc. 4302350SN/A */ 4318733Sgeoffrey.blake@arm.comtemplate <class Impl> 4322315SN/Aclass Checker : public CheckerCPU 4332315SN/A{ 4348733Sgeoffrey.blake@arm.com private: 4358733Sgeoffrey.blake@arm.com typedef typename Impl::DynInstPtr DynInstPtr; 4368733Sgeoffrey.blake@arm.com 4372315SN/A public: 4382315SN/A Checker(Params *p) 4399023Sgblack@eecs.umich.edu : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL) 4402315SN/A { } 4412315SN/A 4422840Sktlim@umich.edu void switchOut(); 4432315SN/A void takeOverFrom(BaseCPU *oldCPU); 4442315SN/A 44510379Sandreas.hansson@arm.com void advancePC(const Fault &fault); 4468733Sgeoffrey.blake@arm.com 4472732Sktlim@umich.edu void verify(DynInstPtr &inst); 4482315SN/A 4492315SN/A void validateInst(DynInstPtr &inst); 4502315SN/A void validateExecution(DynInstPtr &inst); 4512315SN/A void validateState(); 4522315SN/A 45310935Snilay@cs.wisc.edu void copyResult(DynInstPtr &inst, uint64_t mismatch_val, int start_idx); 4548733Sgeoffrey.blake@arm.com void handlePendingInt(); 4552732Sktlim@umich.edu 4562732Sktlim@umich.edu private: 4572732Sktlim@umich.edu void handleError(DynInstPtr &inst) 4582732Sktlim@umich.edu { 4592360SN/A if (exitOnError) { 4602732Sktlim@umich.edu dumpAndExit(inst); 4612360SN/A } else if (updateOnError) { 4622354SN/A updateThisCycle = true; 4632360SN/A } 4642732Sktlim@umich.edu } 4652732Sktlim@umich.edu 4662732Sktlim@umich.edu void dumpAndExit(DynInstPtr &inst); 4672732Sktlim@umich.edu 4682354SN/A bool updateThisCycle; 4692354SN/A 4702354SN/A DynInstPtr unverifiedInst; 4712354SN/A 4722315SN/A std::list<DynInstPtr> instList; 4732315SN/A typedef typename std::list<DynInstPtr>::iterator InstListIt; 4742315SN/A void dumpInsts(); 4752315SN/A}; 4762315SN/A 4772315SN/A#endif // __CPU_CHECKER_CPU_HH__ 478