cpu.cc revision 8793
12330SN/A/* 22330SN/A * Copyright (c) 2006 The Regents of The University of Michigan 32330SN/A * All rights reserved. 42330SN/A * 52330SN/A * Redistribution and use in source and binary forms, with or without 62330SN/A * modification, are permitted provided that the following conditions are 72330SN/A * met: redistributions of source code must retain the above copyright 82330SN/A * notice, this list of conditions and the following disclaimer; 92330SN/A * redistributions in binary form must reproduce the above copyright 102330SN/A * notice, this list of conditions and the following disclaimer in the 112330SN/A * documentation and/or other materials provided with the distribution; 122330SN/A * neither the name of the copyright holders nor the names of its 132330SN/A * contributors may be used to endorse or promote products derived from 142330SN/A * this software without specific prior written permission. 152330SN/A * 162330SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172330SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182330SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192330SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202330SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212330SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222330SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232330SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242330SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252330SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262330SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272689Sktlim@umich.edu * 282689Sktlim@umich.edu * Authors: Kevin Lim 292330SN/A */ 302292SN/A 312292SN/A#include <list> 322292SN/A#include <string> 332292SN/A 342683Sktlim@umich.edu#include "arch/kernel_stats.hh" 352680Sktlim@umich.edu#include "arch/vtophys.hh" 362292SN/A#include "cpu/checker/cpu.hh" 372678Sktlim@umich.edu#include "cpu/base.hh" 382683Sktlim@umich.edu#include "cpu/simple_thread.hh" 392678Sktlim@umich.edu#include "cpu/static_inst.hh" 402683Sktlim@umich.edu#include "cpu/thread_context.hh" 412678Sktlim@umich.edu 422678Sktlim@umich.eduusing namespace std; 432292SN/A//The CheckerCPU does alpha only 442292SN/Ausing namespace AlphaISA; 452292SN/A 462292SN/Avoid 472330SN/ACheckerCPU::init() 482330SN/A{ 492330SN/A} 502292SN/A 512292SN/ACheckerCPU::CheckerCPU(Params *p) 522330SN/A : BaseCPU(p), thread(NULL), tc(NULL) 532330SN/A{ 542330SN/A memReq = NULL; 552330SN/A 562330SN/A numInst = 0; 572330SN/A startNumInst = 0; 582292SN/A numLoad = 0; 592683Sktlim@umich.edu startNumLoad = 0; 602683Sktlim@umich.edu youngestSN = 0; 612292SN/A 622683Sktlim@umich.edu changedPC = willChangePC = changedNextPC = false; 632292SN/A 642791Sktlim@umich.edu exitOnError = p->exitOnError; 652791Sktlim@umich.edu warnOnlyOnLoadError = p->warnOnlyOnLoadError; 662292SN/A itb = p->itb; 672683Sktlim@umich.edu dtb = p->dtb; 682683Sktlim@umich.edu systemPtr = NULL; 692683Sktlim@umich.edu process = p->process; 702683Sktlim@umich.edu thread = new SimpleThread(this, /* thread_num */ 0, process); 712683Sktlim@umich.edu 722683Sktlim@umich.edu tc = thread->getTC(); 732683Sktlim@umich.edu threadContexts.push_back(tc); 742683Sktlim@umich.edu 752683Sktlim@umich.edu result.integer = 0; 762683Sktlim@umich.edu} 772683Sktlim@umich.edu 782683Sktlim@umich.eduCheckerCPU::~CheckerCPU() 792683Sktlim@umich.edu{ 802683Sktlim@umich.edu} 812683Sktlim@umich.edu 822683Sktlim@umich.eduvoid 832683Sktlim@umich.eduCheckerCPU::setSystem(System *system) 842683Sktlim@umich.edu{ 852683Sktlim@umich.edu systemPtr = system; 862683Sktlim@umich.edu 872683Sktlim@umich.edu thread = new SimpleThread(this, 0, systemPtr, itb, dtb, false); 882683Sktlim@umich.edu 892683Sktlim@umich.edu tc = thread->getTC(); 902683Sktlim@umich.edu threadContexts.push_back(tc); 912690Sktlim@umich.edu delete thread->kernelStats; 922690Sktlim@umich.edu thread->kernelStats = NULL; 932683Sktlim@umich.edu} 942683Sktlim@umich.edu 952690Sktlim@umich.eduvoid 962690Sktlim@umich.eduCheckerCPU::setIcachePort(Port *icache_port) 972683Sktlim@umich.edu{ 982683Sktlim@umich.edu icachePort = icache_port; 992683Sktlim@umich.edu} 1002683Sktlim@umich.edu 1012683Sktlim@umich.eduvoid 1022683Sktlim@umich.eduCheckerCPU::setDcachePort(Port *dcache_port) 1032683Sktlim@umich.edu{ 1042683Sktlim@umich.edu dcachePort = dcache_port; 1052683Sktlim@umich.edu} 1062683Sktlim@umich.edu 1072678Sktlim@umich.eduvoid 1082292SN/ACheckerCPU::serialize(ostream &os) 1092683Sktlim@umich.edu{ 1102683Sktlim@umich.edu/* 1112292SN/A BaseCPU::serialize(os); 1122683Sktlim@umich.edu SERIALIZE_SCALAR(inst); 1132683Sktlim@umich.edu nameOut(os, csprintf("%s.xc", name())); 1142683Sktlim@umich.edu thread->serialize(os); 1152683Sktlim@umich.edu cacheCompletionEvent.serialize(os); 1162683Sktlim@umich.edu*/ 1172683Sktlim@umich.edu} 1182683Sktlim@umich.edu 1192683Sktlim@umich.eduvoid 1202683Sktlim@umich.eduCheckerCPU::unserialize(Checkpoint *cp, const string §ion) 1212683Sktlim@umich.edu{ 1222683Sktlim@umich.edu/* 1232683Sktlim@umich.edu BaseCPU::unserialize(cp, section); 1242683Sktlim@umich.edu UNSERIALIZE_SCALAR(inst); 1252683Sktlim@umich.edu thread->unserialize(cp, csprintf("%s.xc", section)); 1262683Sktlim@umich.edu*/ 1272683Sktlim@umich.edu} 1282683Sktlim@umich.edu 1292683Sktlim@umich.edutemplate <class T> 1302683Sktlim@umich.eduFault 1312683Sktlim@umich.eduCheckerCPU::read(Addr addr, T &data, unsigned flags) 1322683Sktlim@umich.edu{ 1332683Sktlim@umich.edu // need to fill in CPU & thread IDs here 1342683Sktlim@umich.edu memReq = new Request(); 1352683Sktlim@umich.edu 1362683Sktlim@umich.edu memReq->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 1372683Sktlim@umich.edu 1382683Sktlim@umich.edu // translate to physical address 1392683Sktlim@umich.edu dtb->translateAtomic(memReq, tc, false); 1402683Sktlim@umich.edu 1412683Sktlim@umich.edu PacketPtr pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast); 1422683Sktlim@umich.edu 1432683Sktlim@umich.edu pkt->dataStatic(&data); 1442683Sktlim@umich.edu 1452683Sktlim@umich.edu if (!(memReq->isUncacheable())) { 1462683Sktlim@umich.edu // Access memory to see if we have the same data 1472683Sktlim@umich.edu dcachePort->sendFunctional(pkt); 1482683Sktlim@umich.edu } else { 1492683Sktlim@umich.edu // Assume the data is correct if it's an uncached access 1502683Sktlim@umich.edu memcpy(&data, &unverifiedResult.integer, sizeof(T)); 1512292SN/A } 1522292SN/A 1532292SN/A delete pkt; 1542292SN/A 1552292SN/A return NoFault; 1562690Sktlim@umich.edu} 1572683Sktlim@umich.edu 1582683Sktlim@umich.edu#ifndef DOXYGEN_SHOULD_SKIP_THIS 1592292SN/A 1602683Sktlim@umich.edutemplate 1612683Sktlim@umich.eduFault 1622292SN/ACheckerCPU::read(Addr addr, uint64_t &data, unsigned flags); 1632292SN/A 1642683Sktlim@umich.edutemplate 1652292SN/AFault 1662292SN/ACheckerCPU::read(Addr addr, uint32_t &data, unsigned flags); 1672292SN/A 1682292SN/Atemplate 1692292SN/AFault 1702330SN/ACheckerCPU::read(Addr addr, uint16_t &data, unsigned flags); 1712683Sktlim@umich.edu 1722683Sktlim@umich.edutemplate 1732683Sktlim@umich.eduFault 1742683Sktlim@umich.eduCheckerCPU::read(Addr addr, uint8_t &data, unsigned flags); 1752683Sktlim@umich.edu 1762683Sktlim@umich.edu#endif //DOXYGEN_SHOULD_SKIP_THIS 1772683Sktlim@umich.edu 1782683Sktlim@umich.edutemplate<> 1792292SN/AFault 1802678Sktlim@umich.eduCheckerCPU::read(Addr addr, double &data, unsigned flags) 1812678Sktlim@umich.edu{ 1822292SN/A return read(addr, *(uint64_t*)&data, flags); 1832292SN/A} 1842292SN/A 1852292SN/Atemplate<> 1862292SN/AFault 1872292SN/ACheckerCPU::read(Addr addr, float &data, unsigned flags) 1882683Sktlim@umich.edu{ 1892292SN/A return read(addr, *(uint32_t*)&data, flags); 1902683Sktlim@umich.edu} 1912683Sktlim@umich.edu 1922683Sktlim@umich.edutemplate<> 1932683Sktlim@umich.eduFault 1942292SN/ACheckerCPU::read(Addr addr, int32_t &data, unsigned flags) 1952690Sktlim@umich.edu{ 1962292SN/A return read(addr, (uint32_t&)data, flags); 1972292SN/A} 1982292SN/A 1992292SN/Atemplate <class T> 2002292SN/AFault 2012292SN/ACheckerCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 2022292SN/A{ 2032292SN/A // need to fill in CPU & thread IDs here 2042292SN/A memReq = new Request(); 2052292SN/A 2062292SN/A memReq->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 2072292SN/A 2082292SN/A // translate to physical address 2092292SN/A dtb->translateAtomic(memReq, tc, true); 2102292SN/A 2112292SN/A // Can compare the write data and result only if it's cacheable, 2122292SN/A // not a store conditional, or is a store conditional that 2132292SN/A // succeeded. 2142292SN/A // @todo: Verify that actual memory matches up with these values. 2152292SN/A // Right now it only verifies that the instruction data is the 2162292SN/A // same as what was in the request that got sent to memory; there 2172292SN/A // is no verification that it is the same as what is in memory. 2182292SN/A // This is because the LSQ would have to be snooped in the CPU to 2192292SN/A // verify this data. 2202292SN/A if (unverifiedReq && 221 !(unverifiedReq->isUncacheable()) && 222 (!(unverifiedReq->isLLSC()) || 223 ((unverifiedReq->isLLSC()) && 224 unverifiedReq->getExtraData() == 1))) { 225 T inst_data; 226/* 227 // This code would work if the LSQ allowed for snooping. 228 PacketPtr pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast); 229 pkt.dataStatic(&inst_data); 230 231 dcachePort->sendFunctional(pkt); 232 233 delete pkt; 234*/ 235 memcpy(&inst_data, unverifiedMemData, sizeof(T)); 236 237 if (data != inst_data) { 238 warn("%lli: Store value does not match value in memory! " 239 "Instruction: %#x, memory: %#x", 240 curTick(), inst_data, data); 241 handleError(); 242 } 243 } 244 245 // Assume the result was the same as the one passed in. This checker 246 // doesn't check if the SC should succeed or fail, it just checks the 247 // value. 248 if (res && unverifiedReq->scResultValid()) 249 *res = unverifiedReq->getExtraData(); 250 251 return NoFault; 252} 253 254 255#ifndef DOXYGEN_SHOULD_SKIP_THIS 256template 257Fault 258CheckerCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res); 259 260template 261Fault 262CheckerCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res); 263 264template 265Fault 266CheckerCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res); 267 268template 269Fault 270CheckerCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res); 271 272#endif //DOXYGEN_SHOULD_SKIP_THIS 273 274template<> 275Fault 276CheckerCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 277{ 278 return write(*(uint64_t*)&data, addr, flags, res); 279} 280 281template<> 282Fault 283CheckerCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 284{ 285 return write(*(uint32_t*)&data, addr, flags, res); 286} 287 288template<> 289Fault 290CheckerCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 291{ 292 return write((uint32_t)data, addr, flags, res); 293} 294 295 296Addr 297CheckerCPU::dbg_vtophys(Addr addr) 298{ 299 return vtophys(tc, addr); 300} 301 302bool 303CheckerCPU::checkFlags(Request *req) 304{ 305 // Remove any dynamic flags that don't have to do with the request itself. 306 unsigned flags = unverifiedReq->getFlags(); 307 unsigned mask = LOCKED | PHYSICAL | VPTE | ALTMODE | UNCACHEABLE | PREFETCH; 308 flags = flags & (mask); 309 if (flags == req->getFlags()) { 310 return false; 311 } else { 312 return true; 313 } 314} 315 316void 317CheckerCPU::dumpAndExit() 318{ 319 warn("%lli: Checker PC:%#x, next PC:%#x", 320 curTick(), thread->readPC(), thread->readNextPC()); 321 panic("Checker found an error!"); 322} 323