cpu.cc revision 13954
12789Sktlim@umich.edu/* 213954Sgiacomo.gabrielli@arm.com * Copyright (c) 2011,2013,2017-2018 ARM Limited 38733Sgeoffrey.blake@arm.com * All rights reserved 48733Sgeoffrey.blake@arm.com * 58733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 68733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 78733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 88733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 98733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 108733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 118733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 128733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 138733Sgeoffrey.blake@arm.com * 142789Sktlim@umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 152789Sktlim@umich.edu * All rights reserved. 162789Sktlim@umich.edu * 172789Sktlim@umich.edu * Redistribution and use in source and binary forms, with or without 182789Sktlim@umich.edu * modification, are permitted provided that the following conditions are 192789Sktlim@umich.edu * met: redistributions of source code must retain the above copyright 202789Sktlim@umich.edu * notice, this list of conditions and the following disclaimer; 212789Sktlim@umich.edu * redistributions in binary form must reproduce the above copyright 222789Sktlim@umich.edu * notice, this list of conditions and the following disclaimer in the 232789Sktlim@umich.edu * documentation and/or other materials provided with the distribution; 242789Sktlim@umich.edu * neither the name of the copyright holders nor the names of its 252789Sktlim@umich.edu * contributors may be used to endorse or promote products derived from 262789Sktlim@umich.edu * this software without specific prior written permission. 272789Sktlim@umich.edu * 282789Sktlim@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292789Sktlim@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302789Sktlim@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312789Sktlim@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322789Sktlim@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332789Sktlim@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342789Sktlim@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352789Sktlim@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362789Sktlim@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372789Sktlim@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382789Sktlim@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392789Sktlim@umich.edu * 402789Sktlim@umich.edu * Authors: Kevin Lim 418733Sgeoffrey.blake@arm.com * Geoffrey Blake 422789Sktlim@umich.edu */ 432789Sktlim@umich.edu 4411793Sbrandon.potter@amd.com#include "cpu/checker/cpu.hh" 4511793Sbrandon.potter@amd.com 462789Sktlim@umich.edu#include <list> 472789Sktlim@umich.edu#include <string> 482789Sktlim@umich.edu 4910687SAndreas.Sandberg@ARM.com#include "arch/generic/tlb.hh" 508793Sgblack@eecs.umich.edu#include "arch/vtophys.hh" 512789Sktlim@umich.edu#include "cpu/base.hh" 522789Sktlim@umich.edu#include "cpu/simple_thread.hh" 533348Sbinkertn@umich.edu#include "cpu/static_inst.hh" 542789Sktlim@umich.edu#include "cpu/thread_context.hh" 5513954Sgiacomo.gabrielli@arm.com#include "cpu/utils.hh" 568733Sgeoffrey.blake@arm.com#include "params/CheckerCPU.hh" 578887Sgeoffrey.blake@arm.com#include "sim/full_system.hh" 582789Sktlim@umich.edu 592789Sktlim@umich.eduusing namespace std; 608733Sgeoffrey.blake@arm.comusing namespace TheISA; 612789Sktlim@umich.edu 622789Sktlim@umich.eduvoid 632789Sktlim@umich.eduCheckerCPU::init() 642789Sktlim@umich.edu{ 6512680Sgiacomo.travaglini@arm.com masterId = systemPtr->getMasterId(this); 662789Sktlim@umich.edu} 672789Sktlim@umich.edu 682789Sktlim@umich.eduCheckerCPU::CheckerCPU(Params *p) 699176Sandreas.hansson@arm.com : BaseCPU(p, true), systemPtr(NULL), icachePort(NULL), dcachePort(NULL), 7013453Srekai.gonzalezalberquilla@arm.com tc(NULL), thread(NULL), 7113453Srekai.gonzalezalberquilla@arm.com unverifiedReq(nullptr), 7213453Srekai.gonzalezalberquilla@arm.com unverifiedMemData(nullptr) 732789Sktlim@umich.edu{ 748733Sgeoffrey.blake@arm.com curStaticInst = NULL; 758733Sgeoffrey.blake@arm.com curMacroStaticInst = NULL; 762789Sktlim@umich.edu 772789Sktlim@umich.edu numInst = 0; 782789Sktlim@umich.edu startNumInst = 0; 792789Sktlim@umich.edu numLoad = 0; 802789Sktlim@umich.edu startNumLoad = 0; 812789Sktlim@umich.edu youngestSN = 0; 822789Sktlim@umich.edu 8310034SGeoffrey.Blake@arm.com changedPC = willChangePC = false; 842789Sktlim@umich.edu 852789Sktlim@umich.edu exitOnError = p->exitOnError; 862789Sktlim@umich.edu warnOnlyOnLoadError = p->warnOnlyOnLoadError; 872789Sktlim@umich.edu itb = p->itb; 882789Sktlim@umich.edu dtb = p->dtb; 898733Sgeoffrey.blake@arm.com workload = p->workload; 902789Sktlim@umich.edu 918733Sgeoffrey.blake@arm.com updateOnError = true; 922789Sktlim@umich.edu} 932789Sktlim@umich.edu 942789Sktlim@umich.eduCheckerCPU::~CheckerCPU() 952789Sktlim@umich.edu{ 962789Sktlim@umich.edu} 972789Sktlim@umich.edu 982789Sktlim@umich.eduvoid 992789Sktlim@umich.eduCheckerCPU::setSystem(System *system) 1002789Sktlim@umich.edu{ 1019384SAndreas.Sandberg@arm.com const Params *p(dynamic_cast<const Params *>(_params)); 1029384SAndreas.Sandberg@arm.com 1032789Sktlim@umich.edu systemPtr = system; 1042789Sktlim@umich.edu 1058887Sgeoffrey.blake@arm.com if (FullSystem) { 1069384SAndreas.Sandberg@arm.com thread = new SimpleThread(this, 0, systemPtr, itb, dtb, 1079384SAndreas.Sandberg@arm.com p->isa[0], false); 1088887Sgeoffrey.blake@arm.com } else { 1098887Sgeoffrey.blake@arm.com thread = new SimpleThread(this, 0, systemPtr, 1108887Sgeoffrey.blake@arm.com workload.size() ? workload[0] : NULL, 1119384SAndreas.Sandberg@arm.com itb, dtb, p->isa[0]); 1128887Sgeoffrey.blake@arm.com } 1132789Sktlim@umich.edu 1142789Sktlim@umich.edu tc = thread->getTC(); 1152789Sktlim@umich.edu threadContexts.push_back(tc); 1162789Sktlim@umich.edu thread->kernelStats = NULL; 1178887Sgeoffrey.blake@arm.com // Thread should never be null after this 1188887Sgeoffrey.blake@arm.com assert(thread != NULL); 1192789Sktlim@umich.edu} 1202789Sktlim@umich.edu 1212789Sktlim@umich.eduvoid 1229608Sandreas.hansson@arm.comCheckerCPU::setIcachePort(MasterPort *icache_port) 1232789Sktlim@umich.edu{ 1242789Sktlim@umich.edu icachePort = icache_port; 1252789Sktlim@umich.edu} 1262789Sktlim@umich.edu 1272789Sktlim@umich.eduvoid 1289608Sandreas.hansson@arm.comCheckerCPU::setDcachePort(MasterPort *dcache_port) 1292789Sktlim@umich.edu{ 1302789Sktlim@umich.edu dcachePort = dcache_port; 1312789Sktlim@umich.edu} 1322789Sktlim@umich.edu 1332789Sktlim@umich.eduvoid 13410905Sandreas.sandberg@arm.comCheckerCPU::serialize(ostream &os) const 1352789Sktlim@umich.edu{ 1362789Sktlim@umich.edu} 1372789Sktlim@umich.edu 1382789Sktlim@umich.eduvoid 13910905Sandreas.sandberg@arm.comCheckerCPU::unserialize(CheckpointIn &cp) 1402789Sktlim@umich.edu{ 1412789Sktlim@umich.edu} 1422789Sktlim@umich.edu 14313954Sgiacomo.gabrielli@arm.comRequestPtr 14413954Sgiacomo.gabrielli@arm.comCheckerCPU::genMemFragmentRequest(Addr frag_addr, int size, 14513954Sgiacomo.gabrielli@arm.com Request::Flags flags, 14613954Sgiacomo.gabrielli@arm.com const std::vector<bool>& byte_enable, 14713954Sgiacomo.gabrielli@arm.com int& frag_size, int& size_left) const 14813954Sgiacomo.gabrielli@arm.com{ 14913954Sgiacomo.gabrielli@arm.com frag_size = std::min( 15013954Sgiacomo.gabrielli@arm.com cacheLineSize() - addrBlockOffset(frag_addr, cacheLineSize()), 15113954Sgiacomo.gabrielli@arm.com (Addr) size_left); 15213954Sgiacomo.gabrielli@arm.com size_left -= frag_size; 15313954Sgiacomo.gabrielli@arm.com 15413954Sgiacomo.gabrielli@arm.com RequestPtr mem_req; 15513954Sgiacomo.gabrielli@arm.com 15613954Sgiacomo.gabrielli@arm.com if (!byte_enable.empty()) { 15713954Sgiacomo.gabrielli@arm.com // Set up byte-enable mask for the current fragment 15813954Sgiacomo.gabrielli@arm.com auto it_start = byte_enable.cbegin() + (size - (frag_size + 15913954Sgiacomo.gabrielli@arm.com size_left)); 16013954Sgiacomo.gabrielli@arm.com auto it_end = byte_enable.cbegin() + (size - size_left); 16113954Sgiacomo.gabrielli@arm.com if (isAnyActiveElement(it_start, it_end)) { 16213954Sgiacomo.gabrielli@arm.com mem_req = std::make_shared<Request>(0, frag_addr, frag_size, 16313954Sgiacomo.gabrielli@arm.com flags, masterId, thread->pcState().instAddr(), 16413954Sgiacomo.gabrielli@arm.com tc->contextId()); 16513954Sgiacomo.gabrielli@arm.com mem_req->setByteEnable(std::vector<bool>(it_start, it_end)); 16613954Sgiacomo.gabrielli@arm.com } 16713954Sgiacomo.gabrielli@arm.com } else { 16813954Sgiacomo.gabrielli@arm.com mem_req = std::make_shared<Request>(0, frag_addr, frag_size, 16913954Sgiacomo.gabrielli@arm.com flags, masterId, thread->pcState().instAddr(), 17013954Sgiacomo.gabrielli@arm.com tc->contextId()); 17113954Sgiacomo.gabrielli@arm.com } 17213954Sgiacomo.gabrielli@arm.com 17313954Sgiacomo.gabrielli@arm.com return mem_req; 17413954Sgiacomo.gabrielli@arm.com} 17513954Sgiacomo.gabrielli@arm.com 1762789Sktlim@umich.eduFault 17711608Snikos.nikoleris@arm.comCheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size, 17813954Sgiacomo.gabrielli@arm.com Request::Flags flags, 17913954Sgiacomo.gabrielli@arm.com const std::vector<bool>& byteEnable) 1802789Sktlim@umich.edu{ 1818733Sgeoffrey.blake@arm.com Fault fault = NoFault; 1828733Sgeoffrey.blake@arm.com bool checked_flags = false; 1838733Sgeoffrey.blake@arm.com bool flags_match = true; 1848733Sgeoffrey.blake@arm.com Addr pAddr = 0x0; 1852789Sktlim@umich.edu 18613954Sgiacomo.gabrielli@arm.com Addr frag_addr = addr; 18713954Sgiacomo.gabrielli@arm.com int frag_size = 0; 18813954Sgiacomo.gabrielli@arm.com int size_left = size; 18913954Sgiacomo.gabrielli@arm.com bool predicate; 1902789Sktlim@umich.edu 1918733Sgeoffrey.blake@arm.com // Need to account for multiple accesses like the Atomic and TimingSimple 1928733Sgeoffrey.blake@arm.com while (1) { 19313954Sgiacomo.gabrielli@arm.com RequestPtr mem_req = genMemFragmentRequest(frag_addr, size, flags, 19413954Sgiacomo.gabrielli@arm.com byteEnable, frag_size, 19513954Sgiacomo.gabrielli@arm.com size_left); 19613954Sgiacomo.gabrielli@arm.com 19713954Sgiacomo.gabrielli@arm.com predicate = (mem_req != nullptr); 1982789Sktlim@umich.edu 1998733Sgeoffrey.blake@arm.com // translate to physical address 20013954Sgiacomo.gabrielli@arm.com if (predicate) { 20113954Sgiacomo.gabrielli@arm.com fault = dtb->translateFunctional(mem_req, tc, BaseTLB::Read); 20213954Sgiacomo.gabrielli@arm.com } 2032789Sktlim@umich.edu 20413954Sgiacomo.gabrielli@arm.com if (predicate && !checked_flags && fault == NoFault && unverifiedReq) { 20512749Sgiacomo.travaglini@arm.com flags_match = checkFlags(unverifiedReq, mem_req->getVaddr(), 20612749Sgiacomo.travaglini@arm.com mem_req->getPaddr(), mem_req->getFlags()); 20712749Sgiacomo.travaglini@arm.com pAddr = mem_req->getPaddr(); 2088733Sgeoffrey.blake@arm.com checked_flags = true; 2098733Sgeoffrey.blake@arm.com } 2108733Sgeoffrey.blake@arm.com 2118733Sgeoffrey.blake@arm.com // Now do the access 21213954Sgiacomo.gabrielli@arm.com if (predicate && fault == NoFault && 21312749Sgiacomo.travaglini@arm.com !mem_req->getFlags().isSet(Request::NO_ACCESS)) { 21412749Sgiacomo.travaglini@arm.com PacketPtr pkt = Packet::createRead(mem_req); 2158733Sgeoffrey.blake@arm.com 2168733Sgeoffrey.blake@arm.com pkt->dataStatic(data); 2178733Sgeoffrey.blake@arm.com 21812749Sgiacomo.travaglini@arm.com if (!(mem_req->isUncacheable() || mem_req->isMmappedIpr())) { 2198733Sgeoffrey.blake@arm.com // Access memory to see if we have the same data 2208733Sgeoffrey.blake@arm.com dcachePort->sendFunctional(pkt); 2218733Sgeoffrey.blake@arm.com } else { 2228733Sgeoffrey.blake@arm.com // Assume the data is correct if it's an uncached access 22313954Sgiacomo.gabrielli@arm.com memcpy(data, unverifiedMemData, frag_size); 2248733Sgeoffrey.blake@arm.com } 2258733Sgeoffrey.blake@arm.com 2268733Sgeoffrey.blake@arm.com delete pkt; 2278733Sgeoffrey.blake@arm.com } 2288733Sgeoffrey.blake@arm.com 2298733Sgeoffrey.blake@arm.com if (fault != NoFault) { 23012749Sgiacomo.travaglini@arm.com if (mem_req->isPrefetch()) { 2318733Sgeoffrey.blake@arm.com fault = NoFault; 2328733Sgeoffrey.blake@arm.com } 2338733Sgeoffrey.blake@arm.com break; 2348733Sgeoffrey.blake@arm.com } 2358733Sgeoffrey.blake@arm.com 2368733Sgeoffrey.blake@arm.com //If we don't need to access a second cache line, stop now. 23713954Sgiacomo.gabrielli@arm.com if (size_left == 0) 2388733Sgeoffrey.blake@arm.com { 2398733Sgeoffrey.blake@arm.com break; 2408733Sgeoffrey.blake@arm.com } 2418733Sgeoffrey.blake@arm.com 2428733Sgeoffrey.blake@arm.com // Setup for accessing next cache line 24313954Sgiacomo.gabrielli@arm.com frag_addr += frag_size; 24413954Sgiacomo.gabrielli@arm.com data += frag_size; 24513954Sgiacomo.gabrielli@arm.com unverifiedMemData += frag_size; 2462789Sktlim@umich.edu } 2472789Sktlim@umich.edu 2488733Sgeoffrey.blake@arm.com if (!flags_match) { 2498733Sgeoffrey.blake@arm.com warn("%lli: Flags do not match CPU:%#x %#x %#x Checker:%#x %#x %#x\n", 2508733Sgeoffrey.blake@arm.com curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(), 25113954Sgiacomo.gabrielli@arm.com unverifiedReq->getFlags(), frag_addr, pAddr, flags); 2528733Sgeoffrey.blake@arm.com handleError(); 2538733Sgeoffrey.blake@arm.com } 2542789Sktlim@umich.edu 2558733Sgeoffrey.blake@arm.com return fault; 2562789Sktlim@umich.edu} 2572789Sktlim@umich.edu 2588733Sgeoffrey.blake@arm.comFault 2598733Sgeoffrey.blake@arm.comCheckerCPU::writeMem(uint8_t *data, unsigned size, 26013954Sgiacomo.gabrielli@arm.com Addr addr, Request::Flags flags, uint64_t *res, 26113954Sgiacomo.gabrielli@arm.com const std::vector<bool>& byteEnable) 2628733Sgeoffrey.blake@arm.com{ 26313954Sgiacomo.gabrielli@arm.com assert(byteEnable.empty() || byteEnable.size() == size); 26413954Sgiacomo.gabrielli@arm.com 2658733Sgeoffrey.blake@arm.com Fault fault = NoFault; 2668733Sgeoffrey.blake@arm.com bool checked_flags = false; 2678733Sgeoffrey.blake@arm.com bool flags_match = true; 2688733Sgeoffrey.blake@arm.com Addr pAddr = 0x0; 26910505SAli.Saidi@ARM.com static uint8_t zero_data[64] = {}; 2702789Sktlim@umich.edu 27113954Sgiacomo.gabrielli@arm.com Addr frag_addr = addr; 27213954Sgiacomo.gabrielli@arm.com int frag_size = 0; 27313954Sgiacomo.gabrielli@arm.com int size_left = size; 27413954Sgiacomo.gabrielli@arm.com bool predicate; 2752789Sktlim@umich.edu 2768733Sgeoffrey.blake@arm.com // Need to account for a multiple access like Atomic and Timing CPUs 2778733Sgeoffrey.blake@arm.com while (1) { 27813954Sgiacomo.gabrielli@arm.com RequestPtr mem_req = genMemFragmentRequest(frag_addr, size, flags, 27913954Sgiacomo.gabrielli@arm.com byteEnable, frag_size, 28013954Sgiacomo.gabrielli@arm.com size_left); 2812789Sktlim@umich.edu 28213954Sgiacomo.gabrielli@arm.com predicate = (mem_req != nullptr); 2832789Sktlim@umich.edu 28413954Sgiacomo.gabrielli@arm.com if (predicate) { 28513954Sgiacomo.gabrielli@arm.com fault = dtb->translateFunctional(mem_req, tc, BaseTLB::Write); 28613954Sgiacomo.gabrielli@arm.com } 28713954Sgiacomo.gabrielli@arm.com 28813954Sgiacomo.gabrielli@arm.com if (predicate && !checked_flags && fault == NoFault && unverifiedReq) { 28912749Sgiacomo.travaglini@arm.com flags_match = checkFlags(unverifiedReq, mem_req->getVaddr(), 29012749Sgiacomo.travaglini@arm.com mem_req->getPaddr(), mem_req->getFlags()); 29112749Sgiacomo.travaglini@arm.com pAddr = mem_req->getPaddr(); 2928733Sgeoffrey.blake@arm.com checked_flags = true; 2938733Sgeoffrey.blake@arm.com } 2948733Sgeoffrey.blake@arm.com 2958733Sgeoffrey.blake@arm.com /* 2968733Sgeoffrey.blake@arm.com * We don't actually check memory for the store because there 2978733Sgeoffrey.blake@arm.com * is no guarantee it has left the lsq yet, and therefore we 2988733Sgeoffrey.blake@arm.com * can't verify the memory on stores without lsq snooping 2998733Sgeoffrey.blake@arm.com * enabled. This is left as future work for the Checker: LSQ snooping 3008733Sgeoffrey.blake@arm.com * and memory validation after stores have committed. 3018733Sgeoffrey.blake@arm.com */ 30212749Sgiacomo.travaglini@arm.com bool was_prefetch = mem_req->isPrefetch(); 3038733Sgeoffrey.blake@arm.com 3048733Sgeoffrey.blake@arm.com //If we don't need to access a second cache line, stop now. 30513954Sgiacomo.gabrielli@arm.com if (fault != NoFault || size_left == 0) 3068733Sgeoffrey.blake@arm.com { 3078990SAli.Saidi@ARM.com if (fault != NoFault && was_prefetch) { 3088733Sgeoffrey.blake@arm.com fault = NoFault; 3098733Sgeoffrey.blake@arm.com } 3108733Sgeoffrey.blake@arm.com break; 3118733Sgeoffrey.blake@arm.com } 3128733Sgeoffrey.blake@arm.com 31313954Sgiacomo.gabrielli@arm.com frag_addr += frag_size; 3148733Sgeoffrey.blake@arm.com } 3158733Sgeoffrey.blake@arm.com 3168733Sgeoffrey.blake@arm.com if (!flags_match) { 3178733Sgeoffrey.blake@arm.com warn("%lli: Flags do not match CPU:%#x %#x Checker:%#x %#x %#x\n", 3188733Sgeoffrey.blake@arm.com curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(), 31913954Sgiacomo.gabrielli@arm.com unverifiedReq->getFlags(), frag_addr, pAddr, flags); 3208733Sgeoffrey.blake@arm.com handleError(); 3218733Sgeoffrey.blake@arm.com } 3228733Sgeoffrey.blake@arm.com 3238733Sgeoffrey.blake@arm.com // Assume the result was the same as the one passed in. This checker 3248733Sgeoffrey.blake@arm.com // doesn't check if the SC should succeed or fail, it just checks the 3258733Sgeoffrey.blake@arm.com // value. 3268733Sgeoffrey.blake@arm.com if (unverifiedReq && res && unverifiedReq->extraDataValid()) 3278733Sgeoffrey.blake@arm.com *res = unverifiedReq->getExtraData(); 3288733Sgeoffrey.blake@arm.com 3298733Sgeoffrey.blake@arm.com // Entire purpose here is to make sure we are getting the 3308733Sgeoffrey.blake@arm.com // same data to send to the mem system as the CPU did. 3318733Sgeoffrey.blake@arm.com // Cannot check this is actually what went to memory because 3328733Sgeoffrey.blake@arm.com // there stores can be in ld/st queue or coherent operations 3338733Sgeoffrey.blake@arm.com // overwriting values. 33410416Sandreas.hansson@arm.com bool extraData = false; 3358733Sgeoffrey.blake@arm.com if (unverifiedReq) { 3368733Sgeoffrey.blake@arm.com extraData = unverifiedReq->extraDataValid() ? 33710416Sandreas.hansson@arm.com unverifiedReq->getExtraData() : true; 3388733Sgeoffrey.blake@arm.com } 3398733Sgeoffrey.blake@arm.com 34010505SAli.Saidi@ARM.com // If the request is to ZERO a cache block, there is no data to check 34110505SAli.Saidi@ARM.com // against, but it's all zero. We need something to compare to, so use a 34210505SAli.Saidi@ARM.com // const set of zeros. 34312355Snikos.nikoleris@arm.com if (flags & Request::STORE_NO_DATA) { 34410505SAli.Saidi@ARM.com assert(!data); 34513954Sgiacomo.gabrielli@arm.com assert(sizeof(zero_data) <= size); 34610505SAli.Saidi@ARM.com data = zero_data; 34710505SAli.Saidi@ARM.com } 34810505SAli.Saidi@ARM.com 3498733Sgeoffrey.blake@arm.com if (unverifiedReq && unverifiedMemData && 35013954Sgiacomo.gabrielli@arm.com memcmp(data, unverifiedMemData, size) && extraData) { 35110367SAndrew.Bardsley@arm.com warn("%lli: Store value does not match value sent to memory! " 35210367SAndrew.Bardsley@arm.com "data: %#x inst_data: %#x", curTick(), data, 3538733Sgeoffrey.blake@arm.com unverifiedMemData); 3548733Sgeoffrey.blake@arm.com handleError(); 3558733Sgeoffrey.blake@arm.com } 3568733Sgeoffrey.blake@arm.com 3578733Sgeoffrey.blake@arm.com return fault; 3582789Sktlim@umich.edu} 3592789Sktlim@umich.edu 3602789Sktlim@umich.eduAddr 3612789Sktlim@umich.eduCheckerCPU::dbg_vtophys(Addr addr) 3622789Sktlim@umich.edu{ 3632789Sktlim@umich.edu return vtophys(tc, addr); 3642789Sktlim@umich.edu} 3652789Sktlim@umich.edu 3668733Sgeoffrey.blake@arm.com/** 3678733Sgeoffrey.blake@arm.com * Checks if the flags set by the Checker and Checkee match. 3688733Sgeoffrey.blake@arm.com */ 3692789Sktlim@umich.edubool 37012749Sgiacomo.travaglini@arm.comCheckerCPU::checkFlags(const RequestPtr &unverified_req, Addr vAddr, 3718733Sgeoffrey.blake@arm.com Addr pAddr, int flags) 3722789Sktlim@umich.edu{ 3738733Sgeoffrey.blake@arm.com Addr unverifiedVAddr = unverified_req->getVaddr(); 3748733Sgeoffrey.blake@arm.com Addr unverifiedPAddr = unverified_req->getPaddr(); 3758733Sgeoffrey.blake@arm.com int unverifiedFlags = unverified_req->getFlags(); 3768733Sgeoffrey.blake@arm.com 3778733Sgeoffrey.blake@arm.com if (unverifiedVAddr != vAddr || 3788733Sgeoffrey.blake@arm.com unverifiedPAddr != pAddr || 3798733Sgeoffrey.blake@arm.com unverifiedFlags != flags) { 3802789Sktlim@umich.edu return false; 3812789Sktlim@umich.edu } 3828733Sgeoffrey.blake@arm.com 3838733Sgeoffrey.blake@arm.com return true; 3842789Sktlim@umich.edu} 3852789Sktlim@umich.edu 3862789Sktlim@umich.eduvoid 3872789Sktlim@umich.eduCheckerCPU::dumpAndExit() 3882789Sktlim@umich.edu{ 3898733Sgeoffrey.blake@arm.com warn("%lli: Checker PC:%s", 3908733Sgeoffrey.blake@arm.com curTick(), thread->pcState()); 3912789Sktlim@umich.edu panic("Checker found an error!"); 3922789Sktlim@umich.edu} 393