cpu.cc revision 13453
12SN/A/* 21458SN/A * Copyright (c) 2011,2013,2017 ARM Limited 32SN/A * All rights reserved 42SN/A * 52SN/A * The license below extends only to copyright in the software and shall 62SN/A * not be construed as granting a license to any other intellectual 72SN/A * property including but not limited to intellectual property relating 82SN/A * to a hardware implementation of the functionality of the software 92SN/A * licensed hereunder. You may use the software subject to the license 102SN/A * terms below provided that you ensure that this notice is replicated 112SN/A * unmodified and in its entirety in all distributions of the software, 122SN/A * modified or unmodified, in source code or in binary form. 132SN/A * 142SN/A * Copyright (c) 2006 The Regents of The University of Michigan 152SN/A * All rights reserved. 162SN/A * 172SN/A * Redistribution and use in source and binary forms, with or without 182SN/A * modification, are permitted provided that the following conditions are 192SN/A * met: redistributions of source code must retain the above copyright 202SN/A * notice, this list of conditions and the following disclaimer; 212SN/A * redistributions in binary form must reproduce the above copyright 222SN/A * notice, this list of conditions and the following disclaimer in the 232SN/A * documentation and/or other materials provided with the distribution; 242SN/A * neither the name of the copyright holders nor the names of its 252SN/A * contributors may be used to endorse or promote products derived from 262SN/A * this software without specific prior written permission. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292665Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321147SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331147SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352037SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362037SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372428SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386216Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 391858SN/A * 402SN/A * Authors: Kevin Lim 412107SN/A * Geoffrey Blake 422SN/A */ 435569Snate@binkert.org 442238SN/A#include "cpu/checker/cpu.hh" 455569Snate@binkert.org 462107SN/A#include <list> 475569Snate@binkert.org#include <string> 485569Snate@binkert.org 495569Snate@binkert.org#include "arch/generic/tlb.hh" 505569Snate@binkert.org#include "arch/kernel_stats.hh" 515569Snate@binkert.org#include "arch/vtophys.hh" 525569Snate@binkert.org#include "cpu/base.hh" 535569Snate@binkert.org#include "cpu/simple_thread.hh" 545569Snate@binkert.org#include "cpu/static_inst.hh" 555569Snate@binkert.org#include "cpu/thread_context.hh" 565569Snate@binkert.org#include "params/CheckerCPU.hh" 575569Snate@binkert.org#include "sim/full_system.hh" 585569Snate@binkert.org 595569Snate@binkert.orgusing namespace std; 605569Snate@binkert.orgusing namespace TheISA; 615569Snate@binkert.org 625569Snate@binkert.orgvoid 635569Snate@binkert.orgCheckerCPU::init() 645569Snate@binkert.org{ 655569Snate@binkert.org masterId = systemPtr->getMasterId(this); 665569Snate@binkert.org} 675569Snate@binkert.org 685569Snate@binkert.orgCheckerCPU::CheckerCPU(Params *p) 695569Snate@binkert.org : BaseCPU(p, true), systemPtr(NULL), icachePort(NULL), dcachePort(NULL), 705569Snate@binkert.org tc(NULL), thread(NULL), 715569Snate@binkert.org unverifiedReq(nullptr), 725569Snate@binkert.org unverifiedMemData(nullptr) 735569Snate@binkert.org{ 745569Snate@binkert.org curStaticInst = NULL; 755569Snate@binkert.org curMacroStaticInst = NULL; 765569Snate@binkert.org 775569Snate@binkert.org numInst = 0; 785569Snate@binkert.org startNumInst = 0; 795569Snate@binkert.org numLoad = 0; 805569Snate@binkert.org startNumLoad = 0; 815569Snate@binkert.org youngestSN = 0; 825569Snate@binkert.org 835569Snate@binkert.org changedPC = willChangePC = false; 845569Snate@binkert.org 855569Snate@binkert.org exitOnError = p->exitOnError; 865569Snate@binkert.org warnOnlyOnLoadError = p->warnOnlyOnLoadError; 875569Snate@binkert.org itb = p->itb; 885569Snate@binkert.org dtb = p->dtb; 895569Snate@binkert.org workload = p->workload; 905569Snate@binkert.org 915569Snate@binkert.org updateOnError = true; 925569Snate@binkert.org} 935569Snate@binkert.org 945569Snate@binkert.orgCheckerCPU::~CheckerCPU() 955569Snate@binkert.org{ 965569Snate@binkert.org} 975569Snate@binkert.org 985569Snate@binkert.orgvoid 995569Snate@binkert.orgCheckerCPU::setSystem(System *system) 1005569Snate@binkert.org{ 1015569Snate@binkert.org const Params *p(dynamic_cast<const Params *>(_params)); 1025569Snate@binkert.org 1035569Snate@binkert.org systemPtr = system; 1045569Snate@binkert.org 1055569Snate@binkert.org if (FullSystem) { 1065569Snate@binkert.org thread = new SimpleThread(this, 0, systemPtr, itb, dtb, 1075569Snate@binkert.org p->isa[0], false); 1085569Snate@binkert.org } else { 1095569Snate@binkert.org thread = new SimpleThread(this, 0, systemPtr, 1105569Snate@binkert.org workload.size() ? workload[0] : NULL, 1115569Snate@binkert.org itb, dtb, p->isa[0]); 1125569Snate@binkert.org } 1135569Snate@binkert.org 1145569Snate@binkert.org tc = thread->getTC(); 1155569Snate@binkert.org threadContexts.push_back(tc); 1165569Snate@binkert.org thread->kernelStats = NULL; 1175569Snate@binkert.org // Thread should never be null after this 1186227Snate@binkert.org assert(thread != NULL); 1196227Snate@binkert.org} 1206227Snate@binkert.org 1215569Snate@binkert.orgvoid 1226227Snate@binkert.orgCheckerCPU::setIcachePort(MasterPort *icache_port) 1235569Snate@binkert.org{ 1246227Snate@binkert.org icachePort = icache_port; 1256227Snate@binkert.org} 1266227Snate@binkert.org 1276227Snate@binkert.orgvoid 1286227Snate@binkert.orgCheckerCPU::setDcachePort(MasterPort *dcache_port) 1295569Snate@binkert.org{ 1305569Snate@binkert.org dcachePort = dcache_port; 1315569Snate@binkert.org} 1325569Snate@binkert.org 1335569Snate@binkert.orgvoid 1346974Stjones1@inf.ed.ac.ukCheckerCPU::serialize(ostream &os) const 1356974Stjones1@inf.ed.ac.uk{ 1366974Stjones1@inf.ed.ac.uk} 1375569Snate@binkert.org 1385569Snate@binkert.orgvoid 1391147SN/ACheckerCPU::unserialize(CheckpointIn &cp) 140{ 141} 142 143Fault 144CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size, 145 Request::Flags flags) 146{ 147 Fault fault = NoFault; 148 int fullSize = size; 149 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 150 bool checked_flags = false; 151 bool flags_match = true; 152 Addr pAddr = 0x0; 153 154 155 if (secondAddr > addr) 156 size = secondAddr - addr; 157 158 // Need to account for multiple accesses like the Atomic and TimingSimple 159 while (1) { 160 auto mem_req = std::make_shared<Request>( 161 0, addr, size, flags, masterId, 162 thread->pcState().instAddr(), tc->contextId()); 163 164 // translate to physical address 165 fault = dtb->translateFunctional(mem_req, tc, BaseTLB::Read); 166 167 if (!checked_flags && fault == NoFault && unverifiedReq) { 168 flags_match = checkFlags(unverifiedReq, mem_req->getVaddr(), 169 mem_req->getPaddr(), mem_req->getFlags()); 170 pAddr = mem_req->getPaddr(); 171 checked_flags = true; 172 } 173 174 // Now do the access 175 if (fault == NoFault && 176 !mem_req->getFlags().isSet(Request::NO_ACCESS)) { 177 PacketPtr pkt = Packet::createRead(mem_req); 178 179 pkt->dataStatic(data); 180 181 if (!(mem_req->isUncacheable() || mem_req->isMmappedIpr())) { 182 // Access memory to see if we have the same data 183 dcachePort->sendFunctional(pkt); 184 } else { 185 // Assume the data is correct if it's an uncached access 186 memcpy(data, unverifiedMemData, size); 187 } 188 189 delete pkt; 190 } 191 192 if (fault != NoFault) { 193 if (mem_req->isPrefetch()) { 194 fault = NoFault; 195 } 196 break; 197 } 198 199 //If we don't need to access a second cache line, stop now. 200 if (secondAddr <= addr) 201 { 202 break; 203 } 204 205 // Setup for accessing next cache line 206 data += size; 207 unverifiedMemData += size; 208 size = addr + fullSize - secondAddr; 209 addr = secondAddr; 210 } 211 212 if (!flags_match) { 213 warn("%lli: Flags do not match CPU:%#x %#x %#x Checker:%#x %#x %#x\n", 214 curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(), 215 unverifiedReq->getFlags(), addr, pAddr, flags); 216 handleError(); 217 } 218 219 return fault; 220} 221 222Fault 223CheckerCPU::writeMem(uint8_t *data, unsigned size, 224 Addr addr, Request::Flags flags, uint64_t *res) 225{ 226 Fault fault = NoFault; 227 bool checked_flags = false; 228 bool flags_match = true; 229 Addr pAddr = 0x0; 230 static uint8_t zero_data[64] = {}; 231 232 int fullSize = size; 233 234 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 235 236 if (secondAddr > addr) 237 size = secondAddr - addr; 238 239 // Need to account for a multiple access like Atomic and Timing CPUs 240 while (1) { 241 auto mem_req = std::make_shared<Request>( 242 0, addr, size, flags, masterId, 243 thread->pcState().instAddr(), tc->contextId()); 244 245 // translate to physical address 246 fault = dtb->translateFunctional(mem_req, tc, BaseTLB::Write); 247 248 if (!checked_flags && fault == NoFault && unverifiedReq) { 249 flags_match = checkFlags(unverifiedReq, mem_req->getVaddr(), 250 mem_req->getPaddr(), mem_req->getFlags()); 251 pAddr = mem_req->getPaddr(); 252 checked_flags = true; 253 } 254 255 /* 256 * We don't actually check memory for the store because there 257 * is no guarantee it has left the lsq yet, and therefore we 258 * can't verify the memory on stores without lsq snooping 259 * enabled. This is left as future work for the Checker: LSQ snooping 260 * and memory validation after stores have committed. 261 */ 262 bool was_prefetch = mem_req->isPrefetch(); 263 264 //If we don't need to access a second cache line, stop now. 265 if (fault != NoFault || secondAddr <= addr) 266 { 267 if (fault != NoFault && was_prefetch) { 268 fault = NoFault; 269 } 270 break; 271 } 272 273 //Update size and access address 274 size = addr + fullSize - secondAddr; 275 //And access the right address. 276 addr = secondAddr; 277 } 278 279 if (!flags_match) { 280 warn("%lli: Flags do not match CPU:%#x %#x Checker:%#x %#x %#x\n", 281 curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(), 282 unverifiedReq->getFlags(), addr, pAddr, flags); 283 handleError(); 284 } 285 286 // Assume the result was the same as the one passed in. This checker 287 // doesn't check if the SC should succeed or fail, it just checks the 288 // value. 289 if (unverifiedReq && res && unverifiedReq->extraDataValid()) 290 *res = unverifiedReq->getExtraData(); 291 292 // Entire purpose here is to make sure we are getting the 293 // same data to send to the mem system as the CPU did. 294 // Cannot check this is actually what went to memory because 295 // there stores can be in ld/st queue or coherent operations 296 // overwriting values. 297 bool extraData = false; 298 if (unverifiedReq) { 299 extraData = unverifiedReq->extraDataValid() ? 300 unverifiedReq->getExtraData() : true; 301 } 302 303 // If the request is to ZERO a cache block, there is no data to check 304 // against, but it's all zero. We need something to compare to, so use a 305 // const set of zeros. 306 if (flags & Request::STORE_NO_DATA) { 307 assert(!data); 308 assert(sizeof(zero_data) <= fullSize); 309 data = zero_data; 310 } 311 312 if (unverifiedReq && unverifiedMemData && 313 memcmp(data, unverifiedMemData, fullSize) && extraData) { 314 warn("%lli: Store value does not match value sent to memory! " 315 "data: %#x inst_data: %#x", curTick(), data, 316 unverifiedMemData); 317 handleError(); 318 } 319 320 return fault; 321} 322 323Addr 324CheckerCPU::dbg_vtophys(Addr addr) 325{ 326 return vtophys(tc, addr); 327} 328 329/** 330 * Checks if the flags set by the Checker and Checkee match. 331 */ 332bool 333CheckerCPU::checkFlags(const RequestPtr &unverified_req, Addr vAddr, 334 Addr pAddr, int flags) 335{ 336 Addr unverifiedVAddr = unverified_req->getVaddr(); 337 Addr unverifiedPAddr = unverified_req->getPaddr(); 338 int unverifiedFlags = unverified_req->getFlags(); 339 340 if (unverifiedVAddr != vAddr || 341 unverifiedPAddr != pAddr || 342 unverifiedFlags != flags) { 343 return false; 344 } 345 346 return true; 347} 348 349void 350CheckerCPU::dumpAndExit() 351{ 352 warn("%lli: Checker PC:%s", 353 curTick(), thread->pcState()); 354 panic("Checker found an error!"); 355} 356