base_dyn_inst_impl.hh revision 5375
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#include <iostream> 32#include <set> 33#include <string> 34#include <sstream> 35 36#include "base/cprintf.hh" 37#include "base/trace.hh" 38 39#include "sim/faults.hh" 40#include "cpu/exetrace.hh" 41#include "mem/request.hh" 42 43#include "cpu/base_dyn_inst.hh" 44 45#define NOHASH 46#ifndef NOHASH 47 48#include "base/hashmap.hh" 49 50unsigned int MyHashFunc(const BaseDynInst *addr) 51{ 52 unsigned a = (unsigned)addr; 53 unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF; 54 55 return hash; 56} 57 58typedef m5::hash_map<const BaseDynInst *, const BaseDynInst *, MyHashFunc> 59my_hash_t; 60 61my_hash_t thishash; 62#endif 63 64template <class Impl> 65BaseDynInst<Impl>::BaseDynInst(StaticInstPtr _staticInst, 66 Addr inst_PC, Addr inst_NPC, 67 Addr inst_MicroPC, 68 Addr pred_PC, Addr pred_NPC, 69 Addr pred_MicroPC, 70 InstSeqNum seq_num, ImplCPU *cpu) 71 : staticInst(_staticInst), traceData(NULL), cpu(cpu) 72{ 73 seqNum = seq_num; 74 75 bool nextIsMicro = 76 staticInst->isMicroop() && !staticInst->isLastMicroop(); 77 78 PC = inst_PC; 79 microPC = inst_MicroPC; 80 if (nextIsMicro) { 81 nextPC = inst_PC; 82 nextNPC = inst_NPC; 83 nextMicroPC = microPC + 1; 84 } else { 85 nextPC = inst_NPC; 86 nextNPC = nextPC + sizeof(TheISA::MachInst); 87 nextMicroPC = 0; 88 } 89 predPC = pred_PC; 90 predNPC = pred_NPC; 91 predMicroPC = pred_MicroPC; 92 predTaken = false; 93 94 initVars(); 95} 96 97template <class Impl> 98BaseDynInst<Impl>::BaseDynInst(TheISA::ExtMachInst inst, 99 Addr inst_PC, Addr inst_NPC, 100 Addr inst_MicroPC, 101 Addr pred_PC, Addr pred_NPC, 102 Addr pred_MicroPC, 103 InstSeqNum seq_num, ImplCPU *cpu) 104 : staticInst(inst, inst_PC), traceData(NULL), cpu(cpu) 105{ 106 seqNum = seq_num; 107 108 bool nextIsMicro = 109 staticInst->isMicroop() && !staticInst->isLastMicroop(); 110 111 PC = inst_PC; 112 microPC = inst_MicroPC; 113 if (nextIsMicro) { 114 nextPC = inst_PC; 115 nextNPC = inst_NPC; 116 nextMicroPC = microPC + 1; 117 } else { 118 nextPC = inst_NPC; 119 nextNPC = nextPC + sizeof(TheISA::MachInst); 120 nextMicroPC = 0; 121 } 122 predPC = pred_PC; 123 predNPC = pred_NPC; 124 predMicroPC = pred_MicroPC; 125 predTaken = false; 126 127 initVars(); 128} 129 130template <class Impl> 131BaseDynInst<Impl>::BaseDynInst(StaticInstPtr &_staticInst) 132 : staticInst(_staticInst), traceData(NULL) 133{ 134 seqNum = 0; 135 initVars(); 136} 137 138template <class Impl> 139void 140BaseDynInst<Impl>::initVars() 141{ 142 memData = NULL; 143 effAddr = 0; 144 effAddrValid = false; 145 physEffAddr = 0; 146 147 isUncacheable = false; 148 reqMade = false; 149 readyRegs = 0; 150 151 instResult.integer = 0; 152 recordResult = true; 153 154 status.reset(); 155 156 eaCalcDone = false; 157 memOpDone = false; 158 159 lqIdx = -1; 160 sqIdx = -1; 161 162 // Eventually make this a parameter. 163 threadNumber = 0; 164 165 // Also make this a parameter, or perhaps get it from xc or cpu. 166 asid = 0; 167 168 // Initialize the fault to be NoFault. 169 fault = NoFault; 170 171 ++instcount; 172 173 if (instcount > 1500) { 174#ifdef DEBUG 175 cpu->dumpInsts(); 176 dumpSNList(); 177#endif 178 assert(instcount <= 1500); 179 } 180 181 DPRINTF(DynInst, "DynInst: [sn:%lli] Instruction created. Instcount=%i\n", 182 seqNum, instcount); 183 184#ifdef DEBUG 185 cpu->snList.insert(seqNum); 186#endif 187} 188 189template <class Impl> 190BaseDynInst<Impl>::~BaseDynInst() 191{ 192 if (memData) { 193 delete [] memData; 194 } 195 196 if (traceData) { 197 delete traceData; 198 } 199 200 fault = NoFault; 201 202 --instcount; 203 204 DPRINTF(DynInst, "DynInst: [sn:%lli] Instruction destroyed. Instcount=%i\n", 205 seqNum, instcount); 206#ifdef DEBUG 207 cpu->snList.erase(seqNum); 208#endif 209} 210 211#ifdef DEBUG 212template <class Impl> 213void 214BaseDynInst<Impl>::dumpSNList() 215{ 216 std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin(); 217 218 int count = 0; 219 while (sn_it != cpu->snList.end()) { 220 cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it)); 221 count++; 222 sn_it++; 223 } 224} 225#endif 226 227template <class Impl> 228void 229BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags) 230{ 231 // This is the "functional" implementation of prefetch. Not much 232 // happens here since prefetches don't affect the architectural 233 // state. 234/* 235 // Generate a MemReq so we can translate the effective address. 236 MemReqPtr req = new MemReq(addr, thread->getXCProxy(), 1, flags); 237 req->asid = asid; 238 239 // Prefetches never cause faults. 240 fault = NoFault; 241 242 // note this is a local, not BaseDynInst::fault 243 Fault trans_fault = cpu->translateDataReadReq(req); 244 245 if (trans_fault == NoFault && !(req->isUncacheable())) { 246 // It's a valid address to cacheable space. Record key MemReq 247 // parameters so we can generate another one just like it for 248 // the timing access without calling translate() again (which 249 // might mess up the TLB). 250 effAddr = req->vaddr; 251 physEffAddr = req->paddr; 252 memReqFlags = req->flags; 253 } else { 254 // Bogus address (invalid or uncacheable space). Mark it by 255 // setting the eff_addr to InvalidAddr. 256 effAddr = physEffAddr = MemReq::inval_addr; 257 } 258 259 if (traceData) { 260 traceData->setAddr(addr); 261 } 262*/ 263} 264 265template <class Impl> 266void 267BaseDynInst<Impl>::writeHint(Addr addr, int size, unsigned flags) 268{ 269 // Not currently supported. 270} 271 272/** 273 * @todo Need to find a way to get the cache block size here. 274 */ 275template <class Impl> 276Fault 277BaseDynInst<Impl>::copySrcTranslate(Addr src) 278{ 279 // Not currently supported. 280 return NoFault; 281} 282 283/** 284 * @todo Need to find a way to get the cache block size here. 285 */ 286template <class Impl> 287Fault 288BaseDynInst<Impl>::copy(Addr dest) 289{ 290 // Not currently supported. 291 return NoFault; 292} 293 294template <class Impl> 295void 296BaseDynInst<Impl>::dump() 297{ 298 cprintf("T%d : %#08d `", threadNumber, PC); 299 std::cout << staticInst->disassemble(PC); 300 cprintf("'\n"); 301} 302 303template <class Impl> 304void 305BaseDynInst<Impl>::dump(std::string &outstring) 306{ 307 std::ostringstream s; 308 s << "T" << threadNumber << " : 0x" << PC << " " 309 << staticInst->disassemble(PC); 310 311 outstring = s.str(); 312} 313 314template <class Impl> 315void 316BaseDynInst<Impl>::markSrcRegReady() 317{ 318 if (++readyRegs == numSrcRegs()) { 319 setCanIssue(); 320 } 321} 322 323template <class Impl> 324void 325BaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx) 326{ 327 _readySrcRegIdx[src_idx] = true; 328 329 markSrcRegReady(); 330} 331 332template <class Impl> 333bool 334BaseDynInst<Impl>::eaSrcsReady() 335{ 336 // For now I am assuming that src registers 1..n-1 are the ones that the 337 // EA calc depends on. (i.e. src reg 0 is the source of the data to be 338 // stored) 339 340 for (int i = 1; i < numSrcRegs(); ++i) { 341 if (!_readySrcRegIdx[i]) 342 return false; 343 } 344 345 return true; 346} 347