base_dyn_inst_impl.hh revision 2733 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include <iostream>
32#include <set>
33#include <string>
34#include <sstream>
35
36#include "base/cprintf.hh"
37#include "base/trace.hh"
38
39#include "arch/faults.hh"
40#include "cpu/exetrace.hh"
41#include "mem/request.hh"
42
43#include "cpu/base_dyn_inst.hh"
44#include "cpu/o3/alpha_impl.hh"
45#include "cpu/o3/alpha_cpu.hh"
46//#include "cpu/ozone/simple_impl.hh"
47//#include "cpu/ozone/ozone_impl.hh"
48
49using namespace std;
50using namespace TheISA;
51
52#define NOHASH
53#ifndef NOHASH
54
55#include "base/hashmap.hh"
56
57unsigned int MyHashFunc(const BaseDynInst *addr)
58{
59    unsigned a = (unsigned)addr;
60    unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
61
62    return hash;
63}
64
65typedef m5::hash_map<const BaseDynInst *, const BaseDynInst *, MyHashFunc>
66my_hash_t;
67
68my_hash_t thishash;
69#endif
70
71template <class Impl>
72BaseDynInst<Impl>::BaseDynInst(ExtMachInst machInst, Addr inst_PC,
73                               Addr pred_PC, InstSeqNum seq_num,
74                               ImplCPU *cpu)
75  : staticInst(machInst), traceData(NULL), cpu(cpu)
76{
77    seqNum = seq_num;
78
79    PC = inst_PC;
80    nextPC = PC + sizeof(MachInst);
81    predPC = pred_PC;
82
83    initVars();
84}
85
86template <class Impl>
87BaseDynInst<Impl>::BaseDynInst(StaticInstPtr &_staticInst)
88    : staticInst(_staticInst), traceData(NULL)
89{
90    seqNum = 0;
91    initVars();
92}
93
94template <class Impl>
95void
96BaseDynInst<Impl>::initVars()
97{
98    req = NULL;
99    memData = NULL;
100    effAddr = 0;
101    physEffAddr = 0;
102
103    readyRegs = 0;
104
105    instResult.integer = 0;
106
107    status.reset();
108
109    eaCalcDone = false;
110    memOpDone = false;
111
112    lqIdx = -1;
113    sqIdx = -1;
114
115    // Eventually make this a parameter.
116    threadNumber = 0;
117
118    // Also make this a parameter, or perhaps get it from xc or cpu.
119    asid = 0;
120
121    // Initialize the fault to be NoFault.
122    fault = NoFault;
123
124    ++instcount;
125
126    if (instcount > 1500) {
127        cpu->dumpInsts();
128#ifdef DEBUG
129        dumpSNList();
130#endif
131        assert(instcount <= 1500);
132    }
133
134    DPRINTF(DynInst, "DynInst: [sn:%lli] Instruction created. Instcount=%i\n",
135            seqNum, instcount);
136
137#ifdef DEBUG
138    cpu->snList.insert(seqNum);
139#endif
140}
141
142template <class Impl>
143BaseDynInst<Impl>::~BaseDynInst()
144{
145    if (req) {
146        delete req;
147    }
148
149    if (memData) {
150        delete [] memData;
151    }
152
153    if (traceData) {
154        delete traceData;
155    }
156
157    fault = NoFault;
158
159    --instcount;
160
161    DPRINTF(DynInst, "DynInst: [sn:%lli] Instruction destroyed. Instcount=%i\n",
162            seqNum, instcount);
163#ifdef DEBUG
164    cpu->snList.erase(seqNum);
165#endif
166}
167
168#ifdef DEBUG
169template <class Impl>
170void
171BaseDynInst<Impl>::dumpSNList()
172{
173    std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
174
175    int count = 0;
176    while (sn_it != cpu->snList.end()) {
177        cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
178        count++;
179        sn_it++;
180    }
181}
182#endif
183
184template <class Impl>
185void
186BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
187{
188    // This is the "functional" implementation of prefetch.  Not much
189    // happens here since prefetches don't affect the architectural
190    // state.
191/*
192    // Generate a MemReq so we can translate the effective address.
193    MemReqPtr req = new MemReq(addr, thread->getXCProxy(), 1, flags);
194    req->asid = asid;
195
196    // Prefetches never cause faults.
197    fault = NoFault;
198
199    // note this is a local, not BaseDynInst::fault
200    Fault trans_fault = cpu->translateDataReadReq(req);
201
202    if (trans_fault == NoFault && !(req->flags & UNCACHEABLE)) {
203        // It's a valid address to cacheable space.  Record key MemReq
204        // parameters so we can generate another one just like it for
205        // the timing access without calling translate() again (which
206        // might mess up the TLB).
207        effAddr = req->vaddr;
208        physEffAddr = req->paddr;
209        memReqFlags = req->flags;
210    } else {
211        // Bogus address (invalid or uncacheable space).  Mark it by
212        // setting the eff_addr to InvalidAddr.
213        effAddr = physEffAddr = MemReq::inval_addr;
214    }
215
216    if (traceData) {
217        traceData->setAddr(addr);
218    }
219*/
220}
221
222template <class Impl>
223void
224BaseDynInst<Impl>::writeHint(Addr addr, int size, unsigned flags)
225{
226    // Not currently supported.
227}
228
229/**
230 * @todo Need to find a way to get the cache block size here.
231 */
232template <class Impl>
233Fault
234BaseDynInst<Impl>::copySrcTranslate(Addr src)
235{
236    // Not currently supported.
237    return NoFault;
238}
239
240/**
241 * @todo Need to find a way to get the cache block size here.
242 */
243template <class Impl>
244Fault
245BaseDynInst<Impl>::copy(Addr dest)
246{
247    // Not currently supported.
248    return NoFault;
249}
250
251template <class Impl>
252void
253BaseDynInst<Impl>::dump()
254{
255    cprintf("T%d : %#08d `", threadNumber, PC);
256    cout << staticInst->disassemble(PC);
257    cprintf("'\n");
258}
259
260template <class Impl>
261void
262BaseDynInst<Impl>::dump(std::string &outstring)
263{
264    std::ostringstream s;
265    s << "T" << threadNumber << " : 0x" << PC << " "
266      << staticInst->disassemble(PC);
267
268    outstring = s.str();
269}
270
271template <class Impl>
272void
273BaseDynInst<Impl>::markSrcRegReady()
274{
275    if (++readyRegs == numSrcRegs()) {
276        status.set(CanIssue);
277    }
278}
279
280template <class Impl>
281void
282BaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx)
283{
284    _readySrcRegIdx[src_idx] = true;
285
286    markSrcRegReady();
287}
288
289template <class Impl>
290bool
291BaseDynInst<Impl>::eaSrcsReady()
292{
293    // For now I am assuming that src registers 1..n-1 are the ones that the
294    // EA calc depends on.  (i.e. src reg 0 is the source of the data to be
295    // stored)
296
297    for (int i = 1; i < numSrcRegs(); ++i) {
298        if (!_readySrcRegIdx[i])
299            return false;
300    }
301
302    return true;
303}
304
305// Forward declaration
306template class BaseDynInst<AlphaSimpleImpl>;
307
308template <>
309int
310BaseDynInst<AlphaSimpleImpl>::instcount = 0;
311/*
312// Forward declaration
313template class BaseDynInst<SimpleImpl>;
314
315template <>
316int
317BaseDynInst<SimpleImpl>::instcount = 0;
318
319// Forward declaration
320template class BaseDynInst<OzoneImpl>;
321
322template <>
323int
324BaseDynInst<OzoneImpl>::instcount = 0;
325*/
326