base_dyn_inst.hh revision 8545
1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * Copyright (c) 2009 The University of Edinburgh 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 * Timothy M. Jones 43 */ 44 45#ifndef __CPU_BASE_DYN_INST_HH__ 46#define __CPU_BASE_DYN_INST_HH__ 47 48#include <bitset> 49#include <list> 50#include <string> 51 52#include "arch/faults.hh" 53#include "arch/utility.hh" 54#include "base/fast_alloc.hh" 55#include "base/trace.hh" 56#include "config/full_system.hh" 57#include "config/the_isa.hh" 58#include "cpu/o3/comm.hh" 59#include "cpu/exetrace.hh" 60#include "cpu/inst_seq.hh" 61#include "cpu/op_class.hh" 62#include "cpu/static_inst.hh" 63#include "cpu/translation.hh" 64#include "mem/packet.hh" 65#include "sim/byteswap.hh" 66#include "sim/system.hh" 67#include "sim/tlb.hh" 68 69/** 70 * @file 71 * Defines a dynamic instruction context. 72 */ 73 74template <class Impl> 75class BaseDynInst : public FastAlloc, public RefCounted 76{ 77 public: 78 // Typedef for the CPU. 79 typedef typename Impl::CPUType ImplCPU; 80 typedef typename ImplCPU::ImplState ImplState; 81 82 // Logical register index type. 83 typedef TheISA::RegIndex RegIndex; 84 // Integer register type. 85 typedef TheISA::IntReg IntReg; 86 // Floating point register type. 87 typedef TheISA::FloatReg FloatReg; 88 89 // The DynInstPtr type. 90 typedef typename Impl::DynInstPtr DynInstPtr; 91 typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr; 92 93 // The list of instructions iterator type. 94 typedef typename std::list<DynInstPtr>::iterator ListIt; 95 96 enum { 97 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 98 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs 99 }; 100 101 /** The StaticInst used by this BaseDynInst. */ 102 StaticInstPtr staticInst; 103 StaticInstPtr macroop; 104 105 //////////////////////////////////////////// 106 // 107 // INSTRUCTION EXECUTION 108 // 109 //////////////////////////////////////////// 110 /** InstRecord that tracks this instructions. */ 111 Trace::InstRecord *traceData; 112 113 void demapPage(Addr vaddr, uint64_t asn) 114 { 115 cpu->demapPage(vaddr, asn); 116 } 117 void demapInstPage(Addr vaddr, uint64_t asn) 118 { 119 cpu->demapPage(vaddr, asn); 120 } 121 void demapDataPage(Addr vaddr, uint64_t asn) 122 { 123 cpu->demapPage(vaddr, asn); 124 } 125 126 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 127 128 Fault writeMem(uint8_t *data, unsigned size, 129 Addr addr, unsigned flags, uint64_t *res); 130 131 /** Splits a request in two if it crosses a dcache block. */ 132 void splitRequest(RequestPtr req, RequestPtr &sreqLow, 133 RequestPtr &sreqHigh); 134 135 /** Initiate a DTB address translation. */ 136 void initiateTranslation(RequestPtr req, RequestPtr sreqLow, 137 RequestPtr sreqHigh, uint64_t *res, 138 BaseTLB::Mode mode); 139 140 /** Finish a DTB address translation. */ 141 void finishTranslation(WholeTranslationState *state); 142 143 /** True if the DTB address translation has started. */ 144 bool translationStarted; 145 146 /** True if the DTB address translation has completed. */ 147 bool translationCompleted; 148 149 /** True if this address was found to match a previous load and they issued 150 * out of order. If that happend, then it's only a problem if an incoming 151 * snoop invalidate modifies the line, in which case we need to squash. 152 * If nothing modified the line the order doesn't matter. 153 */ 154 bool possibleLoadViolation; 155 156 /** True if the address hit a external snoop while sitting in the LSQ. 157 * If this is true and a older instruction sees it, this instruction must 158 * reexecute 159 */ 160 bool hitExternalSnoop; 161 162 /** 163 * Returns true if the DTB address translation is being delayed due to a hw 164 * page table walk. 165 */ 166 bool isTranslationDelayed() const 167 { 168 return (translationStarted && !translationCompleted); 169 } 170 171 /** 172 * Saved memory requests (needed when the DTB address translation is 173 * delayed due to a hw page table walk). 174 */ 175 RequestPtr savedReq; 176 RequestPtr savedSreqLow; 177 RequestPtr savedSreqHigh; 178 179 /** @todo: Consider making this private. */ 180 public: 181 /** The sequence number of the instruction. */ 182 InstSeqNum seqNum; 183 184 enum Status { 185 IqEntry, /// Instruction is in the IQ 186 RobEntry, /// Instruction is in the ROB 187 LsqEntry, /// Instruction is in the LSQ 188 Completed, /// Instruction has completed 189 ResultReady, /// Instruction has its result 190 CanIssue, /// Instruction can issue and execute 191 Issued, /// Instruction has issued 192 Executed, /// Instruction has executed 193 CanCommit, /// Instruction can commit 194 AtCommit, /// Instruction has reached commit 195 Committed, /// Instruction has committed 196 Squashed, /// Instruction is squashed 197 SquashedInIQ, /// Instruction is squashed in the IQ 198 SquashedInLSQ, /// Instruction is squashed in the LSQ 199 SquashedInROB, /// Instruction is squashed in the ROB 200 RecoverInst, /// Is a recover instruction 201 BlockingInst, /// Is a blocking instruction 202 ThreadsyncWait, /// Is a thread synchronization instruction 203 SerializeBefore, /// Needs to serialize on 204 /// instructions ahead of it 205 SerializeAfter, /// Needs to serialize instructions behind it 206 SerializeHandled, /// Serialization has been handled 207 NumStatus 208 }; 209 210 /** The status of this BaseDynInst. Several bits can be set. */ 211 std::bitset<NumStatus> status; 212 213 /** The thread this instruction is from. */ 214 ThreadID threadNumber; 215 216 /** data address space ID, for loads & stores. */ 217 short asid; 218 219 /** How many source registers are ready. */ 220 unsigned readyRegs; 221 222 /** Pointer to the Impl's CPU object. */ 223 ImplCPU *cpu; 224 225 /** Pointer to the thread state. */ 226 ImplState *thread; 227 228 /** The kind of fault this instruction has generated. */ 229 Fault fault; 230 231 /** Pointer to the data for the memory access. */ 232 uint8_t *memData; 233 234 /** The effective virtual address (lds & stores only). */ 235 Addr effAddr; 236 237 /** The size of the request */ 238 Addr effSize; 239 240 /** Is the effective virtual address valid. */ 241 bool effAddrValid; 242 243 /** The effective physical address. */ 244 Addr physEffAddr; 245 246 /** The memory request flags (from translation). */ 247 unsigned memReqFlags; 248 249 union Result { 250 uint64_t integer; 251// float fp; 252 double dbl; 253 }; 254 255 /** The result of the instruction; assumes for now that there's only one 256 * destination register. 257 */ 258 Result instResult; 259 260 /** Records changes to result? */ 261 bool recordResult; 262 263 /** Did this instruction execute, or is it predicated false */ 264 bool predicate; 265 266 protected: 267 /** PC state for this instruction. */ 268 TheISA::PCState pc; 269 270 /** Predicted PC state after this instruction. */ 271 TheISA::PCState predPC; 272 273 /** If this is a branch that was predicted taken */ 274 bool predTaken; 275 276 public: 277 278#ifdef DEBUG 279 void dumpSNList(); 280#endif 281 282 /** Whether or not the source register is ready. 283 * @todo: Not sure this should be here vs the derived class. 284 */ 285 bool _readySrcRegIdx[MaxInstSrcRegs]; 286 287 protected: 288 /** Flattened register index of the destination registers of this 289 * instruction. 290 */ 291 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs]; 292 293 /** Flattened register index of the source registers of this 294 * instruction. 295 */ 296 TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs]; 297 298 /** Physical register index of the destination registers of this 299 * instruction. 300 */ 301 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs]; 302 303 /** Physical register index of the source registers of this 304 * instruction. 305 */ 306 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs]; 307 308 /** Physical register index of the previous producers of the 309 * architected destinations. 310 */ 311 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs]; 312 313 public: 314 315 /** Returns the physical register index of the i'th destination 316 * register. 317 */ 318 PhysRegIndex renamedDestRegIdx(int idx) const 319 { 320 return _destRegIdx[idx]; 321 } 322 323 /** Returns the physical register index of the i'th source register. */ 324 PhysRegIndex renamedSrcRegIdx(int idx) const 325 { 326 return _srcRegIdx[idx]; 327 } 328 329 /** Returns the flattened register index of the i'th destination 330 * register. 331 */ 332 TheISA::RegIndex flattenedDestRegIdx(int idx) const 333 { 334 return _flatDestRegIdx[idx]; 335 } 336 337 /** Returns the flattened register index of the i'th source register */ 338 TheISA::RegIndex flattenedSrcRegIdx(int idx) const 339 { 340 return _flatSrcRegIdx[idx]; 341 } 342 343 /** Returns the physical register index of the previous physical register 344 * that remapped to the same logical register index. 345 */ 346 PhysRegIndex prevDestRegIdx(int idx) const 347 { 348 return _prevDestRegIdx[idx]; 349 } 350 351 /** Renames a destination register to a physical register. Also records 352 * the previous physical register that the logical register mapped to. 353 */ 354 void renameDestReg(int idx, 355 PhysRegIndex renamed_dest, 356 PhysRegIndex previous_rename) 357 { 358 _destRegIdx[idx] = renamed_dest; 359 _prevDestRegIdx[idx] = previous_rename; 360 } 361 362 /** Renames a source logical register to the physical register which 363 * has/will produce that logical register's result. 364 * @todo: add in whether or not the source register is ready. 365 */ 366 void renameSrcReg(int idx, PhysRegIndex renamed_src) 367 { 368 _srcRegIdx[idx] = renamed_src; 369 } 370 371 /** Flattens a source architectural register index into a logical index. 372 */ 373 void flattenSrcReg(int idx, TheISA::RegIndex flattened_src) 374 { 375 _flatSrcRegIdx[idx] = flattened_src; 376 } 377 378 /** Flattens a destination architectural register index into a logical 379 * index. 380 */ 381 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 382 { 383 _flatDestRegIdx[idx] = flattened_dest; 384 } 385 /** BaseDynInst constructor given a binary instruction. 386 * @param staticInst A StaticInstPtr to the underlying instruction. 387 * @param pc The PC state for the instruction. 388 * @param predPC The predicted next PC state for the instruction. 389 * @param seq_num The sequence number of the instruction. 390 * @param cpu Pointer to the instruction's CPU. 391 */ 392 BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop, 393 TheISA::PCState pc, TheISA::PCState predPC, 394 InstSeqNum seq_num, ImplCPU *cpu); 395 396 /** BaseDynInst constructor given a StaticInst pointer. 397 * @param _staticInst The StaticInst for this BaseDynInst. 398 */ 399 BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop); 400 401 /** BaseDynInst destructor. */ 402 ~BaseDynInst(); 403 404 private: 405 /** Function to initialize variables in the constructors. */ 406 void initVars(); 407 408 public: 409 /** Dumps out contents of this BaseDynInst. */ 410 void dump(); 411 412 /** Dumps out contents of this BaseDynInst into given string. */ 413 void dump(std::string &outstring); 414 415 /** Read this CPU's ID. */ 416 int cpuId() { return cpu->cpuId(); } 417 418 /** Read this context's system-wide ID **/ 419 int contextId() { return thread->contextId(); } 420 421 /** Returns the fault type. */ 422 Fault getFault() { return fault; } 423 424 /** Checks whether or not this instruction has had its branch target 425 * calculated yet. For now it is not utilized and is hacked to be 426 * always false. 427 * @todo: Actually use this instruction. 428 */ 429 bool doneTargCalc() { return false; } 430 431 /** Set the predicted target of this current instruction. */ 432 void setPredTarg(const TheISA::PCState &_predPC) 433 { 434 predPC = _predPC; 435 } 436 437 const TheISA::PCState &readPredTarg() { return predPC; } 438 439 /** Returns the predicted PC immediately after the branch. */ 440 Addr predInstAddr() { return predPC.instAddr(); } 441 442 /** Returns the predicted PC two instructions after the branch */ 443 Addr predNextInstAddr() { return predPC.nextInstAddr(); } 444 445 /** Returns the predicted micro PC after the branch */ 446 Addr predMicroPC() { return predPC.microPC(); } 447 448 /** Returns whether the instruction was predicted taken or not. */ 449 bool readPredTaken() 450 { 451 return predTaken; 452 } 453 454 void setPredTaken(bool predicted_taken) 455 { 456 predTaken = predicted_taken; 457 } 458 459 /** Returns whether the instruction mispredicted. */ 460 bool mispredicted() 461 { 462 TheISA::PCState tempPC = pc; 463 TheISA::advancePC(tempPC, staticInst); 464 return !(tempPC == predPC); 465 } 466 467 // 468 // Instruction types. Forward checks to StaticInst object. 469 // 470 bool isNop() const { return staticInst->isNop(); } 471 bool isMemRef() const { return staticInst->isMemRef(); } 472 bool isLoad() const { return staticInst->isLoad(); } 473 bool isStore() const { return staticInst->isStore(); } 474 bool isStoreConditional() const 475 { return staticInst->isStoreConditional(); } 476 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 477 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 478 bool isInteger() const { return staticInst->isInteger(); } 479 bool isFloating() const { return staticInst->isFloating(); } 480 bool isControl() const { return staticInst->isControl(); } 481 bool isCall() const { return staticInst->isCall(); } 482 bool isReturn() const { return staticInst->isReturn(); } 483 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 484 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 485 bool isCondCtrl() const { return staticInst->isCondCtrl(); } 486 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 487 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 488 bool isThreadSync() const { return staticInst->isThreadSync(); } 489 bool isSerializing() const { return staticInst->isSerializing(); } 490 bool isSerializeBefore() const 491 { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 492 bool isSerializeAfter() const 493 { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 494 bool isSquashAfter() const { return staticInst->isSquashAfter(); } 495 bool isMemBarrier() const { return staticInst->isMemBarrier(); } 496 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 497 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 498 bool isQuiesce() const { return staticInst->isQuiesce(); } 499 bool isIprAccess() const { return staticInst->isIprAccess(); } 500 bool isUnverifiable() const { return staticInst->isUnverifiable(); } 501 bool isSyscall() const { return staticInst->isSyscall(); } 502 bool isMacroop() const { return staticInst->isMacroop(); } 503 bool isMicroop() const { return staticInst->isMicroop(); } 504 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 505 bool isLastMicroop() const { return staticInst->isLastMicroop(); } 506 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 507 bool isMicroBranch() const { return staticInst->isMicroBranch(); } 508 509 /** Temporarily sets this instruction as a serialize before instruction. */ 510 void setSerializeBefore() { status.set(SerializeBefore); } 511 512 /** Clears the serializeBefore part of this instruction. */ 513 void clearSerializeBefore() { status.reset(SerializeBefore); } 514 515 /** Checks if this serializeBefore is only temporarily set. */ 516 bool isTempSerializeBefore() { return status[SerializeBefore]; } 517 518 /** Temporarily sets this instruction as a serialize after instruction. */ 519 void setSerializeAfter() { status.set(SerializeAfter); } 520 521 /** Clears the serializeAfter part of this instruction.*/ 522 void clearSerializeAfter() { status.reset(SerializeAfter); } 523 524 /** Checks if this serializeAfter is only temporarily set. */ 525 bool isTempSerializeAfter() { return status[SerializeAfter]; } 526 527 /** Sets the serialization part of this instruction as handled. */ 528 void setSerializeHandled() { status.set(SerializeHandled); } 529 530 /** Checks if the serialization part of this instruction has been 531 * handled. This does not apply to the temporary serializing 532 * state; it only applies to this instruction's own permanent 533 * serializing state. 534 */ 535 bool isSerializeHandled() { return status[SerializeHandled]; } 536 537 /** Returns the opclass of this instruction. */ 538 OpClass opClass() const { return staticInst->opClass(); } 539 540 /** Returns the branch target address. */ 541 TheISA::PCState branchTarget() const 542 { return staticInst->branchTarget(pc); } 543 544 /** Returns the number of source registers. */ 545 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 546 547 /** Returns the number of destination registers. */ 548 int8_t numDestRegs() const { return staticInst->numDestRegs(); } 549 550 // the following are used to track physical register usage 551 // for machines with separate int & FP reg files 552 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 553 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 554 555 /** Returns the logical register index of the i'th destination register. */ 556 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 557 558 /** Returns the logical register index of the i'th source register. */ 559 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 560 561 /** Returns the result of an integer instruction. */ 562 uint64_t readIntResult() { return instResult.integer; } 563 564 /** Returns the result of a floating point instruction. */ 565 float readFloatResult() { return (float)instResult.dbl; } 566 567 /** Returns the result of a floating point (double) instruction. */ 568 double readDoubleResult() { return instResult.dbl; } 569 570 /** Records an integer register being set to a value. */ 571 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 572 { 573 if (recordResult) 574 instResult.integer = val; 575 } 576 577 /** Records an fp register being set to a value. */ 578 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 579 int width) 580 { 581 if (recordResult) { 582 if (width == 32) 583 instResult.dbl = (double)val; 584 else if (width == 64) 585 instResult.dbl = val; 586 else 587 panic("Unsupported width!"); 588 } 589 } 590 591 /** Records an fp register being set to a value. */ 592 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 593 { 594 if (recordResult) 595 instResult.dbl = (double)val; 596 } 597 598 /** Records an fp register being set to an integer value. */ 599 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val, 600 int width) 601 { 602 if (recordResult) 603 instResult.integer = val; 604 } 605 606 /** Records an fp register being set to an integer value. */ 607 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val) 608 { 609 if (recordResult) 610 instResult.integer = val; 611 } 612 613 /** Records that one of the source registers is ready. */ 614 void markSrcRegReady(); 615 616 /** Marks a specific register as ready. */ 617 void markSrcRegReady(RegIndex src_idx); 618 619 /** Returns if a source register is ready. */ 620 bool isReadySrcRegIdx(int idx) const 621 { 622 return this->_readySrcRegIdx[idx]; 623 } 624 625 /** Sets this instruction as completed. */ 626 void setCompleted() { status.set(Completed); } 627 628 /** Returns whether or not this instruction is completed. */ 629 bool isCompleted() const { return status[Completed]; } 630 631 /** Marks the result as ready. */ 632 void setResultReady() { status.set(ResultReady); } 633 634 /** Returns whether or not the result is ready. */ 635 bool isResultReady() const { return status[ResultReady]; } 636 637 /** Sets this instruction as ready to issue. */ 638 void setCanIssue() { status.set(CanIssue); } 639 640 /** Returns whether or not this instruction is ready to issue. */ 641 bool readyToIssue() const { return status[CanIssue]; } 642 643 /** Clears this instruction being able to issue. */ 644 void clearCanIssue() { status.reset(CanIssue); } 645 646 /** Sets this instruction as issued from the IQ. */ 647 void setIssued() { status.set(Issued); } 648 649 /** Returns whether or not this instruction has issued. */ 650 bool isIssued() const { return status[Issued]; } 651 652 /** Clears this instruction as being issued. */ 653 void clearIssued() { status.reset(Issued); } 654 655 /** Sets this instruction as executed. */ 656 void setExecuted() { status.set(Executed); } 657 658 /** Returns whether or not this instruction has executed. */ 659 bool isExecuted() const { return status[Executed]; } 660 661 /** Sets this instruction as ready to commit. */ 662 void setCanCommit() { status.set(CanCommit); } 663 664 /** Clears this instruction as being ready to commit. */ 665 void clearCanCommit() { status.reset(CanCommit); } 666 667 /** Returns whether or not this instruction is ready to commit. */ 668 bool readyToCommit() const { return status[CanCommit]; } 669 670 void setAtCommit() { status.set(AtCommit); } 671 672 bool isAtCommit() { return status[AtCommit]; } 673 674 /** Sets this instruction as committed. */ 675 void setCommitted() { status.set(Committed); } 676 677 /** Returns whether or not this instruction is committed. */ 678 bool isCommitted() const { return status[Committed]; } 679 680 /** Sets this instruction as squashed. */ 681 void setSquashed() { status.set(Squashed); } 682 683 /** Returns whether or not this instruction is squashed. */ 684 bool isSquashed() const { return status[Squashed]; } 685 686 //Instruction Queue Entry 687 //----------------------- 688 /** Sets this instruction as a entry the IQ. */ 689 void setInIQ() { status.set(IqEntry); } 690 691 /** Sets this instruction as a entry the IQ. */ 692 void clearInIQ() { status.reset(IqEntry); } 693 694 /** Returns whether or not this instruction has issued. */ 695 bool isInIQ() const { return status[IqEntry]; } 696 697 /** Sets this instruction as squashed in the IQ. */ 698 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 699 700 /** Returns whether or not this instruction is squashed in the IQ. */ 701 bool isSquashedInIQ() const { return status[SquashedInIQ]; } 702 703 704 //Load / Store Queue Functions 705 //----------------------- 706 /** Sets this instruction as a entry the LSQ. */ 707 void setInLSQ() { status.set(LsqEntry); } 708 709 /** Sets this instruction as a entry the LSQ. */ 710 void removeInLSQ() { status.reset(LsqEntry); } 711 712 /** Returns whether or not this instruction is in the LSQ. */ 713 bool isInLSQ() const { return status[LsqEntry]; } 714 715 /** Sets this instruction as squashed in the LSQ. */ 716 void setSquashedInLSQ() { status.set(SquashedInLSQ);} 717 718 /** Returns whether or not this instruction is squashed in the LSQ. */ 719 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 720 721 722 //Reorder Buffer Functions 723 //----------------------- 724 /** Sets this instruction as a entry the ROB. */ 725 void setInROB() { status.set(RobEntry); } 726 727 /** Sets this instruction as a entry the ROB. */ 728 void clearInROB() { status.reset(RobEntry); } 729 730 /** Returns whether or not this instruction is in the ROB. */ 731 bool isInROB() const { return status[RobEntry]; } 732 733 /** Sets this instruction as squashed in the ROB. */ 734 void setSquashedInROB() { status.set(SquashedInROB); } 735 736 /** Returns whether or not this instruction is squashed in the ROB. */ 737 bool isSquashedInROB() const { return status[SquashedInROB]; } 738 739 /** Read the PC state of this instruction. */ 740 const TheISA::PCState pcState() const { return pc; } 741 742 /** Set the PC state of this instruction. */ 743 const void pcState(const TheISA::PCState &val) { pc = val; } 744 745 /** Read the PC of this instruction. */ 746 const Addr instAddr() const { return pc.instAddr(); } 747 748 /** Read the PC of the next instruction. */ 749 const Addr nextInstAddr() const { return pc.nextInstAddr(); } 750 751 /**Read the micro PC of this instruction. */ 752 const Addr microPC() const { return pc.microPC(); } 753 754 bool readPredicate() 755 { 756 return predicate; 757 } 758 759 void setPredicate(bool val) 760 { 761 predicate = val; 762 763 if (traceData) { 764 traceData->setPredicate(val); 765 } 766 } 767 768 /** Sets the ASID. */ 769 void setASID(short addr_space_id) { asid = addr_space_id; } 770 771 /** Sets the thread id. */ 772 void setTid(ThreadID tid) { threadNumber = tid; } 773 774 /** Sets the pointer to the thread state. */ 775 void setThreadState(ImplState *state) { thread = state; } 776 777 /** Returns the thread context. */ 778 ThreadContext *tcBase() { return thread->getTC(); } 779 780 private: 781 /** Instruction effective address. 782 * @todo: Consider if this is necessary or not. 783 */ 784 Addr instEffAddr; 785 786 /** Whether or not the effective address calculation is completed. 787 * @todo: Consider if this is necessary or not. 788 */ 789 bool eaCalcDone; 790 791 /** Is this instruction's memory access uncacheable. */ 792 bool isUncacheable; 793 794 /** Has this instruction generated a memory request. */ 795 bool reqMade; 796 797 public: 798 /** Sets the effective address. */ 799 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 800 801 /** Returns the effective address. */ 802 const Addr &getEA() const { return instEffAddr; } 803 804 /** Returns whether or not the eff. addr. calculation has been completed. */ 805 bool doneEACalc() { return eaCalcDone; } 806 807 /** Returns whether or not the eff. addr. source registers are ready. */ 808 bool eaSrcsReady(); 809 810 /** Whether or not the memory operation is done. */ 811 bool memOpDone; 812 813 /** Is this instruction's memory access uncacheable. */ 814 bool uncacheable() { return isUncacheable; } 815 816 /** Has this instruction generated a memory request. */ 817 bool hasRequest() { return reqMade; } 818 819 public: 820 /** Load queue index. */ 821 int16_t lqIdx; 822 823 /** Store queue index. */ 824 int16_t sqIdx; 825 826 /** Iterator pointing to this BaseDynInst in the list of all insts. */ 827 ListIt instListIt; 828 829 /** Returns iterator to this instruction in the list of all insts. */ 830 ListIt &getInstListIt() { return instListIt; } 831 832 /** Sets iterator for this instruction in the list of all insts. */ 833 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 834 835 public: 836 /** Returns the number of consecutive store conditional failures. */ 837 unsigned readStCondFailures() 838 { return thread->storeCondFailures; } 839 840 /** Sets the number of consecutive store conditional failures. */ 841 void setStCondFailures(unsigned sc_failures) 842 { thread->storeCondFailures = sc_failures; } 843}; 844 845template<class Impl> 846Fault 847BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data, 848 unsigned size, unsigned flags) 849{ 850 reqMade = true; 851 Request *req = NULL; 852 Request *sreqLow = NULL; 853 Request *sreqHigh = NULL; 854 855 if (reqMade && translationStarted) { 856 req = savedReq; 857 sreqLow = savedSreqLow; 858 sreqHigh = savedSreqHigh; 859 } else { 860 req = new Request(asid, addr, size, flags, this->pc.instAddr(), 861 thread->contextId(), threadNumber); 862 863 // Only split the request if the ISA supports unaligned accesses. 864 if (TheISA::HasUnalignedMemAcc) { 865 splitRequest(req, sreqLow, sreqHigh); 866 } 867 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read); 868 } 869 870 if (translationCompleted) { 871 if (fault == NoFault) { 872 effAddr = req->getVaddr(); 873 effSize = size; 874 effAddrValid = true; 875 fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx); 876 } else { 877 // Commit will have to clean up whatever happened. Set this 878 // instruction as executed. 879 this->setExecuted(); 880 } 881 882 if (fault != NoFault) { 883 // Return a fixed value to keep simulation deterministic even 884 // along misspeculated paths. 885 if (data) 886 bzero(data, size); 887 } 888 } 889 890 if (traceData) { 891 traceData->setAddr(addr); 892 } 893 894 return fault; 895} 896 897template<class Impl> 898Fault 899BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, 900 Addr addr, unsigned flags, uint64_t *res) 901{ 902 if (traceData) { 903 traceData->setAddr(addr); 904 } 905 906 reqMade = true; 907 Request *req = NULL; 908 Request *sreqLow = NULL; 909 Request *sreqHigh = NULL; 910 911 if (reqMade && translationStarted) { 912 req = savedReq; 913 sreqLow = savedSreqLow; 914 sreqHigh = savedSreqHigh; 915 } else { 916 req = new Request(asid, addr, size, flags, this->pc.instAddr(), 917 thread->contextId(), threadNumber); 918 919 // Only split the request if the ISA supports unaligned accesses. 920 if (TheISA::HasUnalignedMemAcc) { 921 splitRequest(req, sreqLow, sreqHigh); 922 } 923 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write); 924 } 925 926 if (fault == NoFault && translationCompleted) { 927 effAddr = req->getVaddr(); 928 effSize = size; 929 effAddrValid = true; 930 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx); 931 } 932 933 return fault; 934} 935 936template<class Impl> 937inline void 938BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow, 939 RequestPtr &sreqHigh) 940{ 941 // Check to see if the request crosses the next level block boundary. 942 unsigned block_size = cpu->getDcachePort()->peerBlockSize(); 943 Addr addr = req->getVaddr(); 944 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size); 945 assert(split_addr <= addr || split_addr - addr < block_size); 946 947 // Spans two blocks. 948 if (split_addr > addr) { 949 req->splitOnVaddr(split_addr, sreqLow, sreqHigh); 950 } 951} 952 953template<class Impl> 954inline void 955BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow, 956 RequestPtr sreqHigh, uint64_t *res, 957 BaseTLB::Mode mode) 958{ 959 translationStarted = true; 960 961 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) { 962 WholeTranslationState *state = 963 new WholeTranslationState(req, NULL, res, mode); 964 965 // One translation if the request isn't split. 966 DataTranslation<BaseDynInstPtr> *trans = 967 new DataTranslation<BaseDynInstPtr>(this, state); 968 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode); 969 if (!translationCompleted) { 970 // Save memory requests. 971 savedReq = state->mainReq; 972 savedSreqLow = state->sreqLow; 973 savedSreqHigh = state->sreqHigh; 974 } 975 } else { 976 WholeTranslationState *state = 977 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode); 978 979 // Two translations when the request is split. 980 DataTranslation<BaseDynInstPtr> *stransLow = 981 new DataTranslation<BaseDynInstPtr>(this, state, 0); 982 DataTranslation<BaseDynInstPtr> *stransHigh = 983 new DataTranslation<BaseDynInstPtr>(this, state, 1); 984 985 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode); 986 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode); 987 if (!translationCompleted) { 988 // Save memory requests. 989 savedReq = state->mainReq; 990 savedSreqLow = state->sreqLow; 991 savedSreqHigh = state->sreqHigh; 992 } 993 } 994} 995 996template<class Impl> 997inline void 998BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state) 999{ 1000 fault = state->getFault(); 1001 1002 if (state->isUncacheable()) 1003 isUncacheable = true; 1004 1005 if (fault == NoFault) { 1006 physEffAddr = state->getPaddr(); 1007 memReqFlags = state->getFlags(); 1008 1009 if (state->mainReq->isCondSwap()) { 1010 assert(state->res); 1011 state->mainReq->setExtraData(*state->res); 1012 } 1013 1014 } else { 1015 state->deleteReqs(); 1016 } 1017 delete state; 1018 1019 translationCompleted = true; 1020} 1021 1022#endif // __CPU_BASE_DYN_INST_HH__ 1023