base_dyn_inst.hh revision 8502
1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * Copyright (c) 2009 The University of Edinburgh 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 * Timothy M. Jones 43 */ 44 45#ifndef __CPU_BASE_DYN_INST_HH__ 46#define __CPU_BASE_DYN_INST_HH__ 47 48#include <bitset> 49#include <list> 50#include <string> 51 52#include "arch/faults.hh" 53#include "arch/utility.hh" 54#include "base/fast_alloc.hh" 55#include "base/trace.hh" 56#include "config/full_system.hh" 57#include "config/the_isa.hh" 58#include "cpu/o3/comm.hh" 59#include "cpu/exetrace.hh" 60#include "cpu/inst_seq.hh" 61#include "cpu/op_class.hh" 62#include "cpu/static_inst.hh" 63#include "cpu/translation.hh" 64#include "mem/packet.hh" 65#include "sim/byteswap.hh" 66#include "sim/system.hh" 67#include "sim/tlb.hh" 68 69/** 70 * @file 71 * Defines a dynamic instruction context. 72 */ 73 74// Forward declaration. 75class StaticInstPtr; 76 77template <class Impl> 78class BaseDynInst : public FastAlloc, public RefCounted 79{ 80 public: 81 // Typedef for the CPU. 82 typedef typename Impl::CPUType ImplCPU; 83 typedef typename ImplCPU::ImplState ImplState; 84 85 // Logical register index type. 86 typedef TheISA::RegIndex RegIndex; 87 // Integer register type. 88 typedef TheISA::IntReg IntReg; 89 // Floating point register type. 90 typedef TheISA::FloatReg FloatReg; 91 92 // The DynInstPtr type. 93 typedef typename Impl::DynInstPtr DynInstPtr; 94 typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr; 95 96 // The list of instructions iterator type. 97 typedef typename std::list<DynInstPtr>::iterator ListIt; 98 99 enum { 100 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 101 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs 102 }; 103 104 /** The StaticInst used by this BaseDynInst. */ 105 StaticInstPtr staticInst; 106 StaticInstPtr macroop; 107 108 //////////////////////////////////////////// 109 // 110 // INSTRUCTION EXECUTION 111 // 112 //////////////////////////////////////////// 113 /** InstRecord that tracks this instructions. */ 114 Trace::InstRecord *traceData; 115 116 void demapPage(Addr vaddr, uint64_t asn) 117 { 118 cpu->demapPage(vaddr, asn); 119 } 120 void demapInstPage(Addr vaddr, uint64_t asn) 121 { 122 cpu->demapPage(vaddr, asn); 123 } 124 void demapDataPage(Addr vaddr, uint64_t asn) 125 { 126 cpu->demapPage(vaddr, asn); 127 } 128 129 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 130 131 Fault writeMem(uint8_t *data, unsigned size, 132 Addr addr, unsigned flags, uint64_t *res); 133 134 /** Splits a request in two if it crosses a dcache block. */ 135 void splitRequest(RequestPtr req, RequestPtr &sreqLow, 136 RequestPtr &sreqHigh); 137 138 /** Initiate a DTB address translation. */ 139 void initiateTranslation(RequestPtr req, RequestPtr sreqLow, 140 RequestPtr sreqHigh, uint64_t *res, 141 BaseTLB::Mode mode); 142 143 /** Finish a DTB address translation. */ 144 void finishTranslation(WholeTranslationState *state); 145 146 /** True if the DTB address translation has started. */ 147 bool translationStarted; 148 149 /** True if the DTB address translation has completed. */ 150 bool translationCompleted; 151 152 /** 153 * Returns true if the DTB address translation is being delayed due to a hw 154 * page table walk. 155 */ 156 bool isTranslationDelayed() const 157 { 158 return (translationStarted && !translationCompleted); 159 } 160 161 /** 162 * Saved memory requests (needed when the DTB address translation is 163 * delayed due to a hw page table walk). 164 */ 165 RequestPtr savedReq; 166 RequestPtr savedSreqLow; 167 RequestPtr savedSreqHigh; 168 169 /** @todo: Consider making this private. */ 170 public: 171 /** The sequence number of the instruction. */ 172 InstSeqNum seqNum; 173 174 enum Status { 175 IqEntry, /// Instruction is in the IQ 176 RobEntry, /// Instruction is in the ROB 177 LsqEntry, /// Instruction is in the LSQ 178 Completed, /// Instruction has completed 179 ResultReady, /// Instruction has its result 180 CanIssue, /// Instruction can issue and execute 181 Issued, /// Instruction has issued 182 Executed, /// Instruction has executed 183 CanCommit, /// Instruction can commit 184 AtCommit, /// Instruction has reached commit 185 Committed, /// Instruction has committed 186 Squashed, /// Instruction is squashed 187 SquashedInIQ, /// Instruction is squashed in the IQ 188 SquashedInLSQ, /// Instruction is squashed in the LSQ 189 SquashedInROB, /// Instruction is squashed in the ROB 190 RecoverInst, /// Is a recover instruction 191 BlockingInst, /// Is a blocking instruction 192 ThreadsyncWait, /// Is a thread synchronization instruction 193 SerializeBefore, /// Needs to serialize on 194 /// instructions ahead of it 195 SerializeAfter, /// Needs to serialize instructions behind it 196 SerializeHandled, /// Serialization has been handled 197 NumStatus 198 }; 199 200 /** The status of this BaseDynInst. Several bits can be set. */ 201 std::bitset<NumStatus> status; 202 203 /** The thread this instruction is from. */ 204 ThreadID threadNumber; 205 206 /** data address space ID, for loads & stores. */ 207 short asid; 208 209 /** How many source registers are ready. */ 210 unsigned readyRegs; 211 212 /** Pointer to the Impl's CPU object. */ 213 ImplCPU *cpu; 214 215 /** Pointer to the thread state. */ 216 ImplState *thread; 217 218 /** The kind of fault this instruction has generated. */ 219 Fault fault; 220 221 /** Pointer to the data for the memory access. */ 222 uint8_t *memData; 223 224 /** The effective virtual address (lds & stores only). */ 225 Addr effAddr; 226 227 /** The size of the request */ 228 Addr effSize; 229 230 /** Is the effective virtual address valid. */ 231 bool effAddrValid; 232 233 /** The effective physical address. */ 234 Addr physEffAddr; 235 236 /** The memory request flags (from translation). */ 237 unsigned memReqFlags; 238 239 union Result { 240 uint64_t integer; 241// float fp; 242 double dbl; 243 }; 244 245 /** The result of the instruction; assumes for now that there's only one 246 * destination register. 247 */ 248 Result instResult; 249 250 /** Records changes to result? */ 251 bool recordResult; 252 253 /** Did this instruction execute, or is it predicated false */ 254 bool predicate; 255 256 protected: 257 /** PC state for this instruction. */ 258 TheISA::PCState pc; 259 260 /** Predicted PC state after this instruction. */ 261 TheISA::PCState predPC; 262 263 /** If this is a branch that was predicted taken */ 264 bool predTaken; 265 266 public: 267 268#ifdef DEBUG 269 void dumpSNList(); 270#endif 271 272 /** Whether or not the source register is ready. 273 * @todo: Not sure this should be here vs the derived class. 274 */ 275 bool _readySrcRegIdx[MaxInstSrcRegs]; 276 277 protected: 278 /** Flattened register index of the destination registers of this 279 * instruction. 280 */ 281 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs]; 282 283 /** Flattened register index of the source registers of this 284 * instruction. 285 */ 286 TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs]; 287 288 /** Physical register index of the destination registers of this 289 * instruction. 290 */ 291 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs]; 292 293 /** Physical register index of the source registers of this 294 * instruction. 295 */ 296 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs]; 297 298 /** Physical register index of the previous producers of the 299 * architected destinations. 300 */ 301 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs]; 302 303 public: 304 305 /** Returns the physical register index of the i'th destination 306 * register. 307 */ 308 PhysRegIndex renamedDestRegIdx(int idx) const 309 { 310 return _destRegIdx[idx]; 311 } 312 313 /** Returns the physical register index of the i'th source register. */ 314 PhysRegIndex renamedSrcRegIdx(int idx) const 315 { 316 return _srcRegIdx[idx]; 317 } 318 319 /** Returns the flattened register index of the i'th destination 320 * register. 321 */ 322 TheISA::RegIndex flattenedDestRegIdx(int idx) const 323 { 324 return _flatDestRegIdx[idx]; 325 } 326 327 /** Returns the flattened register index of the i'th source register */ 328 TheISA::RegIndex flattenedSrcRegIdx(int idx) const 329 { 330 return _flatSrcRegIdx[idx]; 331 } 332 333 /** Returns the physical register index of the previous physical register 334 * that remapped to the same logical register index. 335 */ 336 PhysRegIndex prevDestRegIdx(int idx) const 337 { 338 return _prevDestRegIdx[idx]; 339 } 340 341 /** Renames a destination register to a physical register. Also records 342 * the previous physical register that the logical register mapped to. 343 */ 344 void renameDestReg(int idx, 345 PhysRegIndex renamed_dest, 346 PhysRegIndex previous_rename) 347 { 348 _destRegIdx[idx] = renamed_dest; 349 _prevDestRegIdx[idx] = previous_rename; 350 } 351 352 /** Renames a source logical register to the physical register which 353 * has/will produce that logical register's result. 354 * @todo: add in whether or not the source register is ready. 355 */ 356 void renameSrcReg(int idx, PhysRegIndex renamed_src) 357 { 358 _srcRegIdx[idx] = renamed_src; 359 } 360 361 /** Flattens a source architectural register index into a logical index. 362 */ 363 void flattenSrcReg(int idx, TheISA::RegIndex flattened_src) 364 { 365 _flatSrcRegIdx[idx] = flattened_src; 366 } 367 368 /** Flattens a destination architectural register index into a logical 369 * index. 370 */ 371 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 372 { 373 _flatDestRegIdx[idx] = flattened_dest; 374 } 375 /** BaseDynInst constructor given a binary instruction. 376 * @param staticInst A StaticInstPtr to the underlying instruction. 377 * @param pc The PC state for the instruction. 378 * @param predPC The predicted next PC state for the instruction. 379 * @param seq_num The sequence number of the instruction. 380 * @param cpu Pointer to the instruction's CPU. 381 */ 382 BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop, 383 TheISA::PCState pc, TheISA::PCState predPC, 384 InstSeqNum seq_num, ImplCPU *cpu); 385 386 /** BaseDynInst constructor given a StaticInst pointer. 387 * @param _staticInst The StaticInst for this BaseDynInst. 388 */ 389 BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop); 390 391 /** BaseDynInst destructor. */ 392 ~BaseDynInst(); 393 394 private: 395 /** Function to initialize variables in the constructors. */ 396 void initVars(); 397 398 public: 399 /** Dumps out contents of this BaseDynInst. */ 400 void dump(); 401 402 /** Dumps out contents of this BaseDynInst into given string. */ 403 void dump(std::string &outstring); 404 405 /** Read this CPU's ID. */ 406 int cpuId() { return cpu->cpuId(); } 407 408 /** Read this context's system-wide ID **/ 409 int contextId() { return thread->contextId(); } 410 411 /** Returns the fault type. */ 412 Fault getFault() { return fault; } 413 414 /** Checks whether or not this instruction has had its branch target 415 * calculated yet. For now it is not utilized and is hacked to be 416 * always false. 417 * @todo: Actually use this instruction. 418 */ 419 bool doneTargCalc() { return false; } 420 421 /** Set the predicted target of this current instruction. */ 422 void setPredTarg(const TheISA::PCState &_predPC) 423 { 424 predPC = _predPC; 425 } 426 427 const TheISA::PCState &readPredTarg() { return predPC; } 428 429 /** Returns the predicted PC immediately after the branch. */ 430 Addr predInstAddr() { return predPC.instAddr(); } 431 432 /** Returns the predicted PC two instructions after the branch */ 433 Addr predNextInstAddr() { return predPC.nextInstAddr(); } 434 435 /** Returns the predicted micro PC after the branch */ 436 Addr predMicroPC() { return predPC.microPC(); } 437 438 /** Returns whether the instruction was predicted taken or not. */ 439 bool readPredTaken() 440 { 441 return predTaken; 442 } 443 444 void setPredTaken(bool predicted_taken) 445 { 446 predTaken = predicted_taken; 447 } 448 449 /** Returns whether the instruction mispredicted. */ 450 bool mispredicted() 451 { 452 TheISA::PCState tempPC = pc; 453 TheISA::advancePC(tempPC, staticInst); 454 return !(tempPC == predPC); 455 } 456 457 // 458 // Instruction types. Forward checks to StaticInst object. 459 // 460 bool isNop() const { return staticInst->isNop(); } 461 bool isMemRef() const { return staticInst->isMemRef(); } 462 bool isLoad() const { return staticInst->isLoad(); } 463 bool isStore() const { return staticInst->isStore(); } 464 bool isStoreConditional() const 465 { return staticInst->isStoreConditional(); } 466 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 467 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 468 bool isInteger() const { return staticInst->isInteger(); } 469 bool isFloating() const { return staticInst->isFloating(); } 470 bool isControl() const { return staticInst->isControl(); } 471 bool isCall() const { return staticInst->isCall(); } 472 bool isReturn() const { return staticInst->isReturn(); } 473 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 474 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 475 bool isCondCtrl() const { return staticInst->isCondCtrl(); } 476 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 477 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 478 bool isThreadSync() const { return staticInst->isThreadSync(); } 479 bool isSerializing() const { return staticInst->isSerializing(); } 480 bool isSerializeBefore() const 481 { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 482 bool isSerializeAfter() const 483 { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 484 bool isSquashAfter() const { return staticInst->isSquashAfter(); } 485 bool isMemBarrier() const { return staticInst->isMemBarrier(); } 486 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 487 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 488 bool isQuiesce() const { return staticInst->isQuiesce(); } 489 bool isIprAccess() const { return staticInst->isIprAccess(); } 490 bool isUnverifiable() const { return staticInst->isUnverifiable(); } 491 bool isSyscall() const { return staticInst->isSyscall(); } 492 bool isMacroop() const { return staticInst->isMacroop(); } 493 bool isMicroop() const { return staticInst->isMicroop(); } 494 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 495 bool isLastMicroop() const { return staticInst->isLastMicroop(); } 496 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 497 bool isMicroBranch() const { return staticInst->isMicroBranch(); } 498 499 /** Temporarily sets this instruction as a serialize before instruction. */ 500 void setSerializeBefore() { status.set(SerializeBefore); } 501 502 /** Clears the serializeBefore part of this instruction. */ 503 void clearSerializeBefore() { status.reset(SerializeBefore); } 504 505 /** Checks if this serializeBefore is only temporarily set. */ 506 bool isTempSerializeBefore() { return status[SerializeBefore]; } 507 508 /** Temporarily sets this instruction as a serialize after instruction. */ 509 void setSerializeAfter() { status.set(SerializeAfter); } 510 511 /** Clears the serializeAfter part of this instruction.*/ 512 void clearSerializeAfter() { status.reset(SerializeAfter); } 513 514 /** Checks if this serializeAfter is only temporarily set. */ 515 bool isTempSerializeAfter() { return status[SerializeAfter]; } 516 517 /** Sets the serialization part of this instruction as handled. */ 518 void setSerializeHandled() { status.set(SerializeHandled); } 519 520 /** Checks if the serialization part of this instruction has been 521 * handled. This does not apply to the temporary serializing 522 * state; it only applies to this instruction's own permanent 523 * serializing state. 524 */ 525 bool isSerializeHandled() { return status[SerializeHandled]; } 526 527 /** Returns the opclass of this instruction. */ 528 OpClass opClass() const { return staticInst->opClass(); } 529 530 /** Returns the branch target address. */ 531 TheISA::PCState branchTarget() const 532 { return staticInst->branchTarget(pc); } 533 534 /** Returns the number of source registers. */ 535 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 536 537 /** Returns the number of destination registers. */ 538 int8_t numDestRegs() const { return staticInst->numDestRegs(); } 539 540 // the following are used to track physical register usage 541 // for machines with separate int & FP reg files 542 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 543 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 544 545 /** Returns the logical register index of the i'th destination register. */ 546 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 547 548 /** Returns the logical register index of the i'th source register. */ 549 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 550 551 /** Returns the result of an integer instruction. */ 552 uint64_t readIntResult() { return instResult.integer; } 553 554 /** Returns the result of a floating point instruction. */ 555 float readFloatResult() { return (float)instResult.dbl; } 556 557 /** Returns the result of a floating point (double) instruction. */ 558 double readDoubleResult() { return instResult.dbl; } 559 560 /** Records an integer register being set to a value. */ 561 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 562 { 563 if (recordResult) 564 instResult.integer = val; 565 } 566 567 /** Records an fp register being set to a value. */ 568 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 569 int width) 570 { 571 if (recordResult) { 572 if (width == 32) 573 instResult.dbl = (double)val; 574 else if (width == 64) 575 instResult.dbl = val; 576 else 577 panic("Unsupported width!"); 578 } 579 } 580 581 /** Records an fp register being set to a value. */ 582 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 583 { 584 if (recordResult) 585 instResult.dbl = (double)val; 586 } 587 588 /** Records an fp register being set to an integer value. */ 589 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val, 590 int width) 591 { 592 if (recordResult) 593 instResult.integer = val; 594 } 595 596 /** Records an fp register being set to an integer value. */ 597 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val) 598 { 599 if (recordResult) 600 instResult.integer = val; 601 } 602 603 /** Records that one of the source registers is ready. */ 604 void markSrcRegReady(); 605 606 /** Marks a specific register as ready. */ 607 void markSrcRegReady(RegIndex src_idx); 608 609 /** Returns if a source register is ready. */ 610 bool isReadySrcRegIdx(int idx) const 611 { 612 return this->_readySrcRegIdx[idx]; 613 } 614 615 /** Sets this instruction as completed. */ 616 void setCompleted() { status.set(Completed); } 617 618 /** Returns whether or not this instruction is completed. */ 619 bool isCompleted() const { return status[Completed]; } 620 621 /** Marks the result as ready. */ 622 void setResultReady() { status.set(ResultReady); } 623 624 /** Returns whether or not the result is ready. */ 625 bool isResultReady() const { return status[ResultReady]; } 626 627 /** Sets this instruction as ready to issue. */ 628 void setCanIssue() { status.set(CanIssue); } 629 630 /** Returns whether or not this instruction is ready to issue. */ 631 bool readyToIssue() const { return status[CanIssue]; } 632 633 /** Clears this instruction being able to issue. */ 634 void clearCanIssue() { status.reset(CanIssue); } 635 636 /** Sets this instruction as issued from the IQ. */ 637 void setIssued() { status.set(Issued); } 638 639 /** Returns whether or not this instruction has issued. */ 640 bool isIssued() const { return status[Issued]; } 641 642 /** Clears this instruction as being issued. */ 643 void clearIssued() { status.reset(Issued); } 644 645 /** Sets this instruction as executed. */ 646 void setExecuted() { status.set(Executed); } 647 648 /** Returns whether or not this instruction has executed. */ 649 bool isExecuted() const { return status[Executed]; } 650 651 /** Sets this instruction as ready to commit. */ 652 void setCanCommit() { status.set(CanCommit); } 653 654 /** Clears this instruction as being ready to commit. */ 655 void clearCanCommit() { status.reset(CanCommit); } 656 657 /** Returns whether or not this instruction is ready to commit. */ 658 bool readyToCommit() const { return status[CanCommit]; } 659 660 void setAtCommit() { status.set(AtCommit); } 661 662 bool isAtCommit() { return status[AtCommit]; } 663 664 /** Sets this instruction as committed. */ 665 void setCommitted() { status.set(Committed); } 666 667 /** Returns whether or not this instruction is committed. */ 668 bool isCommitted() const { return status[Committed]; } 669 670 /** Sets this instruction as squashed. */ 671 void setSquashed() { status.set(Squashed); } 672 673 /** Returns whether or not this instruction is squashed. */ 674 bool isSquashed() const { return status[Squashed]; } 675 676 //Instruction Queue Entry 677 //----------------------- 678 /** Sets this instruction as a entry the IQ. */ 679 void setInIQ() { status.set(IqEntry); } 680 681 /** Sets this instruction as a entry the IQ. */ 682 void clearInIQ() { status.reset(IqEntry); } 683 684 /** Returns whether or not this instruction has issued. */ 685 bool isInIQ() const { return status[IqEntry]; } 686 687 /** Sets this instruction as squashed in the IQ. */ 688 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 689 690 /** Returns whether or not this instruction is squashed in the IQ. */ 691 bool isSquashedInIQ() const { return status[SquashedInIQ]; } 692 693 694 //Load / Store Queue Functions 695 //----------------------- 696 /** Sets this instruction as a entry the LSQ. */ 697 void setInLSQ() { status.set(LsqEntry); } 698 699 /** Sets this instruction as a entry the LSQ. */ 700 void removeInLSQ() { status.reset(LsqEntry); } 701 702 /** Returns whether or not this instruction is in the LSQ. */ 703 bool isInLSQ() const { return status[LsqEntry]; } 704 705 /** Sets this instruction as squashed in the LSQ. */ 706 void setSquashedInLSQ() { status.set(SquashedInLSQ);} 707 708 /** Returns whether or not this instruction is squashed in the LSQ. */ 709 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 710 711 712 //Reorder Buffer Functions 713 //----------------------- 714 /** Sets this instruction as a entry the ROB. */ 715 void setInROB() { status.set(RobEntry); } 716 717 /** Sets this instruction as a entry the ROB. */ 718 void clearInROB() { status.reset(RobEntry); } 719 720 /** Returns whether or not this instruction is in the ROB. */ 721 bool isInROB() const { return status[RobEntry]; } 722 723 /** Sets this instruction as squashed in the ROB. */ 724 void setSquashedInROB() { status.set(SquashedInROB); } 725 726 /** Returns whether or not this instruction is squashed in the ROB. */ 727 bool isSquashedInROB() const { return status[SquashedInROB]; } 728 729 /** Read the PC state of this instruction. */ 730 const TheISA::PCState pcState() const { return pc; } 731 732 /** Set the PC state of this instruction. */ 733 const void pcState(const TheISA::PCState &val) { pc = val; } 734 735 /** Read the PC of this instruction. */ 736 const Addr instAddr() const { return pc.instAddr(); } 737 738 /** Read the PC of the next instruction. */ 739 const Addr nextInstAddr() const { return pc.nextInstAddr(); } 740 741 /**Read the micro PC of this instruction. */ 742 const Addr microPC() const { return pc.microPC(); } 743 744 bool readPredicate() 745 { 746 return predicate; 747 } 748 749 void setPredicate(bool val) 750 { 751 predicate = val; 752 753 if (traceData) { 754 traceData->setPredicate(val); 755 } 756 } 757 758 /** Sets the ASID. */ 759 void setASID(short addr_space_id) { asid = addr_space_id; } 760 761 /** Sets the thread id. */ 762 void setTid(ThreadID tid) { threadNumber = tid; } 763 764 /** Sets the pointer to the thread state. */ 765 void setThreadState(ImplState *state) { thread = state; } 766 767 /** Returns the thread context. */ 768 ThreadContext *tcBase() { return thread->getTC(); } 769 770 private: 771 /** Instruction effective address. 772 * @todo: Consider if this is necessary or not. 773 */ 774 Addr instEffAddr; 775 776 /** Whether or not the effective address calculation is completed. 777 * @todo: Consider if this is necessary or not. 778 */ 779 bool eaCalcDone; 780 781 /** Is this instruction's memory access uncacheable. */ 782 bool isUncacheable; 783 784 /** Has this instruction generated a memory request. */ 785 bool reqMade; 786 787 public: 788 /** Sets the effective address. */ 789 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 790 791 /** Returns the effective address. */ 792 const Addr &getEA() const { return instEffAddr; } 793 794 /** Returns whether or not the eff. addr. calculation has been completed. */ 795 bool doneEACalc() { return eaCalcDone; } 796 797 /** Returns whether or not the eff. addr. source registers are ready. */ 798 bool eaSrcsReady(); 799 800 /** Whether or not the memory operation is done. */ 801 bool memOpDone; 802 803 /** Is this instruction's memory access uncacheable. */ 804 bool uncacheable() { return isUncacheable; } 805 806 /** Has this instruction generated a memory request. */ 807 bool hasRequest() { return reqMade; } 808 809 public: 810 /** Load queue index. */ 811 int16_t lqIdx; 812 813 /** Store queue index. */ 814 int16_t sqIdx; 815 816 /** Iterator pointing to this BaseDynInst in the list of all insts. */ 817 ListIt instListIt; 818 819 /** Returns iterator to this instruction in the list of all insts. */ 820 ListIt &getInstListIt() { return instListIt; } 821 822 /** Sets iterator for this instruction in the list of all insts. */ 823 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 824 825 public: 826 /** Returns the number of consecutive store conditional failures. */ 827 unsigned readStCondFailures() 828 { return thread->storeCondFailures; } 829 830 /** Sets the number of consecutive store conditional failures. */ 831 void setStCondFailures(unsigned sc_failures) 832 { thread->storeCondFailures = sc_failures; } 833}; 834 835template<class Impl> 836Fault 837BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data, 838 unsigned size, unsigned flags) 839{ 840 reqMade = true; 841 Request *req = NULL; 842 Request *sreqLow = NULL; 843 Request *sreqHigh = NULL; 844 845 if (reqMade && translationStarted) { 846 req = savedReq; 847 sreqLow = savedSreqLow; 848 sreqHigh = savedSreqHigh; 849 } else { 850 req = new Request(asid, addr, size, flags, this->pc.instAddr(), 851 thread->contextId(), threadNumber); 852 853 // Only split the request if the ISA supports unaligned accesses. 854 if (TheISA::HasUnalignedMemAcc) { 855 splitRequest(req, sreqLow, sreqHigh); 856 } 857 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read); 858 } 859 860 if (translationCompleted) { 861 if (fault == NoFault) { 862 effAddr = req->getVaddr(); 863 effSize = size; 864 effAddrValid = true; 865 fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx); 866 } else { 867 // Commit will have to clean up whatever happened. Set this 868 // instruction as executed. 869 this->setExecuted(); 870 } 871 872 if (fault != NoFault) { 873 // Return a fixed value to keep simulation deterministic even 874 // along misspeculated paths. 875 if (data) 876 bzero(data, size); 877 } 878 } 879 880 if (traceData) { 881 traceData->setAddr(addr); 882 } 883 884 return fault; 885} 886 887template<class Impl> 888Fault 889BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, 890 Addr addr, unsigned flags, uint64_t *res) 891{ 892 if (traceData) { 893 traceData->setAddr(addr); 894 } 895 896 reqMade = true; 897 Request *req = NULL; 898 Request *sreqLow = NULL; 899 Request *sreqHigh = NULL; 900 901 if (reqMade && translationStarted) { 902 req = savedReq; 903 sreqLow = savedSreqLow; 904 sreqHigh = savedSreqHigh; 905 } else { 906 req = new Request(asid, addr, size, flags, this->pc.instAddr(), 907 thread->contextId(), threadNumber); 908 909 // Only split the request if the ISA supports unaligned accesses. 910 if (TheISA::HasUnalignedMemAcc) { 911 splitRequest(req, sreqLow, sreqHigh); 912 } 913 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write); 914 } 915 916 if (fault == NoFault && translationCompleted) { 917 effAddr = req->getVaddr(); 918 effSize = size; 919 effAddrValid = true; 920 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx); 921 } 922 923 return fault; 924} 925 926template<class Impl> 927inline void 928BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow, 929 RequestPtr &sreqHigh) 930{ 931 // Check to see if the request crosses the next level block boundary. 932 unsigned block_size = cpu->getDcachePort()->peerBlockSize(); 933 Addr addr = req->getVaddr(); 934 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size); 935 assert(split_addr <= addr || split_addr - addr < block_size); 936 937 // Spans two blocks. 938 if (split_addr > addr) { 939 req->splitOnVaddr(split_addr, sreqLow, sreqHigh); 940 } 941} 942 943template<class Impl> 944inline void 945BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow, 946 RequestPtr sreqHigh, uint64_t *res, 947 BaseTLB::Mode mode) 948{ 949 translationStarted = true; 950 951 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) { 952 WholeTranslationState *state = 953 new WholeTranslationState(req, NULL, res, mode); 954 955 // One translation if the request isn't split. 956 DataTranslation<BaseDynInstPtr> *trans = 957 new DataTranslation<BaseDynInstPtr>(this, state); 958 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode); 959 if (!translationCompleted) { 960 // Save memory requests. 961 savedReq = state->mainReq; 962 savedSreqLow = state->sreqLow; 963 savedSreqHigh = state->sreqHigh; 964 } 965 } else { 966 WholeTranslationState *state = 967 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode); 968 969 // Two translations when the request is split. 970 DataTranslation<BaseDynInstPtr> *stransLow = 971 new DataTranslation<BaseDynInstPtr>(this, state, 0); 972 DataTranslation<BaseDynInstPtr> *stransHigh = 973 new DataTranslation<BaseDynInstPtr>(this, state, 1); 974 975 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode); 976 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode); 977 if (!translationCompleted) { 978 // Save memory requests. 979 savedReq = state->mainReq; 980 savedSreqLow = state->sreqLow; 981 savedSreqHigh = state->sreqHigh; 982 } 983 } 984} 985 986template<class Impl> 987inline void 988BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state) 989{ 990 fault = state->getFault(); 991 992 if (state->isUncacheable()) 993 isUncacheable = true; 994 995 if (fault == NoFault) { 996 physEffAddr = state->getPaddr(); 997 memReqFlags = state->getFlags(); 998 999 if (state->mainReq->isCondSwap()) { 1000 assert(state->res); 1001 state->mainReq->setExtraData(*state->res); 1002 } 1003 1004 } else { 1005 state->deleteReqs(); 1006 } 1007 delete state; 1008 1009 translationCompleted = true; 1010} 1011 1012#endif // __CPU_BASE_DYN_INST_HH__ 1013