base_dyn_inst.hh revision 8484:3c641509bf3e
1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * Copyright (c) 2009 The University of Edinburgh 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 * Timothy M. Jones 43 */ 44 45#ifndef __CPU_BASE_DYN_INST_HH__ 46#define __CPU_BASE_DYN_INST_HH__ 47 48#include <bitset> 49#include <list> 50#include <string> 51 52#include "arch/faults.hh" 53#include "arch/utility.hh" 54#include "base/fast_alloc.hh" 55#include "base/trace.hh" 56#include "config/full_system.hh" 57#include "config/the_isa.hh" 58#include "cpu/o3/comm.hh" 59#include "cpu/exetrace.hh" 60#include "cpu/inst_seq.hh" 61#include "cpu/op_class.hh" 62#include "cpu/static_inst.hh" 63#include "cpu/translation.hh" 64#include "mem/packet.hh" 65#include "sim/byteswap.hh" 66#include "sim/system.hh" 67#include "sim/tlb.hh" 68 69/** 70 * @file 71 * Defines a dynamic instruction context. 72 */ 73 74// Forward declaration. 75class StaticInstPtr; 76 77template <class Impl> 78class BaseDynInst : public FastAlloc, public RefCounted 79{ 80 public: 81 // Typedef for the CPU. 82 typedef typename Impl::CPUType ImplCPU; 83 typedef typename ImplCPU::ImplState ImplState; 84 85 // Logical register index type. 86 typedef TheISA::RegIndex RegIndex; 87 // Integer register type. 88 typedef TheISA::IntReg IntReg; 89 // Floating point register type. 90 typedef TheISA::FloatReg FloatReg; 91 92 // The DynInstPtr type. 93 typedef typename Impl::DynInstPtr DynInstPtr; 94 95 // The list of instructions iterator type. 96 typedef typename std::list<DynInstPtr>::iterator ListIt; 97 98 enum { 99 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 100 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs 101 }; 102 103 /** The StaticInst used by this BaseDynInst. */ 104 StaticInstPtr staticInst; 105 106 //////////////////////////////////////////// 107 // 108 // INSTRUCTION EXECUTION 109 // 110 //////////////////////////////////////////// 111 /** InstRecord that tracks this instructions. */ 112 Trace::InstRecord *traceData; 113 114 void demapPage(Addr vaddr, uint64_t asn) 115 { 116 cpu->demapPage(vaddr, asn); 117 } 118 void demapInstPage(Addr vaddr, uint64_t asn) 119 { 120 cpu->demapPage(vaddr, asn); 121 } 122 void demapDataPage(Addr vaddr, uint64_t asn) 123 { 124 cpu->demapPage(vaddr, asn); 125 } 126 127 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 128 129 Fault writeMem(uint8_t *data, unsigned size, 130 Addr addr, unsigned flags, uint64_t *res); 131 132 /** Splits a request in two if it crosses a dcache block. */ 133 void splitRequest(RequestPtr req, RequestPtr &sreqLow, 134 RequestPtr &sreqHigh); 135 136 /** Initiate a DTB address translation. */ 137 void initiateTranslation(RequestPtr req, RequestPtr sreqLow, 138 RequestPtr sreqHigh, uint64_t *res, 139 BaseTLB::Mode mode); 140 141 /** Finish a DTB address translation. */ 142 void finishTranslation(WholeTranslationState *state); 143 144 /** True if the DTB address translation has started. */ 145 bool translationStarted; 146 147 /** True if the DTB address translation has completed. */ 148 bool translationCompleted; 149 150 /** 151 * Returns true if the DTB address translation is being delayed due to a hw 152 * page table walk. 153 */ 154 bool isTranslationDelayed() const 155 { 156 return (translationStarted && !translationCompleted); 157 } 158 159 /** 160 * Saved memory requests (needed when the DTB address translation is 161 * delayed due to a hw page table walk). 162 */ 163 RequestPtr savedReq; 164 RequestPtr savedSreqLow; 165 RequestPtr savedSreqHigh; 166 167 /** @todo: Consider making this private. */ 168 public: 169 /** The sequence number of the instruction. */ 170 InstSeqNum seqNum; 171 172 enum Status { 173 IqEntry, /// Instruction is in the IQ 174 RobEntry, /// Instruction is in the ROB 175 LsqEntry, /// Instruction is in the LSQ 176 Completed, /// Instruction has completed 177 ResultReady, /// Instruction has its result 178 CanIssue, /// Instruction can issue and execute 179 Issued, /// Instruction has issued 180 Executed, /// Instruction has executed 181 CanCommit, /// Instruction can commit 182 AtCommit, /// Instruction has reached commit 183 Committed, /// Instruction has committed 184 Squashed, /// Instruction is squashed 185 SquashedInIQ, /// Instruction is squashed in the IQ 186 SquashedInLSQ, /// Instruction is squashed in the LSQ 187 SquashedInROB, /// Instruction is squashed in the ROB 188 RecoverInst, /// Is a recover instruction 189 BlockingInst, /// Is a blocking instruction 190 ThreadsyncWait, /// Is a thread synchronization instruction 191 SerializeBefore, /// Needs to serialize on 192 /// instructions ahead of it 193 SerializeAfter, /// Needs to serialize instructions behind it 194 SerializeHandled, /// Serialization has been handled 195 NumStatus 196 }; 197 198 /** The status of this BaseDynInst. Several bits can be set. */ 199 std::bitset<NumStatus> status; 200 201 /** The thread this instruction is from. */ 202 ThreadID threadNumber; 203 204 /** data address space ID, for loads & stores. */ 205 short asid; 206 207 /** How many source registers are ready. */ 208 unsigned readyRegs; 209 210 /** Pointer to the Impl's CPU object. */ 211 ImplCPU *cpu; 212 213 /** Pointer to the thread state. */ 214 ImplState *thread; 215 216 /** The kind of fault this instruction has generated. */ 217 Fault fault; 218 219 /** Pointer to the data for the memory access. */ 220 uint8_t *memData; 221 222 /** The effective virtual address (lds & stores only). */ 223 Addr effAddr; 224 225 /** The size of the request */ 226 Addr effSize; 227 228 /** Is the effective virtual address valid. */ 229 bool effAddrValid; 230 231 /** The effective physical address. */ 232 Addr physEffAddr; 233 234 /** The memory request flags (from translation). */ 235 unsigned memReqFlags; 236 237 union Result { 238 uint64_t integer; 239// float fp; 240 double dbl; 241 }; 242 243 /** The result of the instruction; assumes for now that there's only one 244 * destination register. 245 */ 246 Result instResult; 247 248 /** Records changes to result? */ 249 bool recordResult; 250 251 /** Did this instruction execute, or is it predicated false */ 252 bool predicate; 253 254 protected: 255 /** PC state for this instruction. */ 256 TheISA::PCState pc; 257 258 /** Predicted PC state after this instruction. */ 259 TheISA::PCState predPC; 260 261 /** If this is a branch that was predicted taken */ 262 bool predTaken; 263 264 public: 265 266#ifdef DEBUG 267 void dumpSNList(); 268#endif 269 270 /** Whether or not the source register is ready. 271 * @todo: Not sure this should be here vs the derived class. 272 */ 273 bool _readySrcRegIdx[MaxInstSrcRegs]; 274 275 protected: 276 /** Flattened register index of the destination registers of this 277 * instruction. 278 */ 279 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs]; 280 281 /** Flattened register index of the source registers of this 282 * instruction. 283 */ 284 TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs]; 285 286 /** Physical register index of the destination registers of this 287 * instruction. 288 */ 289 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs]; 290 291 /** Physical register index of the source registers of this 292 * instruction. 293 */ 294 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs]; 295 296 /** Physical register index of the previous producers of the 297 * architected destinations. 298 */ 299 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs]; 300 301 public: 302 303 /** Returns the physical register index of the i'th destination 304 * register. 305 */ 306 PhysRegIndex renamedDestRegIdx(int idx) const 307 { 308 return _destRegIdx[idx]; 309 } 310 311 /** Returns the physical register index of the i'th source register. */ 312 PhysRegIndex renamedSrcRegIdx(int idx) const 313 { 314 return _srcRegIdx[idx]; 315 } 316 317 /** Returns the flattened register index of the i'th destination 318 * register. 319 */ 320 TheISA::RegIndex flattenedDestRegIdx(int idx) const 321 { 322 return _flatDestRegIdx[idx]; 323 } 324 325 /** Returns the flattened register index of the i'th source register */ 326 TheISA::RegIndex flattenedSrcRegIdx(int idx) const 327 { 328 return _flatSrcRegIdx[idx]; 329 } 330 331 /** Returns the physical register index of the previous physical register 332 * that remapped to the same logical register index. 333 */ 334 PhysRegIndex prevDestRegIdx(int idx) const 335 { 336 return _prevDestRegIdx[idx]; 337 } 338 339 /** Renames a destination register to a physical register. Also records 340 * the previous physical register that the logical register mapped to. 341 */ 342 void renameDestReg(int idx, 343 PhysRegIndex renamed_dest, 344 PhysRegIndex previous_rename) 345 { 346 _destRegIdx[idx] = renamed_dest; 347 _prevDestRegIdx[idx] = previous_rename; 348 } 349 350 /** Renames a source logical register to the physical register which 351 * has/will produce that logical register's result. 352 * @todo: add in whether or not the source register is ready. 353 */ 354 void renameSrcReg(int idx, PhysRegIndex renamed_src) 355 { 356 _srcRegIdx[idx] = renamed_src; 357 } 358 359 /** Flattens a source architectural register index into a logical index. 360 */ 361 void flattenSrcReg(int idx, TheISA::RegIndex flattened_src) 362 { 363 _flatSrcRegIdx[idx] = flattened_src; 364 } 365 366 /** Flattens a destination architectural register index into a logical 367 * index. 368 */ 369 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 370 { 371 _flatDestRegIdx[idx] = flattened_dest; 372 } 373 /** BaseDynInst constructor given a binary instruction. 374 * @param staticInst A StaticInstPtr to the underlying instruction. 375 * @param pc The PC state for the instruction. 376 * @param predPC The predicted next PC state for the instruction. 377 * @param seq_num The sequence number of the instruction. 378 * @param cpu Pointer to the instruction's CPU. 379 */ 380 BaseDynInst(StaticInstPtr staticInst, TheISA::PCState pc, 381 TheISA::PCState predPC, InstSeqNum seq_num, ImplCPU *cpu); 382 383 /** BaseDynInst constructor given a StaticInst pointer. 384 * @param _staticInst The StaticInst for this BaseDynInst. 385 */ 386 BaseDynInst(StaticInstPtr &_staticInst); 387 388 /** BaseDynInst destructor. */ 389 ~BaseDynInst(); 390 391 private: 392 /** Function to initialize variables in the constructors. */ 393 void initVars(); 394 395 public: 396 /** Dumps out contents of this BaseDynInst. */ 397 void dump(); 398 399 /** Dumps out contents of this BaseDynInst into given string. */ 400 void dump(std::string &outstring); 401 402 /** Read this CPU's ID. */ 403 int cpuId() { return cpu->cpuId(); } 404 405 /** Read this context's system-wide ID **/ 406 int contextId() { return thread->contextId(); } 407 408 /** Returns the fault type. */ 409 Fault getFault() { return fault; } 410 411 /** Checks whether or not this instruction has had its branch target 412 * calculated yet. For now it is not utilized and is hacked to be 413 * always false. 414 * @todo: Actually use this instruction. 415 */ 416 bool doneTargCalc() { return false; } 417 418 /** Set the predicted target of this current instruction. */ 419 void setPredTarg(const TheISA::PCState &_predPC) 420 { 421 predPC = _predPC; 422 } 423 424 const TheISA::PCState &readPredTarg() { return predPC; } 425 426 /** Returns the predicted PC immediately after the branch. */ 427 Addr predInstAddr() { return predPC.instAddr(); } 428 429 /** Returns the predicted PC two instructions after the branch */ 430 Addr predNextInstAddr() { return predPC.nextInstAddr(); } 431 432 /** Returns the predicted micro PC after the branch */ 433 Addr predMicroPC() { return predPC.microPC(); } 434 435 /** Returns whether the instruction was predicted taken or not. */ 436 bool readPredTaken() 437 { 438 return predTaken; 439 } 440 441 void setPredTaken(bool predicted_taken) 442 { 443 predTaken = predicted_taken; 444 } 445 446 /** Returns whether the instruction mispredicted. */ 447 bool mispredicted() 448 { 449 TheISA::PCState tempPC = pc; 450 TheISA::advancePC(tempPC, staticInst); 451 return !(tempPC == predPC); 452 } 453 454 // 455 // Instruction types. Forward checks to StaticInst object. 456 // 457 bool isNop() const { return staticInst->isNop(); } 458 bool isMemRef() const { return staticInst->isMemRef(); } 459 bool isLoad() const { return staticInst->isLoad(); } 460 bool isStore() const { return staticInst->isStore(); } 461 bool isStoreConditional() const 462 { return staticInst->isStoreConditional(); } 463 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 464 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 465 bool isInteger() const { return staticInst->isInteger(); } 466 bool isFloating() const { return staticInst->isFloating(); } 467 bool isControl() const { return staticInst->isControl(); } 468 bool isCall() const { return staticInst->isCall(); } 469 bool isReturn() const { return staticInst->isReturn(); } 470 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 471 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 472 bool isCondCtrl() const { return staticInst->isCondCtrl(); } 473 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 474 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 475 bool isThreadSync() const { return staticInst->isThreadSync(); } 476 bool isSerializing() const { return staticInst->isSerializing(); } 477 bool isSerializeBefore() const 478 { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 479 bool isSerializeAfter() const 480 { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 481 bool isSquashAfter() const { return staticInst->isSquashAfter(); } 482 bool isMemBarrier() const { return staticInst->isMemBarrier(); } 483 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 484 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 485 bool isQuiesce() const { return staticInst->isQuiesce(); } 486 bool isIprAccess() const { return staticInst->isIprAccess(); } 487 bool isUnverifiable() const { return staticInst->isUnverifiable(); } 488 bool isSyscall() const { return staticInst->isSyscall(); } 489 bool isMacroop() const { return staticInst->isMacroop(); } 490 bool isMicroop() const { return staticInst->isMicroop(); } 491 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 492 bool isLastMicroop() const { return staticInst->isLastMicroop(); } 493 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 494 bool isMicroBranch() const { return staticInst->isMicroBranch(); } 495 496 /** Temporarily sets this instruction as a serialize before instruction. */ 497 void setSerializeBefore() { status.set(SerializeBefore); } 498 499 /** Clears the serializeBefore part of this instruction. */ 500 void clearSerializeBefore() { status.reset(SerializeBefore); } 501 502 /** Checks if this serializeBefore is only temporarily set. */ 503 bool isTempSerializeBefore() { return status[SerializeBefore]; } 504 505 /** Temporarily sets this instruction as a serialize after instruction. */ 506 void setSerializeAfter() { status.set(SerializeAfter); } 507 508 /** Clears the serializeAfter part of this instruction.*/ 509 void clearSerializeAfter() { status.reset(SerializeAfter); } 510 511 /** Checks if this serializeAfter is only temporarily set. */ 512 bool isTempSerializeAfter() { return status[SerializeAfter]; } 513 514 /** Sets the serialization part of this instruction as handled. */ 515 void setSerializeHandled() { status.set(SerializeHandled); } 516 517 /** Checks if the serialization part of this instruction has been 518 * handled. This does not apply to the temporary serializing 519 * state; it only applies to this instruction's own permanent 520 * serializing state. 521 */ 522 bool isSerializeHandled() { return status[SerializeHandled]; } 523 524 /** Returns the opclass of this instruction. */ 525 OpClass opClass() const { return staticInst->opClass(); } 526 527 /** Returns the branch target address. */ 528 TheISA::PCState branchTarget() const 529 { return staticInst->branchTarget(pc); } 530 531 /** Returns the number of source registers. */ 532 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 533 534 /** Returns the number of destination registers. */ 535 int8_t numDestRegs() const { return staticInst->numDestRegs(); } 536 537 // the following are used to track physical register usage 538 // for machines with separate int & FP reg files 539 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 540 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 541 542 /** Returns the logical register index of the i'th destination register. */ 543 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 544 545 /** Returns the logical register index of the i'th source register. */ 546 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 547 548 /** Returns the result of an integer instruction. */ 549 uint64_t readIntResult() { return instResult.integer; } 550 551 /** Returns the result of a floating point instruction. */ 552 float readFloatResult() { return (float)instResult.dbl; } 553 554 /** Returns the result of a floating point (double) instruction. */ 555 double readDoubleResult() { return instResult.dbl; } 556 557 /** Records an integer register being set to a value. */ 558 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 559 { 560 if (recordResult) 561 instResult.integer = val; 562 } 563 564 /** Records an fp register being set to a value. */ 565 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 566 int width) 567 { 568 if (recordResult) { 569 if (width == 32) 570 instResult.dbl = (double)val; 571 else if (width == 64) 572 instResult.dbl = val; 573 else 574 panic("Unsupported width!"); 575 } 576 } 577 578 /** Records an fp register being set to a value. */ 579 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 580 { 581 if (recordResult) 582 instResult.dbl = (double)val; 583 } 584 585 /** Records an fp register being set to an integer value. */ 586 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val, 587 int width) 588 { 589 if (recordResult) 590 instResult.integer = val; 591 } 592 593 /** Records an fp register being set to an integer value. */ 594 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val) 595 { 596 if (recordResult) 597 instResult.integer = val; 598 } 599 600 /** Records that one of the source registers is ready. */ 601 void markSrcRegReady(); 602 603 /** Marks a specific register as ready. */ 604 void markSrcRegReady(RegIndex src_idx); 605 606 /** Returns if a source register is ready. */ 607 bool isReadySrcRegIdx(int idx) const 608 { 609 return this->_readySrcRegIdx[idx]; 610 } 611 612 /** Sets this instruction as completed. */ 613 void setCompleted() { status.set(Completed); } 614 615 /** Returns whether or not this instruction is completed. */ 616 bool isCompleted() const { return status[Completed]; } 617 618 /** Marks the result as ready. */ 619 void setResultReady() { status.set(ResultReady); } 620 621 /** Returns whether or not the result is ready. */ 622 bool isResultReady() const { return status[ResultReady]; } 623 624 /** Sets this instruction as ready to issue. */ 625 void setCanIssue() { status.set(CanIssue); } 626 627 /** Returns whether or not this instruction is ready to issue. */ 628 bool readyToIssue() const { return status[CanIssue]; } 629 630 /** Clears this instruction being able to issue. */ 631 void clearCanIssue() { status.reset(CanIssue); } 632 633 /** Sets this instruction as issued from the IQ. */ 634 void setIssued() { status.set(Issued); } 635 636 /** Returns whether or not this instruction has issued. */ 637 bool isIssued() const { return status[Issued]; } 638 639 /** Clears this instruction as being issued. */ 640 void clearIssued() { status.reset(Issued); } 641 642 /** Sets this instruction as executed. */ 643 void setExecuted() { status.set(Executed); } 644 645 /** Returns whether or not this instruction has executed. */ 646 bool isExecuted() const { return status[Executed]; } 647 648 /** Sets this instruction as ready to commit. */ 649 void setCanCommit() { status.set(CanCommit); } 650 651 /** Clears this instruction as being ready to commit. */ 652 void clearCanCommit() { status.reset(CanCommit); } 653 654 /** Returns whether or not this instruction is ready to commit. */ 655 bool readyToCommit() const { return status[CanCommit]; } 656 657 void setAtCommit() { status.set(AtCommit); } 658 659 bool isAtCommit() { return status[AtCommit]; } 660 661 /** Sets this instruction as committed. */ 662 void setCommitted() { status.set(Committed); } 663 664 /** Returns whether or not this instruction is committed. */ 665 bool isCommitted() const { return status[Committed]; } 666 667 /** Sets this instruction as squashed. */ 668 void setSquashed() { status.set(Squashed); } 669 670 /** Returns whether or not this instruction is squashed. */ 671 bool isSquashed() const { return status[Squashed]; } 672 673 //Instruction Queue Entry 674 //----------------------- 675 /** Sets this instruction as a entry the IQ. */ 676 void setInIQ() { status.set(IqEntry); } 677 678 /** Sets this instruction as a entry the IQ. */ 679 void clearInIQ() { status.reset(IqEntry); } 680 681 /** Returns whether or not this instruction has issued. */ 682 bool isInIQ() const { return status[IqEntry]; } 683 684 /** Sets this instruction as squashed in the IQ. */ 685 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 686 687 /** Returns whether or not this instruction is squashed in the IQ. */ 688 bool isSquashedInIQ() const { return status[SquashedInIQ]; } 689 690 691 //Load / Store Queue Functions 692 //----------------------- 693 /** Sets this instruction as a entry the LSQ. */ 694 void setInLSQ() { status.set(LsqEntry); } 695 696 /** Sets this instruction as a entry the LSQ. */ 697 void removeInLSQ() { status.reset(LsqEntry); } 698 699 /** Returns whether or not this instruction is in the LSQ. */ 700 bool isInLSQ() const { return status[LsqEntry]; } 701 702 /** Sets this instruction as squashed in the LSQ. */ 703 void setSquashedInLSQ() { status.set(SquashedInLSQ);} 704 705 /** Returns whether or not this instruction is squashed in the LSQ. */ 706 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 707 708 709 //Reorder Buffer Functions 710 //----------------------- 711 /** Sets this instruction as a entry the ROB. */ 712 void setInROB() { status.set(RobEntry); } 713 714 /** Sets this instruction as a entry the ROB. */ 715 void clearInROB() { status.reset(RobEntry); } 716 717 /** Returns whether or not this instruction is in the ROB. */ 718 bool isInROB() const { return status[RobEntry]; } 719 720 /** Sets this instruction as squashed in the ROB. */ 721 void setSquashedInROB() { status.set(SquashedInROB); } 722 723 /** Returns whether or not this instruction is squashed in the ROB. */ 724 bool isSquashedInROB() const { return status[SquashedInROB]; } 725 726 /** Read the PC state of this instruction. */ 727 const TheISA::PCState pcState() const { return pc; } 728 729 /** Set the PC state of this instruction. */ 730 const void pcState(const TheISA::PCState &val) { pc = val; } 731 732 /** Read the PC of this instruction. */ 733 const Addr instAddr() const { return pc.instAddr(); } 734 735 /** Read the PC of the next instruction. */ 736 const Addr nextInstAddr() const { return pc.nextInstAddr(); } 737 738 /**Read the micro PC of this instruction. */ 739 const Addr microPC() const { return pc.microPC(); } 740 741 bool readPredicate() 742 { 743 return predicate; 744 } 745 746 void setPredicate(bool val) 747 { 748 predicate = val; 749 750 if (traceData) { 751 traceData->setPredicate(val); 752 } 753 } 754 755 /** Sets the ASID. */ 756 void setASID(short addr_space_id) { asid = addr_space_id; } 757 758 /** Sets the thread id. */ 759 void setTid(ThreadID tid) { threadNumber = tid; } 760 761 /** Sets the pointer to the thread state. */ 762 void setThreadState(ImplState *state) { thread = state; } 763 764 /** Returns the thread context. */ 765 ThreadContext *tcBase() { return thread->getTC(); } 766 767 private: 768 /** Instruction effective address. 769 * @todo: Consider if this is necessary or not. 770 */ 771 Addr instEffAddr; 772 773 /** Whether or not the effective address calculation is completed. 774 * @todo: Consider if this is necessary or not. 775 */ 776 bool eaCalcDone; 777 778 /** Is this instruction's memory access uncacheable. */ 779 bool isUncacheable; 780 781 /** Has this instruction generated a memory request. */ 782 bool reqMade; 783 784 public: 785 /** Sets the effective address. */ 786 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 787 788 /** Returns the effective address. */ 789 const Addr &getEA() const { return instEffAddr; } 790 791 /** Returns whether or not the eff. addr. calculation has been completed. */ 792 bool doneEACalc() { return eaCalcDone; } 793 794 /** Returns whether or not the eff. addr. source registers are ready. */ 795 bool eaSrcsReady(); 796 797 /** Whether or not the memory operation is done. */ 798 bool memOpDone; 799 800 /** Is this instruction's memory access uncacheable. */ 801 bool uncacheable() { return isUncacheable; } 802 803 /** Has this instruction generated a memory request. */ 804 bool hasRequest() { return reqMade; } 805 806 public: 807 /** Load queue index. */ 808 int16_t lqIdx; 809 810 /** Store queue index. */ 811 int16_t sqIdx; 812 813 /** Iterator pointing to this BaseDynInst in the list of all insts. */ 814 ListIt instListIt; 815 816 /** Returns iterator to this instruction in the list of all insts. */ 817 ListIt &getInstListIt() { return instListIt; } 818 819 /** Sets iterator for this instruction in the list of all insts. */ 820 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 821 822 public: 823 /** Returns the number of consecutive store conditional failures. */ 824 unsigned readStCondFailures() 825 { return thread->storeCondFailures; } 826 827 /** Sets the number of consecutive store conditional failures. */ 828 void setStCondFailures(unsigned sc_failures) 829 { thread->storeCondFailures = sc_failures; } 830}; 831 832template<class Impl> 833Fault 834BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data, 835 unsigned size, unsigned flags) 836{ 837 reqMade = true; 838 Request *req = NULL; 839 Request *sreqLow = NULL; 840 Request *sreqHigh = NULL; 841 842 if (reqMade && translationStarted) { 843 req = savedReq; 844 sreqLow = savedSreqLow; 845 sreqHigh = savedSreqHigh; 846 } else { 847 req = new Request(asid, addr, size, flags, this->pc.instAddr(), 848 thread->contextId(), threadNumber); 849 850 // Only split the request if the ISA supports unaligned accesses. 851 if (TheISA::HasUnalignedMemAcc) { 852 splitRequest(req, sreqLow, sreqHigh); 853 } 854 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read); 855 } 856 857 if (translationCompleted) { 858 if (fault == NoFault) { 859 effAddr = req->getVaddr(); 860 effSize = size; 861 effAddrValid = true; 862 fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx); 863 } else { 864 // Commit will have to clean up whatever happened. Set this 865 // instruction as executed. 866 this->setExecuted(); 867 } 868 869 if (fault != NoFault) { 870 // Return a fixed value to keep simulation deterministic even 871 // along misspeculated paths. 872 if (data) 873 bzero(data, size); 874 } 875 } 876 877 if (traceData) { 878 traceData->setAddr(addr); 879 } 880 881 return fault; 882} 883 884template<class Impl> 885Fault 886BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, 887 Addr addr, unsigned flags, uint64_t *res) 888{ 889 if (traceData) { 890 traceData->setAddr(addr); 891 } 892 893 reqMade = true; 894 Request *req = NULL; 895 Request *sreqLow = NULL; 896 Request *sreqHigh = NULL; 897 898 if (reqMade && translationStarted) { 899 req = savedReq; 900 sreqLow = savedSreqLow; 901 sreqHigh = savedSreqHigh; 902 } else { 903 req = new Request(asid, addr, size, flags, this->pc.instAddr(), 904 thread->contextId(), threadNumber); 905 906 // Only split the request if the ISA supports unaligned accesses. 907 if (TheISA::HasUnalignedMemAcc) { 908 splitRequest(req, sreqLow, sreqHigh); 909 } 910 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write); 911 } 912 913 if (fault == NoFault && translationCompleted) { 914 effAddr = req->getVaddr(); 915 effSize = size; 916 effAddrValid = true; 917 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx); 918 } 919 920 return fault; 921} 922 923template<class Impl> 924inline void 925BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow, 926 RequestPtr &sreqHigh) 927{ 928 // Check to see if the request crosses the next level block boundary. 929 unsigned block_size = cpu->getDcachePort()->peerBlockSize(); 930 Addr addr = req->getVaddr(); 931 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size); 932 assert(split_addr <= addr || split_addr - addr < block_size); 933 934 // Spans two blocks. 935 if (split_addr > addr) { 936 req->splitOnVaddr(split_addr, sreqLow, sreqHigh); 937 } 938} 939 940template<class Impl> 941inline void 942BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow, 943 RequestPtr sreqHigh, uint64_t *res, 944 BaseTLB::Mode mode) 945{ 946 translationStarted = true; 947 948 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) { 949 WholeTranslationState *state = 950 new WholeTranslationState(req, NULL, res, mode); 951 952 // One translation if the request isn't split. 953 DataTranslation<BaseDynInst<Impl> > *trans = 954 new DataTranslation<BaseDynInst<Impl> >(this, state); 955 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode); 956 if (!translationCompleted) { 957 // Save memory requests. 958 savedReq = state->mainReq; 959 savedSreqLow = state->sreqLow; 960 savedSreqHigh = state->sreqHigh; 961 } 962 } else { 963 WholeTranslationState *state = 964 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode); 965 966 // Two translations when the request is split. 967 DataTranslation<BaseDynInst<Impl> > *stransLow = 968 new DataTranslation<BaseDynInst<Impl> >(this, state, 0); 969 DataTranslation<BaseDynInst<Impl> > *stransHigh = 970 new DataTranslation<BaseDynInst<Impl> >(this, state, 1); 971 972 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode); 973 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode); 974 if (!translationCompleted) { 975 // Save memory requests. 976 savedReq = state->mainReq; 977 savedSreqLow = state->sreqLow; 978 savedSreqHigh = state->sreqHigh; 979 } 980 } 981} 982 983template<class Impl> 984inline void 985BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state) 986{ 987 fault = state->getFault(); 988 989 if (state->isUncacheable()) 990 isUncacheable = true; 991 992 if (fault == NoFault) { 993 physEffAddr = state->getPaddr(); 994 memReqFlags = state->getFlags(); 995 996 if (state->mainReq->isCondSwap()) { 997 assert(state->res); 998 state->mainReq->setExtraData(*state->res); 999 } 1000 1001 } else { 1002 state->deleteReqs(); 1003 } 1004 delete state; 1005 1006 translationCompleted = true; 1007} 1008 1009#endif // __CPU_BASE_DYN_INST_HH__ 1010