base_dyn_inst.hh revision 7784:e7649570ff3a
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * Copyright (c) 2009 The University of Edinburgh 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution; 13 * neither the name of the copyright holders nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * Authors: Kevin Lim 30 * Timothy M. Jones 31 */ 32 33#ifndef __CPU_BASE_DYN_INST_HH__ 34#define __CPU_BASE_DYN_INST_HH__ 35 36#include <bitset> 37#include <list> 38#include <string> 39 40#include "arch/faults.hh" 41#include "arch/utility.hh" 42#include "base/fast_alloc.hh" 43#include "base/trace.hh" 44#include "config/full_system.hh" 45#include "config/the_isa.hh" 46#include "cpu/o3/comm.hh" 47#include "cpu/exetrace.hh" 48#include "cpu/inst_seq.hh" 49#include "cpu/op_class.hh" 50#include "cpu/static_inst.hh" 51#include "cpu/translation.hh" 52#include "mem/packet.hh" 53#include "sim/byteswap.hh" 54#include "sim/system.hh" 55#include "sim/tlb.hh" 56 57/** 58 * @file 59 * Defines a dynamic instruction context. 60 */ 61 62// Forward declaration. 63class StaticInstPtr; 64 65template <class Impl> 66class BaseDynInst : public FastAlloc, public RefCounted 67{ 68 public: 69 // Typedef for the CPU. 70 typedef typename Impl::CPUType ImplCPU; 71 typedef typename ImplCPU::ImplState ImplState; 72 73 // Logical register index type. 74 typedef TheISA::RegIndex RegIndex; 75 // Integer register type. 76 typedef TheISA::IntReg IntReg; 77 // Floating point register type. 78 typedef TheISA::FloatReg FloatReg; 79 80 // The DynInstPtr type. 81 typedef typename Impl::DynInstPtr DynInstPtr; 82 83 // The list of instructions iterator type. 84 typedef typename std::list<DynInstPtr>::iterator ListIt; 85 86 enum { 87 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 88 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs 89 }; 90 91 /** The StaticInst used by this BaseDynInst. */ 92 StaticInstPtr staticInst; 93 94 //////////////////////////////////////////// 95 // 96 // INSTRUCTION EXECUTION 97 // 98 //////////////////////////////////////////// 99 /** InstRecord that tracks this instructions. */ 100 Trace::InstRecord *traceData; 101 102 void demapPage(Addr vaddr, uint64_t asn) 103 { 104 cpu->demapPage(vaddr, asn); 105 } 106 void demapInstPage(Addr vaddr, uint64_t asn) 107 { 108 cpu->demapPage(vaddr, asn); 109 } 110 void demapDataPage(Addr vaddr, uint64_t asn) 111 { 112 cpu->demapPage(vaddr, asn); 113 } 114 115 /** 116 * Does a read to a given address. 117 * @param addr The address to read. 118 * @param data The read's data is written into this parameter. 119 * @param flags The request's flags. 120 * @return Returns any fault due to the read. 121 */ 122 template <class T> 123 Fault read(Addr addr, T &data, unsigned flags); 124 125 Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags); 126 127 /** 128 * Does a write to a given address. 129 * @param data The data to be written. 130 * @param addr The address to write to. 131 * @param flags The request's flags. 132 * @param res The result of the write (for load locked/store conditionals). 133 * @return Returns any fault due to the write. 134 */ 135 template <class T> 136 Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 137 138 Fault writeBytes(uint8_t *data, unsigned size, 139 Addr addr, unsigned flags, uint64_t *res); 140 141 /** Splits a request in two if it crosses a dcache block. */ 142 void splitRequest(RequestPtr req, RequestPtr &sreqLow, 143 RequestPtr &sreqHigh); 144 145 /** Initiate a DTB address translation. */ 146 void initiateTranslation(RequestPtr req, RequestPtr sreqLow, 147 RequestPtr sreqHigh, uint64_t *res, 148 BaseTLB::Mode mode); 149 150 /** Finish a DTB address translation. */ 151 void finishTranslation(WholeTranslationState *state); 152 153 /** @todo: Consider making this private. */ 154 public: 155 /** The sequence number of the instruction. */ 156 InstSeqNum seqNum; 157 158 enum Status { 159 IqEntry, /// Instruction is in the IQ 160 RobEntry, /// Instruction is in the ROB 161 LsqEntry, /// Instruction is in the LSQ 162 Completed, /// Instruction has completed 163 ResultReady, /// Instruction has its result 164 CanIssue, /// Instruction can issue and execute 165 Issued, /// Instruction has issued 166 Executed, /// Instruction has executed 167 CanCommit, /// Instruction can commit 168 AtCommit, /// Instruction has reached commit 169 Committed, /// Instruction has committed 170 Squashed, /// Instruction is squashed 171 SquashedInIQ, /// Instruction is squashed in the IQ 172 SquashedInLSQ, /// Instruction is squashed in the LSQ 173 SquashedInROB, /// Instruction is squashed in the ROB 174 RecoverInst, /// Is a recover instruction 175 BlockingInst, /// Is a blocking instruction 176 ThreadsyncWait, /// Is a thread synchronization instruction 177 SerializeBefore, /// Needs to serialize on 178 /// instructions ahead of it 179 SerializeAfter, /// Needs to serialize instructions behind it 180 SerializeHandled, /// Serialization has been handled 181 NumStatus 182 }; 183 184 /** The status of this BaseDynInst. Several bits can be set. */ 185 std::bitset<NumStatus> status; 186 187 /** The thread this instruction is from. */ 188 ThreadID threadNumber; 189 190 /** data address space ID, for loads & stores. */ 191 short asid; 192 193 /** How many source registers are ready. */ 194 unsigned readyRegs; 195 196 /** Pointer to the Impl's CPU object. */ 197 ImplCPU *cpu; 198 199 /** Pointer to the thread state. */ 200 ImplState *thread; 201 202 /** The kind of fault this instruction has generated. */ 203 Fault fault; 204 205 /** Pointer to the data for the memory access. */ 206 uint8_t *memData; 207 208 /** The effective virtual address (lds & stores only). */ 209 Addr effAddr; 210 211 /** Is the effective virtual address valid. */ 212 bool effAddrValid; 213 214 /** The effective physical address. */ 215 Addr physEffAddr; 216 217 /** Effective virtual address for a copy source. */ 218 Addr copySrcEffAddr; 219 220 /** Effective physical address for a copy source. */ 221 Addr copySrcPhysEffAddr; 222 223 /** The memory request flags (from translation). */ 224 unsigned memReqFlags; 225 226 union Result { 227 uint64_t integer; 228// float fp; 229 double dbl; 230 }; 231 232 /** The result of the instruction; assumes for now that there's only one 233 * destination register. 234 */ 235 Result instResult; 236 237 /** Records changes to result? */ 238 bool recordResult; 239 240 /** Did this instruction execute, or is it predicated false */ 241 bool predicate; 242 243 protected: 244 /** PC state for this instruction. */ 245 TheISA::PCState pc; 246 247 /** Predicted PC state after this instruction. */ 248 TheISA::PCState predPC; 249 250 /** If this is a branch that was predicted taken */ 251 bool predTaken; 252 253 public: 254 255#ifdef DEBUG 256 void dumpSNList(); 257#endif 258 259 /** Whether or not the source register is ready. 260 * @todo: Not sure this should be here vs the derived class. 261 */ 262 bool _readySrcRegIdx[MaxInstSrcRegs]; 263 264 protected: 265 /** Flattened register index of the destination registers of this 266 * instruction. 267 */ 268 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs]; 269 270 /** Flattened register index of the source registers of this 271 * instruction. 272 */ 273 TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs]; 274 275 /** Physical register index of the destination registers of this 276 * instruction. 277 */ 278 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs]; 279 280 /** Physical register index of the source registers of this 281 * instruction. 282 */ 283 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs]; 284 285 /** Physical register index of the previous producers of the 286 * architected destinations. 287 */ 288 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs]; 289 290 public: 291 292 /** Returns the physical register index of the i'th destination 293 * register. 294 */ 295 PhysRegIndex renamedDestRegIdx(int idx) const 296 { 297 return _destRegIdx[idx]; 298 } 299 300 /** Returns the physical register index of the i'th source register. */ 301 PhysRegIndex renamedSrcRegIdx(int idx) const 302 { 303 return _srcRegIdx[idx]; 304 } 305 306 /** Returns the flattened register index of the i'th destination 307 * register. 308 */ 309 TheISA::RegIndex flattenedDestRegIdx(int idx) const 310 { 311 return _flatDestRegIdx[idx]; 312 } 313 314 /** Returns the flattened register index of the i'th source register */ 315 TheISA::RegIndex flattenedSrcRegIdx(int idx) const 316 { 317 return _flatSrcRegIdx[idx]; 318 } 319 320 /** Returns the physical register index of the previous physical register 321 * that remapped to the same logical register index. 322 */ 323 PhysRegIndex prevDestRegIdx(int idx) const 324 { 325 return _prevDestRegIdx[idx]; 326 } 327 328 /** Renames a destination register to a physical register. Also records 329 * the previous physical register that the logical register mapped to. 330 */ 331 void renameDestReg(int idx, 332 PhysRegIndex renamed_dest, 333 PhysRegIndex previous_rename) 334 { 335 _destRegIdx[idx] = renamed_dest; 336 _prevDestRegIdx[idx] = previous_rename; 337 } 338 339 /** Renames a source logical register to the physical register which 340 * has/will produce that logical register's result. 341 * @todo: add in whether or not the source register is ready. 342 */ 343 void renameSrcReg(int idx, PhysRegIndex renamed_src) 344 { 345 _srcRegIdx[idx] = renamed_src; 346 } 347 348 /** Flattens a source architectural register index into a logical index. 349 */ 350 void flattenSrcReg(int idx, TheISA::RegIndex flattened_src) 351 { 352 _flatSrcRegIdx[idx] = flattened_src; 353 } 354 355 /** Flattens a destination architectural register index into a logical 356 * index. 357 */ 358 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 359 { 360 _flatDestRegIdx[idx] = flattened_dest; 361 } 362 /** BaseDynInst constructor given a binary instruction. 363 * @param staticInst A StaticInstPtr to the underlying instruction. 364 * @param pc The PC state for the instruction. 365 * @param predPC The predicted next PC state for the instruction. 366 * @param seq_num The sequence number of the instruction. 367 * @param cpu Pointer to the instruction's CPU. 368 */ 369 BaseDynInst(StaticInstPtr staticInst, TheISA::PCState pc, 370 TheISA::PCState predPC, InstSeqNum seq_num, ImplCPU *cpu); 371 372 /** BaseDynInst constructor given a binary instruction. 373 * @param inst The binary instruction. 374 * @param _pc The PC state for the instruction. 375 * @param _predPC The predicted next PC state for the instruction. 376 * @param seq_num The sequence number of the instruction. 377 * @param cpu Pointer to the instruction's CPU. 378 */ 379 BaseDynInst(TheISA::ExtMachInst inst, TheISA::PCState pc, 380 TheISA::PCState predPC, InstSeqNum seq_num, ImplCPU *cpu); 381 382 /** BaseDynInst constructor given a StaticInst pointer. 383 * @param _staticInst The StaticInst for this BaseDynInst. 384 */ 385 BaseDynInst(StaticInstPtr &_staticInst); 386 387 /** BaseDynInst destructor. */ 388 ~BaseDynInst(); 389 390 private: 391 /** Function to initialize variables in the constructors. */ 392 void initVars(); 393 394 public: 395 /** Dumps out contents of this BaseDynInst. */ 396 void dump(); 397 398 /** Dumps out contents of this BaseDynInst into given string. */ 399 void dump(std::string &outstring); 400 401 /** Read this CPU's ID. */ 402 int cpuId() { return cpu->cpuId(); } 403 404 /** Read this context's system-wide ID **/ 405 int contextId() { return thread->contextId(); } 406 407 /** Returns the fault type. */ 408 Fault getFault() { return fault; } 409 410 /** Checks whether or not this instruction has had its branch target 411 * calculated yet. For now it is not utilized and is hacked to be 412 * always false. 413 * @todo: Actually use this instruction. 414 */ 415 bool doneTargCalc() { return false; } 416 417 /** Set the predicted target of this current instruction. */ 418 void setPredTarg(const TheISA::PCState &_predPC) 419 { 420 predPC = _predPC; 421 } 422 423 const TheISA::PCState &readPredTarg() { return predPC; } 424 425 /** Returns the predicted PC immediately after the branch. */ 426 Addr predInstAddr() { return predPC.instAddr(); } 427 428 /** Returns the predicted PC two instructions after the branch */ 429 Addr predNextInstAddr() { return predPC.nextInstAddr(); } 430 431 /** Returns the predicted micro PC after the branch */ 432 Addr predMicroPC() { return predPC.microPC(); } 433 434 /** Returns whether the instruction was predicted taken or not. */ 435 bool readPredTaken() 436 { 437 return predTaken; 438 } 439 440 void setPredTaken(bool predicted_taken) 441 { 442 predTaken = predicted_taken; 443 } 444 445 /** Returns whether the instruction mispredicted. */ 446 bool mispredicted() 447 { 448 TheISA::PCState tempPC = pc; 449 TheISA::advancePC(tempPC, staticInst); 450 return !(tempPC == predPC); 451 } 452 453 // 454 // Instruction types. Forward checks to StaticInst object. 455 // 456 bool isNop() const { return staticInst->isNop(); } 457 bool isMemRef() const { return staticInst->isMemRef(); } 458 bool isLoad() const { return staticInst->isLoad(); } 459 bool isStore() const { return staticInst->isStore(); } 460 bool isStoreConditional() const 461 { return staticInst->isStoreConditional(); } 462 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 463 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 464 bool isCopy() const { return staticInst->isCopy(); } 465 bool isInteger() const { return staticInst->isInteger(); } 466 bool isFloating() const { return staticInst->isFloating(); } 467 bool isControl() const { return staticInst->isControl(); } 468 bool isCall() const { return staticInst->isCall(); } 469 bool isReturn() const { return staticInst->isReturn(); } 470 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 471 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 472 bool isCondCtrl() const { return staticInst->isCondCtrl(); } 473 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 474 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 475 bool isThreadSync() const { return staticInst->isThreadSync(); } 476 bool isSerializing() const { return staticInst->isSerializing(); } 477 bool isSerializeBefore() const 478 { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 479 bool isSerializeAfter() const 480 { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 481 bool isSquashAfter() const { return staticInst->isSquashAfter(); } 482 bool isMemBarrier() const { return staticInst->isMemBarrier(); } 483 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 484 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 485 bool isQuiesce() const { return staticInst->isQuiesce(); } 486 bool isIprAccess() const { return staticInst->isIprAccess(); } 487 bool isUnverifiable() const { return staticInst->isUnverifiable(); } 488 bool isSyscall() const { return staticInst->isSyscall(); } 489 bool isMacroop() const { return staticInst->isMacroop(); } 490 bool isMicroop() const { return staticInst->isMicroop(); } 491 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 492 bool isLastMicroop() const { return staticInst->isLastMicroop(); } 493 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 494 bool isMicroBranch() const { return staticInst->isMicroBranch(); } 495 496 /** Temporarily sets this instruction as a serialize before instruction. */ 497 void setSerializeBefore() { status.set(SerializeBefore); } 498 499 /** Clears the serializeBefore part of this instruction. */ 500 void clearSerializeBefore() { status.reset(SerializeBefore); } 501 502 /** Checks if this serializeBefore is only temporarily set. */ 503 bool isTempSerializeBefore() { return status[SerializeBefore]; } 504 505 /** Temporarily sets this instruction as a serialize after instruction. */ 506 void setSerializeAfter() { status.set(SerializeAfter); } 507 508 /** Clears the serializeAfter part of this instruction.*/ 509 void clearSerializeAfter() { status.reset(SerializeAfter); } 510 511 /** Checks if this serializeAfter is only temporarily set. */ 512 bool isTempSerializeAfter() { return status[SerializeAfter]; } 513 514 /** Sets the serialization part of this instruction as handled. */ 515 void setSerializeHandled() { status.set(SerializeHandled); } 516 517 /** Checks if the serialization part of this instruction has been 518 * handled. This does not apply to the temporary serializing 519 * state; it only applies to this instruction's own permanent 520 * serializing state. 521 */ 522 bool isSerializeHandled() { return status[SerializeHandled]; } 523 524 /** Returns the opclass of this instruction. */ 525 OpClass opClass() const { return staticInst->opClass(); } 526 527 /** Returns the branch target address. */ 528 TheISA::PCState branchTarget() const 529 { return staticInst->branchTarget(pc); } 530 531 /** Returns the number of source registers. */ 532 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 533 534 /** Returns the number of destination registers. */ 535 int8_t numDestRegs() const { return staticInst->numDestRegs(); } 536 537 // the following are used to track physical register usage 538 // for machines with separate int & FP reg files 539 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 540 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 541 542 /** Returns the logical register index of the i'th destination register. */ 543 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 544 545 /** Returns the logical register index of the i'th source register. */ 546 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 547 548 /** Returns the result of an integer instruction. */ 549 uint64_t readIntResult() { return instResult.integer; } 550 551 /** Returns the result of a floating point instruction. */ 552 float readFloatResult() { return (float)instResult.dbl; } 553 554 /** Returns the result of a floating point (double) instruction. */ 555 double readDoubleResult() { return instResult.dbl; } 556 557 /** Records an integer register being set to a value. */ 558 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 559 { 560 if (recordResult) 561 instResult.integer = val; 562 } 563 564 /** Records an fp register being set to a value. */ 565 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 566 int width) 567 { 568 if (recordResult) { 569 if (width == 32) 570 instResult.dbl = (double)val; 571 else if (width == 64) 572 instResult.dbl = val; 573 else 574 panic("Unsupported width!"); 575 } 576 } 577 578 /** Records an fp register being set to a value. */ 579 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 580 { 581 if (recordResult) 582 instResult.dbl = (double)val; 583 } 584 585 /** Records an fp register being set to an integer value. */ 586 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val, 587 int width) 588 { 589 if (recordResult) 590 instResult.integer = val; 591 } 592 593 /** Records an fp register being set to an integer value. */ 594 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val) 595 { 596 if (recordResult) 597 instResult.integer = val; 598 } 599 600 /** Records that one of the source registers is ready. */ 601 void markSrcRegReady(); 602 603 /** Marks a specific register as ready. */ 604 void markSrcRegReady(RegIndex src_idx); 605 606 /** Returns if a source register is ready. */ 607 bool isReadySrcRegIdx(int idx) const 608 { 609 return this->_readySrcRegIdx[idx]; 610 } 611 612 /** Sets this instruction as completed. */ 613 void setCompleted() { status.set(Completed); } 614 615 /** Returns whether or not this instruction is completed. */ 616 bool isCompleted() const { return status[Completed]; } 617 618 /** Marks the result as ready. */ 619 void setResultReady() { status.set(ResultReady); } 620 621 /** Returns whether or not the result is ready. */ 622 bool isResultReady() const { return status[ResultReady]; } 623 624 /** Sets this instruction as ready to issue. */ 625 void setCanIssue() { status.set(CanIssue); } 626 627 /** Returns whether or not this instruction is ready to issue. */ 628 bool readyToIssue() const { return status[CanIssue]; } 629 630 /** Clears this instruction being able to issue. */ 631 void clearCanIssue() { status.reset(CanIssue); } 632 633 /** Sets this instruction as issued from the IQ. */ 634 void setIssued() { status.set(Issued); } 635 636 /** Returns whether or not this instruction has issued. */ 637 bool isIssued() const { return status[Issued]; } 638 639 /** Clears this instruction as being issued. */ 640 void clearIssued() { status.reset(Issued); } 641 642 /** Sets this instruction as executed. */ 643 void setExecuted() { status.set(Executed); } 644 645 /** Returns whether or not this instruction has executed. */ 646 bool isExecuted() const { return status[Executed]; } 647 648 /** Sets this instruction as ready to commit. */ 649 void setCanCommit() { status.set(CanCommit); } 650 651 /** Clears this instruction as being ready to commit. */ 652 void clearCanCommit() { status.reset(CanCommit); } 653 654 /** Returns whether or not this instruction is ready to commit. */ 655 bool readyToCommit() const { return status[CanCommit]; } 656 657 void setAtCommit() { status.set(AtCommit); } 658 659 bool isAtCommit() { return status[AtCommit]; } 660 661 /** Sets this instruction as committed. */ 662 void setCommitted() { status.set(Committed); } 663 664 /** Returns whether or not this instruction is committed. */ 665 bool isCommitted() const { return status[Committed]; } 666 667 /** Sets this instruction as squashed. */ 668 void setSquashed() { status.set(Squashed); } 669 670 /** Returns whether or not this instruction is squashed. */ 671 bool isSquashed() const { return status[Squashed]; } 672 673 //Instruction Queue Entry 674 //----------------------- 675 /** Sets this instruction as a entry the IQ. */ 676 void setInIQ() { status.set(IqEntry); } 677 678 /** Sets this instruction as a entry the IQ. */ 679 void clearInIQ() { status.reset(IqEntry); } 680 681 /** Returns whether or not this instruction has issued. */ 682 bool isInIQ() const { return status[IqEntry]; } 683 684 /** Sets this instruction as squashed in the IQ. */ 685 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 686 687 /** Returns whether or not this instruction is squashed in the IQ. */ 688 bool isSquashedInIQ() const { return status[SquashedInIQ]; } 689 690 691 //Load / Store Queue Functions 692 //----------------------- 693 /** Sets this instruction as a entry the LSQ. */ 694 void setInLSQ() { status.set(LsqEntry); } 695 696 /** Sets this instruction as a entry the LSQ. */ 697 void removeInLSQ() { status.reset(LsqEntry); } 698 699 /** Returns whether or not this instruction is in the LSQ. */ 700 bool isInLSQ() const { return status[LsqEntry]; } 701 702 /** Sets this instruction as squashed in the LSQ. */ 703 void setSquashedInLSQ() { status.set(SquashedInLSQ);} 704 705 /** Returns whether or not this instruction is squashed in the LSQ. */ 706 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 707 708 709 //Reorder Buffer Functions 710 //----------------------- 711 /** Sets this instruction as a entry the ROB. */ 712 void setInROB() { status.set(RobEntry); } 713 714 /** Sets this instruction as a entry the ROB. */ 715 void clearInROB() { status.reset(RobEntry); } 716 717 /** Returns whether or not this instruction is in the ROB. */ 718 bool isInROB() const { return status[RobEntry]; } 719 720 /** Sets this instruction as squashed in the ROB. */ 721 void setSquashedInROB() { status.set(SquashedInROB); } 722 723 /** Returns whether or not this instruction is squashed in the ROB. */ 724 bool isSquashedInROB() const { return status[SquashedInROB]; } 725 726 /** Read the PC state of this instruction. */ 727 const TheISA::PCState pcState() const { return pc; } 728 729 /** Set the PC state of this instruction. */ 730 const void pcState(const TheISA::PCState &val) { pc = val; } 731 732 /** Read the PC of this instruction. */ 733 const Addr instAddr() const { return pc.instAddr(); } 734 735 /** Read the PC of the next instruction. */ 736 const Addr nextInstAddr() const { return pc.nextInstAddr(); } 737 738 /**Read the micro PC of this instruction. */ 739 const Addr microPC() const { return pc.microPC(); } 740 741 bool readPredicate() 742 { 743 return predicate; 744 } 745 746 void setPredicate(bool val) 747 { 748 predicate = val; 749 750 if (traceData) { 751 traceData->setPredicate(val); 752 } 753 } 754 755 /** Sets the ASID. */ 756 void setASID(short addr_space_id) { asid = addr_space_id; } 757 758 /** Sets the thread id. */ 759 void setTid(ThreadID tid) { threadNumber = tid; } 760 761 /** Sets the pointer to the thread state. */ 762 void setThreadState(ImplState *state) { thread = state; } 763 764 /** Returns the thread context. */ 765 ThreadContext *tcBase() { return thread->getTC(); } 766 767 private: 768 /** Instruction effective address. 769 * @todo: Consider if this is necessary or not. 770 */ 771 Addr instEffAddr; 772 773 /** Whether or not the effective address calculation is completed. 774 * @todo: Consider if this is necessary or not. 775 */ 776 bool eaCalcDone; 777 778 /** Is this instruction's memory access uncacheable. */ 779 bool isUncacheable; 780 781 /** Has this instruction generated a memory request. */ 782 bool reqMade; 783 784 public: 785 /** Sets the effective address. */ 786 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 787 788 /** Returns the effective address. */ 789 const Addr &getEA() const { return instEffAddr; } 790 791 /** Returns whether or not the eff. addr. calculation has been completed. */ 792 bool doneEACalc() { return eaCalcDone; } 793 794 /** Returns whether or not the eff. addr. source registers are ready. */ 795 bool eaSrcsReady(); 796 797 /** Whether or not the memory operation is done. */ 798 bool memOpDone; 799 800 /** Is this instruction's memory access uncacheable. */ 801 bool uncacheable() { return isUncacheable; } 802 803 /** Has this instruction generated a memory request. */ 804 bool hasRequest() { return reqMade; } 805 806 public: 807 /** Load queue index. */ 808 int16_t lqIdx; 809 810 /** Store queue index. */ 811 int16_t sqIdx; 812 813 /** Iterator pointing to this BaseDynInst in the list of all insts. */ 814 ListIt instListIt; 815 816 /** Returns iterator to this instruction in the list of all insts. */ 817 ListIt &getInstListIt() { return instListIt; } 818 819 /** Sets iterator for this instruction in the list of all insts. */ 820 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 821 822 public: 823 /** Returns the number of consecutive store conditional failures. */ 824 unsigned readStCondFailures() 825 { return thread->storeCondFailures; } 826 827 /** Sets the number of consecutive store conditional failures. */ 828 void setStCondFailures(unsigned sc_failures) 829 { thread->storeCondFailures = sc_failures; } 830}; 831 832template<class Impl> 833Fault 834BaseDynInst<Impl>::readBytes(Addr addr, uint8_t *data, 835 unsigned size, unsigned flags) 836{ 837 reqMade = true; 838 Request *req = new Request(asid, addr, size, flags, this->pc.instAddr(), 839 thread->contextId(), threadNumber); 840 841 Request *sreqLow = NULL; 842 Request *sreqHigh = NULL; 843 844 // Only split the request if the ISA supports unaligned accesses. 845 if (TheISA::HasUnalignedMemAcc) { 846 splitRequest(req, sreqLow, sreqHigh); 847 } 848 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read); 849 850 if (fault == NoFault) { 851 effAddr = req->getVaddr(); 852 effAddrValid = true; 853 fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx); 854 } else { 855 // Commit will have to clean up whatever happened. Set this 856 // instruction as executed. 857 this->setExecuted(); 858 } 859 860 if (fault != NoFault) { 861 // Return a fixed value to keep simulation deterministic even 862 // along misspeculated paths. 863 if (data) 864 bzero(data, size); 865 } 866 867 if (traceData) { 868 traceData->setAddr(addr); 869 } 870 871 return fault; 872} 873 874template<class Impl> 875template<class T> 876inline Fault 877BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) 878{ 879 Fault fault = readBytes(addr, (uint8_t *)&data, sizeof(T), flags); 880 881 data = TheISA::gtoh(data); 882 883 if (traceData) { 884 traceData->setData(data); 885 } 886 887 return fault; 888} 889 890template<class Impl> 891Fault 892BaseDynInst<Impl>::writeBytes(uint8_t *data, unsigned size, 893 Addr addr, unsigned flags, uint64_t *res) 894{ 895 if (traceData) { 896 traceData->setAddr(addr); 897 } 898 899 reqMade = true; 900 Request *req = new Request(asid, addr, size, flags, this->pc.instAddr(), 901 thread->contextId(), threadNumber); 902 903 Request *sreqLow = NULL; 904 Request *sreqHigh = NULL; 905 906 // Only split the request if the ISA supports unaligned accesses. 907 if (TheISA::HasUnalignedMemAcc) { 908 splitRequest(req, sreqLow, sreqHigh); 909 } 910 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write); 911 912 if (fault == NoFault) { 913 effAddr = req->getVaddr(); 914 effAddrValid = true; 915 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx); 916 } 917 918 return fault; 919} 920 921template<class Impl> 922template<class T> 923inline Fault 924BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) 925{ 926 if (traceData) { 927 traceData->setData(data); 928 } 929 data = TheISA::htog(data); 930 return writeBytes((uint8_t *)&data, sizeof(T), addr, flags, res); 931} 932 933template<class Impl> 934inline void 935BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow, 936 RequestPtr &sreqHigh) 937{ 938 // Check to see if the request crosses the next level block boundary. 939 unsigned block_size = cpu->getDcachePort()->peerBlockSize(); 940 Addr addr = req->getVaddr(); 941 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size); 942 assert(split_addr <= addr || split_addr - addr < block_size); 943 944 // Spans two blocks. 945 if (split_addr > addr) { 946 req->splitOnVaddr(split_addr, sreqLow, sreqHigh); 947 } 948} 949 950template<class Impl> 951inline void 952BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow, 953 RequestPtr sreqHigh, uint64_t *res, 954 BaseTLB::Mode mode) 955{ 956 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) { 957 WholeTranslationState *state = 958 new WholeTranslationState(req, NULL, res, mode); 959 960 // One translation if the request isn't split. 961 DataTranslation<BaseDynInst<Impl> > *trans = 962 new DataTranslation<BaseDynInst<Impl> >(this, state); 963 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode); 964 } else { 965 WholeTranslationState *state = 966 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode); 967 968 // Two translations when the request is split. 969 DataTranslation<BaseDynInst<Impl> > *stransLow = 970 new DataTranslation<BaseDynInst<Impl> >(this, state, 0); 971 DataTranslation<BaseDynInst<Impl> > *stransHigh = 972 new DataTranslation<BaseDynInst<Impl> >(this, state, 1); 973 974 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode); 975 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode); 976 } 977} 978 979template<class Impl> 980inline void 981BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state) 982{ 983 fault = state->getFault(); 984 985 if (state->isUncacheable()) 986 isUncacheable = true; 987 988 if (fault == NoFault) { 989 physEffAddr = state->getPaddr(); 990 memReqFlags = state->getFlags(); 991 992 if (state->mainReq->isCondSwap()) { 993 assert(state->res); 994 state->mainReq->setExtraData(*state->res); 995 } 996 997 } else { 998 state->deleteReqs(); 999 } 1000 delete state; 1001} 1002 1003#endif // __CPU_BASE_DYN_INST_HH__ 1004