base_dyn_inst.hh revision 7725:00ea9430643b
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * Copyright (c) 2009 The University of Edinburgh
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Kevin Lim
30 *          Timothy M. Jones
31 */
32
33#ifndef __CPU_BASE_DYN_INST_HH__
34#define __CPU_BASE_DYN_INST_HH__
35
36#include <bitset>
37#include <list>
38#include <string>
39
40#include "arch/faults.hh"
41#include "arch/utility.hh"
42#include "base/fast_alloc.hh"
43#include "base/trace.hh"
44#include "config/full_system.hh"
45#include "config/the_isa.hh"
46#include "cpu/o3/comm.hh"
47#include "cpu/exetrace.hh"
48#include "cpu/inst_seq.hh"
49#include "cpu/op_class.hh"
50#include "cpu/static_inst.hh"
51#include "cpu/translation.hh"
52#include "mem/packet.hh"
53#include "sim/byteswap.hh"
54#include "sim/system.hh"
55#include "sim/tlb.hh"
56
57/**
58 * @file
59 * Defines a dynamic instruction context.
60 */
61
62// Forward declaration.
63class StaticInstPtr;
64
65template <class Impl>
66class BaseDynInst : public FastAlloc, public RefCounted
67{
68  public:
69    // Typedef for the CPU.
70    typedef typename Impl::CPUType ImplCPU;
71    typedef typename ImplCPU::ImplState ImplState;
72
73    // Logical register index type.
74    typedef TheISA::RegIndex RegIndex;
75    // Integer register type.
76    typedef TheISA::IntReg IntReg;
77    // Floating point register type.
78    typedef TheISA::FloatReg FloatReg;
79
80    // The DynInstPtr type.
81    typedef typename Impl::DynInstPtr DynInstPtr;
82
83    // The list of instructions iterator type.
84    typedef typename std::list<DynInstPtr>::iterator ListIt;
85
86    enum {
87        MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        /// Max source regs
88        MaxInstDestRegs = TheISA::MaxInstDestRegs,      /// Max dest regs
89    };
90
91    /** The StaticInst used by this BaseDynInst. */
92    StaticInstPtr staticInst;
93
94    ////////////////////////////////////////////
95    //
96    // INSTRUCTION EXECUTION
97    //
98    ////////////////////////////////////////////
99    /** InstRecord that tracks this instructions. */
100    Trace::InstRecord *traceData;
101
102    void demapPage(Addr vaddr, uint64_t asn)
103    {
104        cpu->demapPage(vaddr, asn);
105    }
106    void demapInstPage(Addr vaddr, uint64_t asn)
107    {
108        cpu->demapPage(vaddr, asn);
109    }
110    void demapDataPage(Addr vaddr, uint64_t asn)
111    {
112        cpu->demapPage(vaddr, asn);
113    }
114
115    /**
116     * Does a read to a given address.
117     * @param addr The address to read.
118     * @param data The read's data is written into this parameter.
119     * @param flags The request's flags.
120     * @return Returns any fault due to the read.
121     */
122    template <class T>
123    Fault read(Addr addr, T &data, unsigned flags);
124
125    Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
126
127    /**
128     * Does a write to a given address.
129     * @param data The data to be written.
130     * @param addr The address to write to.
131     * @param flags The request's flags.
132     * @param res The result of the write (for load locked/store conditionals).
133     * @return Returns any fault due to the write.
134     */
135    template <class T>
136    Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
137
138    Fault writeBytes(uint8_t *data, unsigned size,
139                     Addr addr, unsigned flags, uint64_t *res);
140
141    /** Splits a request in two if it crosses a dcache block. */
142    void splitRequest(RequestPtr req, RequestPtr &sreqLow,
143                      RequestPtr &sreqHigh);
144
145    /** Initiate a DTB address translation. */
146    void initiateTranslation(RequestPtr req, RequestPtr sreqLow,
147                             RequestPtr sreqHigh, uint64_t *res,
148                             BaseTLB::Mode mode);
149
150    /** Finish a DTB address translation. */
151    void finishTranslation(WholeTranslationState *state);
152
153    /** @todo: Consider making this private. */
154  public:
155    /** The sequence number of the instruction. */
156    InstSeqNum seqNum;
157
158    enum Status {
159        IqEntry,                 /// Instruction is in the IQ
160        RobEntry,                /// Instruction is in the ROB
161        LsqEntry,                /// Instruction is in the LSQ
162        Completed,               /// Instruction has completed
163        ResultReady,             /// Instruction has its result
164        CanIssue,                /// Instruction can issue and execute
165        Issued,                  /// Instruction has issued
166        Executed,                /// Instruction has executed
167        CanCommit,               /// Instruction can commit
168        AtCommit,                /// Instruction has reached commit
169        Committed,               /// Instruction has committed
170        Squashed,                /// Instruction is squashed
171        SquashedInIQ,            /// Instruction is squashed in the IQ
172        SquashedInLSQ,           /// Instruction is squashed in the LSQ
173        SquashedInROB,           /// Instruction is squashed in the ROB
174        RecoverInst,             /// Is a recover instruction
175        BlockingInst,            /// Is a blocking instruction
176        ThreadsyncWait,          /// Is a thread synchronization instruction
177        SerializeBefore,         /// Needs to serialize on
178                                 /// instructions ahead of it
179        SerializeAfter,          /// Needs to serialize instructions behind it
180        SerializeHandled,        /// Serialization has been handled
181        NumStatus
182    };
183
184    /** The status of this BaseDynInst.  Several bits can be set. */
185    std::bitset<NumStatus> status;
186
187    /** The thread this instruction is from. */
188    ThreadID threadNumber;
189
190    /** data address space ID, for loads & stores. */
191    short asid;
192
193    /** How many source registers are ready. */
194    unsigned readyRegs;
195
196    /** Pointer to the Impl's CPU object. */
197    ImplCPU *cpu;
198
199    /** Pointer to the thread state. */
200    ImplState *thread;
201
202    /** The kind of fault this instruction has generated. */
203    Fault fault;
204
205    /** Pointer to the data for the memory access. */
206    uint8_t *memData;
207
208    /** The effective virtual address (lds & stores only). */
209    Addr effAddr;
210
211    /** Is the effective virtual address valid. */
212    bool effAddrValid;
213
214    /** The effective physical address. */
215    Addr physEffAddr;
216
217    /** Effective virtual address for a copy source. */
218    Addr copySrcEffAddr;
219
220    /** Effective physical address for a copy source. */
221    Addr copySrcPhysEffAddr;
222
223    /** The memory request flags (from translation). */
224    unsigned memReqFlags;
225
226    union Result {
227        uint64_t integer;
228//        float fp;
229        double dbl;
230    };
231
232    /** The result of the instruction; assumes for now that there's only one
233     *  destination register.
234     */
235    Result instResult;
236
237    /** Records changes to result? */
238    bool recordResult;
239
240    /** Did this instruction execute, or is it predicated false */
241    bool predicate;
242
243  protected:
244    /** PC state for this instruction. */
245    TheISA::PCState pc;
246
247    /** Predicted PC state after this instruction. */
248    TheISA::PCState predPC;
249
250    /** If this is a branch that was predicted taken */
251    bool predTaken;
252
253  public:
254
255#ifdef DEBUG
256    void dumpSNList();
257#endif
258
259    /** Whether or not the source register is ready.
260     *  @todo: Not sure this should be here vs the derived class.
261     */
262    bool _readySrcRegIdx[MaxInstSrcRegs];
263
264  protected:
265    /** Flattened register index of the destination registers of this
266     *  instruction.
267     */
268    TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
269
270    /** Flattened register index of the source registers of this
271     *  instruction.
272     */
273    TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs];
274
275    /** Physical register index of the destination registers of this
276     *  instruction.
277     */
278    PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs];
279
280    /** Physical register index of the source registers of this
281     *  instruction.
282     */
283    PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs];
284
285    /** Physical register index of the previous producers of the
286     *  architected destinations.
287     */
288    PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs];
289
290  public:
291
292    /** Returns the physical register index of the i'th destination
293     *  register.
294     */
295    PhysRegIndex renamedDestRegIdx(int idx) const
296    {
297        return _destRegIdx[idx];
298    }
299
300    /** Returns the physical register index of the i'th source register. */
301    PhysRegIndex renamedSrcRegIdx(int idx) const
302    {
303        return _srcRegIdx[idx];
304    }
305
306    /** Returns the flattened register index of the i'th destination
307     *  register.
308     */
309    TheISA::RegIndex flattenedDestRegIdx(int idx) const
310    {
311        return _flatDestRegIdx[idx];
312    }
313
314    /** Returns the flattened register index of the i'th source register */
315    TheISA::RegIndex flattenedSrcRegIdx(int idx) const
316    {
317        return _flatSrcRegIdx[idx];
318    }
319
320    /** Returns the physical register index of the previous physical register
321     *  that remapped to the same logical register index.
322     */
323    PhysRegIndex prevDestRegIdx(int idx) const
324    {
325        return _prevDestRegIdx[idx];
326    }
327
328    /** Renames a destination register to a physical register.  Also records
329     *  the previous physical register that the logical register mapped to.
330     */
331    void renameDestReg(int idx,
332                       PhysRegIndex renamed_dest,
333                       PhysRegIndex previous_rename)
334    {
335        _destRegIdx[idx] = renamed_dest;
336        _prevDestRegIdx[idx] = previous_rename;
337    }
338
339    /** Renames a source logical register to the physical register which
340     *  has/will produce that logical register's result.
341     *  @todo: add in whether or not the source register is ready.
342     */
343    void renameSrcReg(int idx, PhysRegIndex renamed_src)
344    {
345        _srcRegIdx[idx] = renamed_src;
346    }
347
348    /** Flattens a source architectural register index into a logical index.
349     */
350    void flattenSrcReg(int idx, TheISA::RegIndex flattened_src)
351    {
352        _flatSrcRegIdx[idx] = flattened_src;
353    }
354
355    /** Flattens a destination architectural register index into a logical
356     * index.
357     */
358    void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
359    {
360        _flatDestRegIdx[idx] = flattened_dest;
361    }
362    /** BaseDynInst constructor given a binary instruction.
363     *  @param staticInst A StaticInstPtr to the underlying instruction.
364     *  @param pc The PC state for the instruction.
365     *  @param predPC The predicted next PC state for the instruction.
366     *  @param seq_num The sequence number of the instruction.
367     *  @param cpu Pointer to the instruction's CPU.
368     */
369    BaseDynInst(StaticInstPtr staticInst, TheISA::PCState pc,
370                TheISA::PCState predPC, InstSeqNum seq_num, ImplCPU *cpu);
371
372    /** BaseDynInst constructor given a binary instruction.
373     *  @param inst The binary instruction.
374     *  @param _pc The PC state for the instruction.
375     *  @param _predPC The predicted next PC state for the instruction.
376     *  @param seq_num The sequence number of the instruction.
377     *  @param cpu Pointer to the instruction's CPU.
378     */
379    BaseDynInst(TheISA::ExtMachInst inst, TheISA::PCState pc,
380                TheISA::PCState predPC, InstSeqNum seq_num, ImplCPU *cpu);
381
382    /** BaseDynInst constructor given a StaticInst pointer.
383     *  @param _staticInst The StaticInst for this BaseDynInst.
384     */
385    BaseDynInst(StaticInstPtr &_staticInst);
386
387    /** BaseDynInst destructor. */
388    ~BaseDynInst();
389
390  private:
391    /** Function to initialize variables in the constructors. */
392    void initVars();
393
394  public:
395    /** Dumps out contents of this BaseDynInst. */
396    void dump();
397
398    /** Dumps out contents of this BaseDynInst into given string. */
399    void dump(std::string &outstring);
400
401    /** Read this CPU's ID. */
402    int cpuId() { return cpu->cpuId(); }
403
404    /** Read this context's system-wide ID **/
405    int contextId() { return thread->contextId(); }
406
407    /** Returns the fault type. */
408    Fault getFault() { return fault; }
409
410    /** Checks whether or not this instruction has had its branch target
411     *  calculated yet.  For now it is not utilized and is hacked to be
412     *  always false.
413     *  @todo: Actually use this instruction.
414     */
415    bool doneTargCalc() { return false; }
416
417    /** Set the predicted target of this current instruction. */
418    void setPredTarg(const TheISA::PCState &_predPC)
419    {
420        predPC = _predPC;
421    }
422
423    const TheISA::PCState &readPredTarg() { return predPC; }
424
425    /** Returns the predicted PC immediately after the branch. */
426    Addr predInstAddr() { return predPC.instAddr(); }
427
428    /** Returns the predicted PC two instructions after the branch */
429    Addr predNextInstAddr() { return predPC.nextInstAddr(); }
430
431    /** Returns the predicted micro PC after the branch */
432    Addr predMicroPC() { return predPC.microPC(); }
433
434    /** Returns whether the instruction was predicted taken or not. */
435    bool readPredTaken()
436    {
437        return predTaken;
438    }
439
440    void setPredTaken(bool predicted_taken)
441    {
442        predTaken = predicted_taken;
443    }
444
445    /** Returns whether the instruction mispredicted. */
446    bool mispredicted()
447    {
448        TheISA::PCState tempPC = pc;
449        TheISA::advancePC(tempPC, staticInst);
450        return !(tempPC == predPC);
451    }
452
453    //
454    //  Instruction types.  Forward checks to StaticInst object.
455    //
456    bool isNop()          const { return staticInst->isNop(); }
457    bool isMemRef()       const { return staticInst->isMemRef(); }
458    bool isLoad()         const { return staticInst->isLoad(); }
459    bool isStore()        const { return staticInst->isStore(); }
460    bool isStoreConditional() const
461    { return staticInst->isStoreConditional(); }
462    bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
463    bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
464    bool isCopy()         const { return staticInst->isCopy(); }
465    bool isInteger()      const { return staticInst->isInteger(); }
466    bool isFloating()     const { return staticInst->isFloating(); }
467    bool isControl()      const { return staticInst->isControl(); }
468    bool isCall()         const { return staticInst->isCall(); }
469    bool isReturn()       const { return staticInst->isReturn(); }
470    bool isDirectCtrl()   const { return staticInst->isDirectCtrl(); }
471    bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
472    bool isCondCtrl()     const { return staticInst->isCondCtrl(); }
473    bool isUncondCtrl()   const { return staticInst->isUncondCtrl(); }
474    bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
475    bool isThreadSync()   const { return staticInst->isThreadSync(); }
476    bool isSerializing()  const { return staticInst->isSerializing(); }
477    bool isSerializeBefore() const
478    { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
479    bool isSerializeAfter() const
480    { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
481    bool isMemBarrier()   const { return staticInst->isMemBarrier(); }
482    bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
483    bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
484    bool isQuiesce() const { return staticInst->isQuiesce(); }
485    bool isIprAccess() const { return staticInst->isIprAccess(); }
486    bool isUnverifiable() const { return staticInst->isUnverifiable(); }
487    bool isSyscall() const { return staticInst->isSyscall(); }
488    bool isMacroop() const { return staticInst->isMacroop(); }
489    bool isMicroop() const { return staticInst->isMicroop(); }
490    bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
491    bool isLastMicroop() const { return staticInst->isLastMicroop(); }
492    bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
493    bool isMicroBranch() const { return staticInst->isMicroBranch(); }
494
495    /** Temporarily sets this instruction as a serialize before instruction. */
496    void setSerializeBefore() { status.set(SerializeBefore); }
497
498    /** Clears the serializeBefore part of this instruction. */
499    void clearSerializeBefore() { status.reset(SerializeBefore); }
500
501    /** Checks if this serializeBefore is only temporarily set. */
502    bool isTempSerializeBefore() { return status[SerializeBefore]; }
503
504    /** Temporarily sets this instruction as a serialize after instruction. */
505    void setSerializeAfter() { status.set(SerializeAfter); }
506
507    /** Clears the serializeAfter part of this instruction.*/
508    void clearSerializeAfter() { status.reset(SerializeAfter); }
509
510    /** Checks if this serializeAfter is only temporarily set. */
511    bool isTempSerializeAfter() { return status[SerializeAfter]; }
512
513    /** Sets the serialization part of this instruction as handled. */
514    void setSerializeHandled() { status.set(SerializeHandled); }
515
516    /** Checks if the serialization part of this instruction has been
517     *  handled.  This does not apply to the temporary serializing
518     *  state; it only applies to this instruction's own permanent
519     *  serializing state.
520     */
521    bool isSerializeHandled() { return status[SerializeHandled]; }
522
523    /** Returns the opclass of this instruction. */
524    OpClass opClass() const { return staticInst->opClass(); }
525
526    /** Returns the branch target address. */
527    TheISA::PCState branchTarget() const
528    { return staticInst->branchTarget(pc); }
529
530    /** Returns the number of source registers. */
531    int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
532
533    /** Returns the number of destination registers. */
534    int8_t numDestRegs() const { return staticInst->numDestRegs(); }
535
536    // the following are used to track physical register usage
537    // for machines with separate int & FP reg files
538    int8_t numFPDestRegs()  const { return staticInst->numFPDestRegs(); }
539    int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
540
541    /** Returns the logical register index of the i'th destination register. */
542    RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
543
544    /** Returns the logical register index of the i'th source register. */
545    RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
546
547    /** Returns the result of an integer instruction. */
548    uint64_t readIntResult() { return instResult.integer; }
549
550    /** Returns the result of a floating point instruction. */
551    float readFloatResult() { return (float)instResult.dbl; }
552
553    /** Returns the result of a floating point (double) instruction. */
554    double readDoubleResult() { return instResult.dbl; }
555
556    /** Records an integer register being set to a value. */
557    void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
558    {
559        if (recordResult)
560            instResult.integer = val;
561    }
562
563    /** Records an fp register being set to a value. */
564    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
565                            int width)
566    {
567        if (recordResult) {
568            if (width == 32)
569                instResult.dbl = (double)val;
570            else if (width == 64)
571                instResult.dbl = val;
572            else
573                panic("Unsupported width!");
574        }
575    }
576
577    /** Records an fp register being set to a value. */
578    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
579    {
580        if (recordResult)
581            instResult.dbl = (double)val;
582    }
583
584    /** Records an fp register being set to an integer value. */
585    void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val,
586                                int width)
587    {
588        if (recordResult)
589            instResult.integer = val;
590    }
591
592    /** Records an fp register being set to an integer value. */
593    void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val)
594    {
595        if (recordResult)
596            instResult.integer = val;
597    }
598
599    /** Records that one of the source registers is ready. */
600    void markSrcRegReady();
601
602    /** Marks a specific register as ready. */
603    void markSrcRegReady(RegIndex src_idx);
604
605    /** Returns if a source register is ready. */
606    bool isReadySrcRegIdx(int idx) const
607    {
608        return this->_readySrcRegIdx[idx];
609    }
610
611    /** Sets this instruction as completed. */
612    void setCompleted() { status.set(Completed); }
613
614    /** Returns whether or not this instruction is completed. */
615    bool isCompleted() const { return status[Completed]; }
616
617    /** Marks the result as ready. */
618    void setResultReady() { status.set(ResultReady); }
619
620    /** Returns whether or not the result is ready. */
621    bool isResultReady() const { return status[ResultReady]; }
622
623    /** Sets this instruction as ready to issue. */
624    void setCanIssue() { status.set(CanIssue); }
625
626    /** Returns whether or not this instruction is ready to issue. */
627    bool readyToIssue() const { return status[CanIssue]; }
628
629    /** Clears this instruction being able to issue. */
630    void clearCanIssue() { status.reset(CanIssue); }
631
632    /** Sets this instruction as issued from the IQ. */
633    void setIssued() { status.set(Issued); }
634
635    /** Returns whether or not this instruction has issued. */
636    bool isIssued() const { return status[Issued]; }
637
638    /** Clears this instruction as being issued. */
639    void clearIssued() { status.reset(Issued); }
640
641    /** Sets this instruction as executed. */
642    void setExecuted() { status.set(Executed); }
643
644    /** Returns whether or not this instruction has executed. */
645    bool isExecuted() const { return status[Executed]; }
646
647    /** Sets this instruction as ready to commit. */
648    void setCanCommit() { status.set(CanCommit); }
649
650    /** Clears this instruction as being ready to commit. */
651    void clearCanCommit() { status.reset(CanCommit); }
652
653    /** Returns whether or not this instruction is ready to commit. */
654    bool readyToCommit() const { return status[CanCommit]; }
655
656    void setAtCommit() { status.set(AtCommit); }
657
658    bool isAtCommit() { return status[AtCommit]; }
659
660    /** Sets this instruction as committed. */
661    void setCommitted() { status.set(Committed); }
662
663    /** Returns whether or not this instruction is committed. */
664    bool isCommitted() const { return status[Committed]; }
665
666    /** Sets this instruction as squashed. */
667    void setSquashed() { status.set(Squashed); }
668
669    /** Returns whether or not this instruction is squashed. */
670    bool isSquashed() const { return status[Squashed]; }
671
672    //Instruction Queue Entry
673    //-----------------------
674    /** Sets this instruction as a entry the IQ. */
675    void setInIQ() { status.set(IqEntry); }
676
677    /** Sets this instruction as a entry the IQ. */
678    void clearInIQ() { status.reset(IqEntry); }
679
680    /** Returns whether or not this instruction has issued. */
681    bool isInIQ() const { return status[IqEntry]; }
682
683    /** Sets this instruction as squashed in the IQ. */
684    void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
685
686    /** Returns whether or not this instruction is squashed in the IQ. */
687    bool isSquashedInIQ() const { return status[SquashedInIQ]; }
688
689
690    //Load / Store Queue Functions
691    //-----------------------
692    /** Sets this instruction as a entry the LSQ. */
693    void setInLSQ() { status.set(LsqEntry); }
694
695    /** Sets this instruction as a entry the LSQ. */
696    void removeInLSQ() { status.reset(LsqEntry); }
697
698    /** Returns whether or not this instruction is in the LSQ. */
699    bool isInLSQ() const { return status[LsqEntry]; }
700
701    /** Sets this instruction as squashed in the LSQ. */
702    void setSquashedInLSQ() { status.set(SquashedInLSQ);}
703
704    /** Returns whether or not this instruction is squashed in the LSQ. */
705    bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
706
707
708    //Reorder Buffer Functions
709    //-----------------------
710    /** Sets this instruction as a entry the ROB. */
711    void setInROB() { status.set(RobEntry); }
712
713    /** Sets this instruction as a entry the ROB. */
714    void clearInROB() { status.reset(RobEntry); }
715
716    /** Returns whether or not this instruction is in the ROB. */
717    bool isInROB() const { return status[RobEntry]; }
718
719    /** Sets this instruction as squashed in the ROB. */
720    void setSquashedInROB() { status.set(SquashedInROB); }
721
722    /** Returns whether or not this instruction is squashed in the ROB. */
723    bool isSquashedInROB() const { return status[SquashedInROB]; }
724
725    /** Read the PC state of this instruction. */
726    const TheISA::PCState pcState() const { return pc; }
727
728    /** Set the PC state of this instruction. */
729    const void pcState(const TheISA::PCState &val) { pc = val; }
730
731    /** Read the PC of this instruction. */
732    const Addr instAddr() const { return pc.instAddr(); }
733
734    /** Read the PC of the next instruction. */
735    const Addr nextInstAddr() const { return pc.nextInstAddr(); }
736
737    /**Read the micro PC of this instruction. */
738    const Addr microPC() const { return pc.microPC(); }
739
740    bool readPredicate()
741    {
742        return predicate;
743    }
744
745    void setPredicate(bool val)
746    {
747        predicate = val;
748
749        if (traceData) {
750            traceData->setPredicate(val);
751        }
752    }
753
754    /** Sets the ASID. */
755    void setASID(short addr_space_id) { asid = addr_space_id; }
756
757    /** Sets the thread id. */
758    void setTid(ThreadID tid) { threadNumber = tid; }
759
760    /** Sets the pointer to the thread state. */
761    void setThreadState(ImplState *state) { thread = state; }
762
763    /** Returns the thread context. */
764    ThreadContext *tcBase() { return thread->getTC(); }
765
766  private:
767    /** Instruction effective address.
768     *  @todo: Consider if this is necessary or not.
769     */
770    Addr instEffAddr;
771
772    /** Whether or not the effective address calculation is completed.
773     *  @todo: Consider if this is necessary or not.
774     */
775    bool eaCalcDone;
776
777    /** Is this instruction's memory access uncacheable. */
778    bool isUncacheable;
779
780    /** Has this instruction generated a memory request. */
781    bool reqMade;
782
783  public:
784    /** Sets the effective address. */
785    void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
786
787    /** Returns the effective address. */
788    const Addr &getEA() const { return instEffAddr; }
789
790    /** Returns whether or not the eff. addr. calculation has been completed. */
791    bool doneEACalc() { return eaCalcDone; }
792
793    /** Returns whether or not the eff. addr. source registers are ready. */
794    bool eaSrcsReady();
795
796    /** Whether or not the memory operation is done. */
797    bool memOpDone;
798
799    /** Is this instruction's memory access uncacheable. */
800    bool uncacheable() { return isUncacheable; }
801
802    /** Has this instruction generated a memory request. */
803    bool hasRequest() { return reqMade; }
804
805  public:
806    /** Load queue index. */
807    int16_t lqIdx;
808
809    /** Store queue index. */
810    int16_t sqIdx;
811
812    /** Iterator pointing to this BaseDynInst in the list of all insts. */
813    ListIt instListIt;
814
815    /** Returns iterator to this instruction in the list of all insts. */
816    ListIt &getInstListIt() { return instListIt; }
817
818    /** Sets iterator for this instruction in the list of all insts. */
819    void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
820
821  public:
822    /** Returns the number of consecutive store conditional failures. */
823    unsigned readStCondFailures()
824    { return thread->storeCondFailures; }
825
826    /** Sets the number of consecutive store conditional failures. */
827    void setStCondFailures(unsigned sc_failures)
828    { thread->storeCondFailures = sc_failures; }
829};
830
831template<class Impl>
832Fault
833BaseDynInst<Impl>::readBytes(Addr addr, uint8_t *data,
834                             unsigned size, unsigned flags)
835{
836    reqMade = true;
837    Request *req = new Request(asid, addr, size, flags, this->pc.instAddr(),
838                               thread->contextId(), threadNumber);
839
840    Request *sreqLow = NULL;
841    Request *sreqHigh = NULL;
842
843    // Only split the request if the ISA supports unaligned accesses.
844    if (TheISA::HasUnalignedMemAcc) {
845        splitRequest(req, sreqLow, sreqHigh);
846    }
847    initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
848
849    if (fault == NoFault) {
850        effAddr = req->getVaddr();
851        effAddrValid = true;
852        fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx);
853    } else {
854        // Commit will have to clean up whatever happened.  Set this
855        // instruction as executed.
856        this->setExecuted();
857    }
858
859    if (fault != NoFault) {
860        // Return a fixed value to keep simulation deterministic even
861        // along misspeculated paths.
862        bzero(data, size);
863    }
864
865    if (traceData) {
866        traceData->setAddr(addr);
867    }
868
869    return fault;
870}
871
872template<class Impl>
873template<class T>
874inline Fault
875BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
876{
877    Fault fault = readBytes(addr, (uint8_t *)&data, sizeof(T), flags);
878
879    data = TheISA::gtoh(data);
880
881    if (traceData) {
882        traceData->setData(data);
883    }
884
885    return fault;
886}
887
888template<class Impl>
889Fault
890BaseDynInst<Impl>::writeBytes(uint8_t *data, unsigned size,
891                              Addr addr, unsigned flags, uint64_t *res)
892{
893    if (traceData) {
894        traceData->setAddr(addr);
895    }
896
897    reqMade = true;
898    Request *req = new Request(asid, addr, size, flags, this->pc.instAddr(),
899                               thread->contextId(), threadNumber);
900
901    Request *sreqLow = NULL;
902    Request *sreqHigh = NULL;
903
904    // Only split the request if the ISA supports unaligned accesses.
905    if (TheISA::HasUnalignedMemAcc) {
906        splitRequest(req, sreqLow, sreqHigh);
907    }
908    initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write);
909
910    if (fault == NoFault) {
911        effAddr = req->getVaddr();
912        effAddrValid = true;
913        fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
914    }
915
916    return fault;
917}
918
919template<class Impl>
920template<class T>
921inline Fault
922BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
923{
924    if (traceData) {
925        traceData->setData(data);
926    }
927    data = TheISA::htog(data);
928    return writeBytes((uint8_t *)&data, sizeof(T), addr, flags, res);
929}
930
931template<class Impl>
932inline void
933BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow,
934                                RequestPtr &sreqHigh)
935{
936    // Check to see if the request crosses the next level block boundary.
937    unsigned block_size = cpu->getDcachePort()->peerBlockSize();
938    Addr addr = req->getVaddr();
939    Addr split_addr = roundDown(addr + req->getSize() - 1, block_size);
940    assert(split_addr <= addr || split_addr - addr < block_size);
941
942    // Spans two blocks.
943    if (split_addr > addr) {
944        req->splitOnVaddr(split_addr, sreqLow, sreqHigh);
945    }
946}
947
948template<class Impl>
949inline void
950BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow,
951                                       RequestPtr sreqHigh, uint64_t *res,
952                                       BaseTLB::Mode mode)
953{
954    if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) {
955        WholeTranslationState *state =
956            new WholeTranslationState(req, NULL, res, mode);
957
958        // One translation if the request isn't split.
959        DataTranslation<BaseDynInst<Impl> > *trans =
960            new DataTranslation<BaseDynInst<Impl> >(this, state);
961        cpu->dtb->translateTiming(req, thread->getTC(), trans, mode);
962    } else {
963        WholeTranslationState *state =
964            new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode);
965
966        // Two translations when the request is split.
967        DataTranslation<BaseDynInst<Impl> > *stransLow =
968            new DataTranslation<BaseDynInst<Impl> >(this, state, 0);
969        DataTranslation<BaseDynInst<Impl> > *stransHigh =
970            new DataTranslation<BaseDynInst<Impl> >(this, state, 1);
971
972        cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode);
973        cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode);
974    }
975}
976
977template<class Impl>
978inline void
979BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state)
980{
981    fault = state->getFault();
982
983    if (state->isUncacheable())
984        isUncacheable = true;
985
986    if (fault == NoFault) {
987        physEffAddr = state->getPaddr();
988        memReqFlags = state->getFlags();
989
990        if (state->mainReq->isCondSwap()) {
991            assert(state->res);
992            state->mainReq->setExtraData(*state->res);
993        }
994
995    } else {
996        state->deleteReqs();
997    }
998    delete state;
999}
1000
1001#endif // __CPU_BASE_DYN_INST_HH__
1002