base_dyn_inst.hh revision 5737:f43dbc09fad3
11060SN/A/* 27944SGiacomo.Gabrielli@arm.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 37944SGiacomo.Gabrielli@arm.com * All rights reserved. 47944SGiacomo.Gabrielli@arm.com * 57944SGiacomo.Gabrielli@arm.com * Redistribution and use in source and binary forms, with or without 67944SGiacomo.Gabrielli@arm.com * modification, are permitted provided that the following conditions are 77944SGiacomo.Gabrielli@arm.com * met: redistributions of source code must retain the above copyright 87944SGiacomo.Gabrielli@arm.com * notice, this list of conditions and the following disclaimer; 97944SGiacomo.Gabrielli@arm.com * redistributions in binary form must reproduce the above copyright 107944SGiacomo.Gabrielli@arm.com * notice, this list of conditions and the following disclaimer in the 117944SGiacomo.Gabrielli@arm.com * documentation and/or other materials provided with the distribution; 127944SGiacomo.Gabrielli@arm.com * neither the name of the copyright holders nor the names of its 137944SGiacomo.Gabrielli@arm.com * contributors may be used to endorse or promote products derived from 142702SN/A * this software without specific prior written permission. 151060SN/A * 161060SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171060SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181060SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191060SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211060SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221060SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241060SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251060SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261060SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 271060SN/A * 281060SN/A * Authors: Kevin Lim 291060SN/A */ 301060SN/A 311060SN/A#ifndef __CPU_BASE_DYN_INST_HH__ 321060SN/A#define __CPU_BASE_DYN_INST_HH__ 331060SN/A 341060SN/A#include <bitset> 351060SN/A#include <list> 361060SN/A#include <string> 371060SN/A 381060SN/A#include "arch/faults.hh" 392665SN/A#include "base/fast_alloc.hh" 402665SN/A#include "base/trace.hh" 411060SN/A#include "config/full_system.hh" 421060SN/A#include "cpu/o3/comm.hh" 431060SN/A#include "cpu/exetrace.hh" 442292SN/A#include "cpu/inst_seq.hh" 458229Snate@binkert.org#include "cpu/op_class.hh" 461060SN/A#include "cpu/static_inst.hh" 471060SN/A#include "mem/packet.hh" 481060SN/A#include "sim/system.hh" 491061SN/A 506658Snate@binkert.org/** 516658Snate@binkert.org * @file 521060SN/A * Defines a dynamic instruction context. 538232Snate@binkert.org */ 548232Snate@binkert.org 552669SN/A// Forward declaration. 566658Snate@binkert.orgclass StaticInstPtr; 571060SN/A 581060SN/Atemplate <class Impl> 591060SN/Aclass BaseDynInst : public FastAlloc, public RefCounted 601060SN/A{ 611060SN/A public: 621060SN/A // Typedef for the CPU. 631060SN/A typedef typename Impl::CPUType ImplCPU; 641060SN/A typedef typename ImplCPU::ImplState ImplState; 652292SN/A 662292SN/A // Logical register index type. 671060SN/A typedef TheISA::RegIndex RegIndex; 682292SN/A // Integer register type. 691060SN/A typedef TheISA::IntReg IntReg; 701060SN/A // Floating point register type. 712292SN/A typedef TheISA::FloatReg FloatReg; 722292SN/A 732292SN/A // The DynInstPtr type. 741060SN/A typedef typename Impl::DynInstPtr DynInstPtr; 751060SN/A 761060SN/A // The list of instructions iterator type. 771061SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 784636Sgblack@eecs.umich.edu 797720Sgblack@eecs.umich.edu enum { 803794Sgblack@eecs.umich.edu MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 814636Sgblack@eecs.umich.edu MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs 821060SN/A }; 831464SN/A 841061SN/A /** The StaticInst used by this BaseDynInst. */ 857720Sgblack@eecs.umich.edu StaticInstPtr staticInst; 867720Sgblack@eecs.umich.edu 874636Sgblack@eecs.umich.edu //////////////////////////////////////////// 884636Sgblack@eecs.umich.edu // 894636Sgblack@eecs.umich.edu // INSTRUCTION EXECUTION 904636Sgblack@eecs.umich.edu // 914636Sgblack@eecs.umich.edu //////////////////////////////////////////// 924636Sgblack@eecs.umich.edu /** InstRecord that tracks this instructions. */ 934636Sgblack@eecs.umich.edu Trace::InstRecord *traceData; 947720Sgblack@eecs.umich.edu 954636Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 967720Sgblack@eecs.umich.edu { 974636Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 984636Sgblack@eecs.umich.edu } 994636Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 1007720Sgblack@eecs.umich.edu { 1017720Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 1023794Sgblack@eecs.umich.edu } 1031464SN/A void demapDataPage(Addr vaddr, uint64_t asn) 1041464SN/A { 1051464SN/A cpu->demapPage(vaddr, asn); 1061464SN/A } 1071464SN/A 1082107SN/A /** 1091464SN/A * Does a read to a given address. 1101464SN/A * @param addr The address to read. 1112292SN/A * @param data The read's data is written into this parameter. 1121464SN/A * @param flags The request's flags. 1131464SN/A * @return Returns any fault due to the read. 1141464SN/A */ 1151464SN/A template <class T> 1161464SN/A Fault read(Addr addr, T &data, unsigned flags); 1171464SN/A 1181464SN/A Fault translateDataReadAddr(Addr vaddr, Addr &paddr, 1192678SN/A int size, unsigned flags); 1202669SN/A 1214032Sktlim@umich.edu /** 1222669SN/A * Does a write to a given address. 1231060SN/A * @param data The data to be written. 1247944SGiacomo.Gabrielli@arm.com * @param addr The address to write to. 1257944SGiacomo.Gabrielli@arm.com * @param flags The request's flags. 1267944SGiacomo.Gabrielli@arm.com * @param res The result of the write (for load locked/store conditionals). 1274032Sktlim@umich.edu * @return Returns any fault due to the write. 1284032Sktlim@umich.edu */ 1291060SN/A template <class T> 1301060SN/A Fault write(T data, Addr addr, unsigned flags, 1312702SN/A uint64_t *res); 1323326Sktlim@umich.edu 1332702SN/A Fault translateDataWriteAddr(Addr vaddr, Addr &paddr, 1342731SN/A int size, unsigned flags); 1352731SN/A 1361464SN/A void prefetch(Addr addr, unsigned flags); 1372292SN/A void writeHint(Addr addr, int size, unsigned flags); 1387597Sminkyu.jeong@arm.com Fault copySrcTranslate(Addr src); 1392731SN/A Fault copy(Addr dest); 1402292SN/A 1412292SN/A /** @todo: Consider making this private. */ 1422292SN/A public: 1431060SN/A /** The sequence number of the instruction. */ 1441060SN/A InstSeqNum seqNum; 1451464SN/A 1461060SN/A enum Status { 1471060SN/A IqEntry, /// Instruction is in the IQ 1481060SN/A RobEntry, /// Instruction is in the ROB 1492698SN/A LsqEntry, /// Instruction is in the LSQ 1502292SN/A Completed, /// Instruction has completed 1511060SN/A ResultReady, /// Instruction has its result 1525737Scws3k@cs.virginia.edu CanIssue, /// Instruction can issue and execute 1535737Scws3k@cs.virginia.edu Issued, /// Instruction has issued 1541060SN/A Executed, /// Instruction has executed 1555737Scws3k@cs.virginia.edu CanCommit, /// Instruction can commit 1565375Svilas.sridharan@gmail.com AtCommit, /// Instruction has reached commit 1572292SN/A Committed, /// Instruction has committed 1582292SN/A Squashed, /// Instruction is squashed 1592292SN/A SquashedInIQ, /// Instruction is squashed in the IQ 1605737Scws3k@cs.virginia.edu SquashedInLSQ, /// Instruction is squashed in the LSQ 1612292SN/A SquashedInROB, /// Instruction is squashed in the ROB 1622292SN/A RecoverInst, /// Is a recover instruction 1635737Scws3k@cs.virginia.edu BlockingInst, /// Is a blocking instruction 1645737Scws3k@cs.virginia.edu ThreadsyncWait, /// Is a thread synchronization instruction 1655737Scws3k@cs.virginia.edu SerializeBefore, /// Needs to serialize on 1665737Scws3k@cs.virginia.edu /// instructions ahead of it 1672292SN/A SerializeAfter, /// Needs to serialize instructions behind it 1682292SN/A SerializeHandled, /// Serialization has been handled 1692292SN/A NumStatus 1702292SN/A }; 1711060SN/A 1721060SN/A /** The status of this BaseDynInst. Several bits can be set. */ 1731061SN/A std::bitset<NumStatus> status; 1741060SN/A 1751060SN/A /** The thread this instruction is from. */ 1762678SN/A short threadNumber; 1772678SN/A 1782292SN/A /** data address space ID, for loads & stores. */ 1792292SN/A short asid; 1802292SN/A 1812292SN/A /** How many source registers are ready. */ 1822292SN/A unsigned readyRegs; 1832292SN/A 1842348SN/A /** Pointer to the Impl's CPU object. */ 1852348SN/A ImplCPU *cpu; 1865737Scws3k@cs.virginia.edu 1875737Scws3k@cs.virginia.edu /** Pointer to the thread state. */ 1882292SN/A ImplState *thread; 1895737Scws3k@cs.virginia.edu 1905737Scws3k@cs.virginia.edu /** The kind of fault this instruction has generated. */ 1915737Scws3k@cs.virginia.edu Fault fault; 1925737Scws3k@cs.virginia.edu 1932292SN/A /** Pointer to the data for the memory access. */ 1942292SN/A uint8_t *memData; 1952292SN/A 1961060SN/A /** The effective virtual address (lds & stores only). */ 1971464SN/A Addr effAddr; 1982292SN/A 1992292SN/A /** Is the effective virtual address valid. */ 2002292SN/A bool effAddrValid; 2012292SN/A 2022292SN/A /** The effective physical address. */ 2032292SN/A Addr physEffAddr; 2042292SN/A 2052292SN/A /** Effective virtual address for a copy source. */ 2062292SN/A Addr copySrcEffAddr; 2072292SN/A 2082292SN/A /** Effective physical address for a copy source. */ 2092292SN/A Addr copySrcPhysEffAddr; 2102292SN/A 2112292SN/A /** The memory request flags (from translation). */ 2122292SN/A unsigned memReqFlags; 2132292SN/A 2141061SN/A union Result { 2151060SN/A uint64_t integer; 2161060SN/A// float fp; 2171060SN/A double dbl; 2187720Sgblack@eecs.umich.edu }; 2197720Sgblack@eecs.umich.edu 2201060SN/A /** The result of the instruction; assumes for now that there's only one 2211060SN/A * destination register. 2221060SN/A */ 2231061SN/A Result instResult; 2241060SN/A 2251060SN/A /** Records changes to result? */ 2261060SN/A bool recordResult; 2271060SN/A 2287720Sgblack@eecs.umich.edu /** PC of this instruction. */ 2297720Sgblack@eecs.umich.edu Addr PC; 2301060SN/A 2311060SN/A /** Micro PC of this instruction. */ 2321060SN/A Addr microPC; 2331060SN/A 2341464SN/A protected: 2352292SN/A /** Next non-speculative PC. It is not filled in at fetch, but rather 2362292SN/A * once the target of the branch is truly known (either decode or 2372292SN/A * execute). 2387599Sminkyu.jeong@arm.com */ 2397599Sminkyu.jeong@arm.com Addr nextPC; 2402292SN/A 2414032Sktlim@umich.edu /** Next non-speculative NPC. Target PC for Mips or Sparc. */ 2422292SN/A Addr nextNPC; 2432292SN/A 2442292SN/A /** Next non-speculative micro PC. */ 2452292SN/A Addr nextMicroPC; 2462292SN/A 2472292SN/A /** Predicted next PC. */ 2482292SN/A Addr predPC; 2492292SN/A 2502292SN/A /** Predicted next NPC. */ 2512731SN/A Addr predNPC; 2522292SN/A 2532292SN/A /** Predicted next microPC */ 2542292SN/A Addr predMicroPC; 2551464SN/A 2561464SN/A /** If this is a branch that was predicted taken */ 2571464SN/A bool predTaken; 2581464SN/A 2591464SN/A public: 2601464SN/A 2611464SN/A#ifdef DEBUG 2622292SN/A void dumpSNList(); 2631464SN/A#endif 2641464SN/A 2651464SN/A /** Whether or not the source register is ready. 2661464SN/A * @todo: Not sure this should be here vs the derived class. 2671464SN/A */ 2681464SN/A bool _readySrcRegIdx[MaxInstSrcRegs]; 269 270 protected: 271 /** Flattened register index of the destination registers of this 272 * instruction. 273 */ 274 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs]; 275 276 /** Flattened register index of the source registers of this 277 * instruction. 278 */ 279 TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs]; 280 281 /** Physical register index of the destination registers of this 282 * instruction. 283 */ 284 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs]; 285 286 /** Physical register index of the source registers of this 287 * instruction. 288 */ 289 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs]; 290 291 /** Physical register index of the previous producers of the 292 * architected destinations. 293 */ 294 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs]; 295 296 public: 297 298 /** Returns the physical register index of the i'th destination 299 * register. 300 */ 301 PhysRegIndex renamedDestRegIdx(int idx) const 302 { 303 return _destRegIdx[idx]; 304 } 305 306 /** Returns the physical register index of the i'th source register. */ 307 PhysRegIndex renamedSrcRegIdx(int idx) const 308 { 309 return _srcRegIdx[idx]; 310 } 311 312 /** Returns the flattened register index of the i'th destination 313 * register. 314 */ 315 TheISA::RegIndex flattenedDestRegIdx(int idx) const 316 { 317 return _flatDestRegIdx[idx]; 318 } 319 320 /** Returns the flattened register index of the i'th source register */ 321 TheISA::RegIndex flattenedSrcRegIdx(int idx) const 322 { 323 return _flatSrcRegIdx[idx]; 324 } 325 326 /** Returns the physical register index of the previous physical register 327 * that remapped to the same logical register index. 328 */ 329 PhysRegIndex prevDestRegIdx(int idx) const 330 { 331 return _prevDestRegIdx[idx]; 332 } 333 334 /** Renames a destination register to a physical register. Also records 335 * the previous physical register that the logical register mapped to. 336 */ 337 void renameDestReg(int idx, 338 PhysRegIndex renamed_dest, 339 PhysRegIndex previous_rename) 340 { 341 _destRegIdx[idx] = renamed_dest; 342 _prevDestRegIdx[idx] = previous_rename; 343 } 344 345 /** Renames a source logical register to the physical register which 346 * has/will produce that logical register's result. 347 * @todo: add in whether or not the source register is ready. 348 */ 349 void renameSrcReg(int idx, PhysRegIndex renamed_src) 350 { 351 _srcRegIdx[idx] = renamed_src; 352 } 353 354 /** Flattens a source architectural register index into a logical index. 355 */ 356 void flattenSrcReg(int idx, TheISA::RegIndex flattened_src) 357 { 358 _flatSrcRegIdx[idx] = flattened_src; 359 } 360 361 /** Flattens a destination architectural register index into a logical 362 * index. 363 */ 364 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 365 { 366 _flatDestRegIdx[idx] = flattened_dest; 367 } 368 /** BaseDynInst constructor given a binary instruction. 369 * @param staticInst A StaticInstPtr to the underlying instruction. 370 * @param PC The PC of the instruction. 371 * @param pred_PC The predicted next PC. 372 * @param pred_NPC The predicted next NPC. 373 * @param seq_num The sequence number of the instruction. 374 * @param cpu Pointer to the instruction's CPU. 375 */ 376 BaseDynInst(StaticInstPtr staticInst, Addr PC, Addr NPC, Addr microPC, 377 Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC, 378 InstSeqNum seq_num, ImplCPU *cpu); 379 380 /** BaseDynInst constructor given a binary instruction. 381 * @param inst The binary instruction. 382 * @param PC The PC of the instruction. 383 * @param pred_PC The predicted next PC. 384 * @param pred_NPC The predicted next NPC. 385 * @param seq_num The sequence number of the instruction. 386 * @param cpu Pointer to the instruction's CPU. 387 */ 388 BaseDynInst(TheISA::ExtMachInst inst, Addr PC, Addr NPC, Addr microPC, 389 Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC, 390 InstSeqNum seq_num, ImplCPU *cpu); 391 392 /** BaseDynInst constructor given a StaticInst pointer. 393 * @param _staticInst The StaticInst for this BaseDynInst. 394 */ 395 BaseDynInst(StaticInstPtr &_staticInst); 396 397 /** BaseDynInst destructor. */ 398 ~BaseDynInst(); 399 400 private: 401 /** Function to initialize variables in the constructors. */ 402 void initVars(); 403 404 public: 405 /** Dumps out contents of this BaseDynInst. */ 406 void dump(); 407 408 /** Dumps out contents of this BaseDynInst into given string. */ 409 void dump(std::string &outstring); 410 411 /** Read this CPU's ID. */ 412 int cpuId() { return cpu->cpuId(); } 413 414 /** Read this context's system-wide ID **/ 415 int contextId() { return thread->contextId(); } 416 417 /** Returns the fault type. */ 418 Fault getFault() { return fault; } 419 420 /** Checks whether or not this instruction has had its branch target 421 * calculated yet. For now it is not utilized and is hacked to be 422 * always false. 423 * @todo: Actually use this instruction. 424 */ 425 bool doneTargCalc() { return false; } 426 427 /** Returns the next PC. This could be the speculative next PC if it is 428 * called prior to the actual branch target being calculated. 429 */ 430 Addr readNextPC() { return nextPC; } 431 432 /** Returns the next NPC. This could be the speculative next NPC if it is 433 * called prior to the actual branch target being calculated. 434 */ 435 Addr readNextNPC() 436 { 437#if ISA_HAS_DELAY_SLOT 438 return nextNPC; 439#else 440 return nextPC + sizeof(TheISA::MachInst); 441#endif 442 } 443 444 Addr readNextMicroPC() 445 { 446 return nextMicroPC; 447 } 448 449 /** Set the predicted target of this current instruction. */ 450 void setPredTarg(Addr predicted_PC, Addr predicted_NPC, 451 Addr predicted_MicroPC) 452 { 453 predPC = predicted_PC; 454 predNPC = predicted_NPC; 455 predMicroPC = predicted_MicroPC; 456 } 457 458 /** Returns the predicted PC immediately after the branch. */ 459 Addr readPredPC() { return predPC; } 460 461 /** Returns the predicted PC two instructions after the branch */ 462 Addr readPredNPC() { return predNPC; } 463 464 /** Returns the predicted micro PC after the branch */ 465 Addr readPredMicroPC() { return predMicroPC; } 466 467 /** Returns whether the instruction was predicted taken or not. */ 468 bool readPredTaken() 469 { 470 return predTaken; 471 } 472 473 void setPredTaken(bool predicted_taken) 474 { 475 predTaken = predicted_taken; 476 } 477 478 /** Returns whether the instruction mispredicted. */ 479 bool mispredicted() 480 { 481 return readPredPC() != readNextPC() || 482 readPredNPC() != readNextNPC() || 483 readPredMicroPC() != readNextMicroPC(); 484 } 485 486 // 487 // Instruction types. Forward checks to StaticInst object. 488 // 489 bool isNop() const { return staticInst->isNop(); } 490 bool isMemRef() const { return staticInst->isMemRef(); } 491 bool isLoad() const { return staticInst->isLoad(); } 492 bool isStore() const { return staticInst->isStore(); } 493 bool isStoreConditional() const 494 { return staticInst->isStoreConditional(); } 495 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 496 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 497 bool isCopy() const { return staticInst->isCopy(); } 498 bool isInteger() const { return staticInst->isInteger(); } 499 bool isFloating() const { return staticInst->isFloating(); } 500 bool isControl() const { return staticInst->isControl(); } 501 bool isCall() const { return staticInst->isCall(); } 502 bool isReturn() const { return staticInst->isReturn(); } 503 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 504 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 505 bool isCondCtrl() const { return staticInst->isCondCtrl(); } 506 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 507 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 508 bool isThreadSync() const { return staticInst->isThreadSync(); } 509 bool isSerializing() const { return staticInst->isSerializing(); } 510 bool isSerializeBefore() const 511 { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 512 bool isSerializeAfter() const 513 { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 514 bool isMemBarrier() const { return staticInst->isMemBarrier(); } 515 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 516 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 517 bool isQuiesce() const { return staticInst->isQuiesce(); } 518 bool isIprAccess() const { return staticInst->isIprAccess(); } 519 bool isUnverifiable() const { return staticInst->isUnverifiable(); } 520 bool isSyscall() const { return staticInst->isSyscall(); } 521 bool isMacroop() const { return staticInst->isMacroop(); } 522 bool isMicroop() const { return staticInst->isMicroop(); } 523 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 524 bool isLastMicroop() const { return staticInst->isLastMicroop(); } 525 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 526 bool isMicroBranch() const { return staticInst->isMicroBranch(); } 527 528 /** Temporarily sets this instruction as a serialize before instruction. */ 529 void setSerializeBefore() { status.set(SerializeBefore); } 530 531 /** Clears the serializeBefore part of this instruction. */ 532 void clearSerializeBefore() { status.reset(SerializeBefore); } 533 534 /** Checks if this serializeBefore is only temporarily set. */ 535 bool isTempSerializeBefore() { return status[SerializeBefore]; } 536 537 /** Temporarily sets this instruction as a serialize after instruction. */ 538 void setSerializeAfter() { status.set(SerializeAfter); } 539 540 /** Clears the serializeAfter part of this instruction.*/ 541 void clearSerializeAfter() { status.reset(SerializeAfter); } 542 543 /** Checks if this serializeAfter is only temporarily set. */ 544 bool isTempSerializeAfter() { return status[SerializeAfter]; } 545 546 /** Sets the serialization part of this instruction as handled. */ 547 void setSerializeHandled() { status.set(SerializeHandled); } 548 549 /** Checks if the serialization part of this instruction has been 550 * handled. This does not apply to the temporary serializing 551 * state; it only applies to this instruction's own permanent 552 * serializing state. 553 */ 554 bool isSerializeHandled() { return status[SerializeHandled]; } 555 556 /** Returns the opclass of this instruction. */ 557 OpClass opClass() const { return staticInst->opClass(); } 558 559 /** Returns the branch target address. */ 560 Addr branchTarget() const { return staticInst->branchTarget(PC); } 561 562 /** Returns the number of source registers. */ 563 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 564 565 /** Returns the number of destination registers. */ 566 int8_t numDestRegs() const { return staticInst->numDestRegs(); } 567 568 // the following are used to track physical register usage 569 // for machines with separate int & FP reg files 570 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 571 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 572 573 /** Returns the logical register index of the i'th destination register. */ 574 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 575 576 /** Returns the logical register index of the i'th source register. */ 577 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 578 579 /** Returns the result of an integer instruction. */ 580 uint64_t readIntResult() { return instResult.integer; } 581 582 /** Returns the result of a floating point instruction. */ 583 float readFloatResult() { return (float)instResult.dbl; } 584 585 /** Returns the result of a floating point (double) instruction. */ 586 double readDoubleResult() { return instResult.dbl; } 587 588 /** Records an integer register being set to a value. */ 589 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 590 { 591 if (recordResult) 592 instResult.integer = val; 593 } 594 595 /** Records an fp register being set to a value. */ 596 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 597 int width) 598 { 599 if (recordResult) { 600 if (width == 32) 601 instResult.dbl = (double)val; 602 else if (width == 64) 603 instResult.dbl = val; 604 else 605 panic("Unsupported width!"); 606 } 607 } 608 609 /** Records an fp register being set to a value. */ 610 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 611 { 612 if (recordResult) 613 instResult.dbl = (double)val; 614 } 615 616 /** Records an fp register being set to an integer value. */ 617 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val, 618 int width) 619 { 620 if (recordResult) 621 instResult.integer = val; 622 } 623 624 /** Records an fp register being set to an integer value. */ 625 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val) 626 { 627 if (recordResult) 628 instResult.integer = val; 629 } 630 631 /** Records that one of the source registers is ready. */ 632 void markSrcRegReady(); 633 634 /** Marks a specific register as ready. */ 635 void markSrcRegReady(RegIndex src_idx); 636 637 /** Returns if a source register is ready. */ 638 bool isReadySrcRegIdx(int idx) const 639 { 640 return this->_readySrcRegIdx[idx]; 641 } 642 643 /** Sets this instruction as completed. */ 644 void setCompleted() { status.set(Completed); } 645 646 /** Returns whether or not this instruction is completed. */ 647 bool isCompleted() const { return status[Completed]; } 648 649 /** Marks the result as ready. */ 650 void setResultReady() { status.set(ResultReady); } 651 652 /** Returns whether or not the result is ready. */ 653 bool isResultReady() const { return status[ResultReady]; } 654 655 /** Sets this instruction as ready to issue. */ 656 void setCanIssue() { status.set(CanIssue); } 657 658 /** Returns whether or not this instruction is ready to issue. */ 659 bool readyToIssue() const { return status[CanIssue]; } 660 661 /** Clears this instruction being able to issue. */ 662 void clearCanIssue() { status.reset(CanIssue); } 663 664 /** Sets this instruction as issued from the IQ. */ 665 void setIssued() { status.set(Issued); } 666 667 /** Returns whether or not this instruction has issued. */ 668 bool isIssued() const { return status[Issued]; } 669 670 /** Clears this instruction as being issued. */ 671 void clearIssued() { status.reset(Issued); } 672 673 /** Sets this instruction as executed. */ 674 void setExecuted() { status.set(Executed); } 675 676 /** Returns whether or not this instruction has executed. */ 677 bool isExecuted() const { return status[Executed]; } 678 679 /** Sets this instruction as ready to commit. */ 680 void setCanCommit() { status.set(CanCommit); } 681 682 /** Clears this instruction as being ready to commit. */ 683 void clearCanCommit() { status.reset(CanCommit); } 684 685 /** Returns whether or not this instruction is ready to commit. */ 686 bool readyToCommit() const { return status[CanCommit]; } 687 688 void setAtCommit() { status.set(AtCommit); } 689 690 bool isAtCommit() { return status[AtCommit]; } 691 692 /** Sets this instruction as committed. */ 693 void setCommitted() { status.set(Committed); } 694 695 /** Returns whether or not this instruction is committed. */ 696 bool isCommitted() const { return status[Committed]; } 697 698 /** Sets this instruction as squashed. */ 699 void setSquashed() { status.set(Squashed); } 700 701 /** Returns whether or not this instruction is squashed. */ 702 bool isSquashed() const { return status[Squashed]; } 703 704 //Instruction Queue Entry 705 //----------------------- 706 /** Sets this instruction as a entry the IQ. */ 707 void setInIQ() { status.set(IqEntry); } 708 709 /** Sets this instruction as a entry the IQ. */ 710 void clearInIQ() { status.reset(IqEntry); } 711 712 /** Returns whether or not this instruction has issued. */ 713 bool isInIQ() const { return status[IqEntry]; } 714 715 /** Sets this instruction as squashed in the IQ. */ 716 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 717 718 /** Returns whether or not this instruction is squashed in the IQ. */ 719 bool isSquashedInIQ() const { return status[SquashedInIQ]; } 720 721 722 //Load / Store Queue Functions 723 //----------------------- 724 /** Sets this instruction as a entry the LSQ. */ 725 void setInLSQ() { status.set(LsqEntry); } 726 727 /** Sets this instruction as a entry the LSQ. */ 728 void removeInLSQ() { status.reset(LsqEntry); } 729 730 /** Returns whether or not this instruction is in the LSQ. */ 731 bool isInLSQ() const { return status[LsqEntry]; } 732 733 /** Sets this instruction as squashed in the LSQ. */ 734 void setSquashedInLSQ() { status.set(SquashedInLSQ);} 735 736 /** Returns whether or not this instruction is squashed in the LSQ. */ 737 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 738 739 740 //Reorder Buffer Functions 741 //----------------------- 742 /** Sets this instruction as a entry the ROB. */ 743 void setInROB() { status.set(RobEntry); } 744 745 /** Sets this instruction as a entry the ROB. */ 746 void clearInROB() { status.reset(RobEntry); } 747 748 /** Returns whether or not this instruction is in the ROB. */ 749 bool isInROB() const { return status[RobEntry]; } 750 751 /** Sets this instruction as squashed in the ROB. */ 752 void setSquashedInROB() { status.set(SquashedInROB); } 753 754 /** Returns whether or not this instruction is squashed in the ROB. */ 755 bool isSquashedInROB() const { return status[SquashedInROB]; } 756 757 /** Read the PC of this instruction. */ 758 const Addr readPC() const { return PC; } 759 760 /**Read the micro PC of this instruction. */ 761 const Addr readMicroPC() const { return microPC; } 762 763 /** Set the next PC of this instruction (its actual target). */ 764 void setNextPC(Addr val) 765 { 766 nextPC = val; 767 } 768 769 /** Set the next NPC of this instruction (the target in Mips or Sparc).*/ 770 void setNextNPC(Addr val) 771 { 772#if ISA_HAS_DELAY_SLOT 773 nextNPC = val; 774#endif 775 } 776 777 void setNextMicroPC(Addr val) 778 { 779 nextMicroPC = val; 780 } 781 782 /** Sets the ASID. */ 783 void setASID(short addr_space_id) { asid = addr_space_id; } 784 785 /** Sets the thread id. */ 786 void setTid(unsigned tid) { threadNumber = tid; } 787 788 /** Sets the pointer to the thread state. */ 789 void setThreadState(ImplState *state) { thread = state; } 790 791 /** Returns the thread context. */ 792 ThreadContext *tcBase() { return thread->getTC(); } 793 794 private: 795 /** Instruction effective address. 796 * @todo: Consider if this is necessary or not. 797 */ 798 Addr instEffAddr; 799 800 /** Whether or not the effective address calculation is completed. 801 * @todo: Consider if this is necessary or not. 802 */ 803 bool eaCalcDone; 804 805 /** Is this instruction's memory access uncacheable. */ 806 bool isUncacheable; 807 808 /** Has this instruction generated a memory request. */ 809 bool reqMade; 810 811 public: 812 /** Sets the effective address. */ 813 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 814 815 /** Returns the effective address. */ 816 const Addr &getEA() const { return instEffAddr; } 817 818 /** Returns whether or not the eff. addr. calculation has been completed. */ 819 bool doneEACalc() { return eaCalcDone; } 820 821 /** Returns whether or not the eff. addr. source registers are ready. */ 822 bool eaSrcsReady(); 823 824 /** Whether or not the memory operation is done. */ 825 bool memOpDone; 826 827 /** Is this instruction's memory access uncacheable. */ 828 bool uncacheable() { return isUncacheable; } 829 830 /** Has this instruction generated a memory request. */ 831 bool hasRequest() { return reqMade; } 832 833 public: 834 /** Load queue index. */ 835 int16_t lqIdx; 836 837 /** Store queue index. */ 838 int16_t sqIdx; 839 840 /** Iterator pointing to this BaseDynInst in the list of all insts. */ 841 ListIt instListIt; 842 843 /** Returns iterator to this instruction in the list of all insts. */ 844 ListIt &getInstListIt() { return instListIt; } 845 846 /** Sets iterator for this instruction in the list of all insts. */ 847 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 848 849 public: 850 /** Returns the number of consecutive store conditional failures. */ 851 unsigned readStCondFailures() 852 { return thread->storeCondFailures; } 853 854 /** Sets the number of consecutive store conditional failures. */ 855 void setStCondFailures(unsigned sc_failures) 856 { thread->storeCondFailures = sc_failures; } 857}; 858 859template<class Impl> 860Fault 861BaseDynInst<Impl>::translateDataReadAddr(Addr vaddr, Addr &paddr, 862 int size, unsigned flags) 863{ 864 if (traceData) { 865 traceData->setAddr(vaddr); 866 } 867 868 reqMade = true; 869 Request *req = new Request(); 870 req->setVirt(asid, vaddr, size, flags, PC); 871 req->setThreadContext(thread->contextId(), threadNumber); 872 873 fault = cpu->translateDataReadReq(req, thread); 874 875 if (fault == NoFault) 876 paddr = req->getPaddr(); 877 878 delete req; 879 return fault; 880} 881 882template<class Impl> 883template<class T> 884inline Fault 885BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) 886{ 887 reqMade = true; 888 Request *req = new Request(); 889 req->setVirt(asid, addr, sizeof(T), flags, this->PC); 890 req->setThreadContext(thread->contextId(), threadNumber); 891 892 fault = cpu->translateDataReadReq(req, thread); 893 894 if (req->isUncacheable()) 895 isUncacheable = true; 896 897 if (fault == NoFault) { 898 effAddr = req->getVaddr(); 899 effAddrValid = true; 900 physEffAddr = req->getPaddr(); 901 memReqFlags = req->getFlags(); 902 903#if 0 904 if (cpu->system->memctrl->badaddr(physEffAddr)) { 905 fault = TheISA::genMachineCheckFault(); 906 data = (T)-1; 907 this->setExecuted(); 908 } else { 909 fault = cpu->read(req, data, lqIdx); 910 } 911#else 912 fault = cpu->read(req, data, lqIdx); 913#endif 914 } else { 915 // Return a fixed value to keep simulation deterministic even 916 // along misspeculated paths. 917 data = (T)-1; 918 919 // Commit will have to clean up whatever happened. Set this 920 // instruction as executed. 921 this->setExecuted(); 922 delete req; 923 } 924 925 if (traceData) { 926 traceData->setAddr(addr); 927 traceData->setData(data); 928 } 929 930 return fault; 931} 932 933template<class Impl> 934Fault 935BaseDynInst<Impl>::translateDataWriteAddr(Addr vaddr, Addr &paddr, 936 int size, unsigned flags) 937{ 938 if (traceData) { 939 traceData->setAddr(vaddr); 940 } 941 942 reqMade = true; 943 Request *req = new Request(); 944 req->setVirt(asid, vaddr, size, flags, PC); 945 req->setThreadContext(thread->contextId(), threadNumber); 946 947 fault = cpu->translateDataWriteReq(req, thread); 948 949 if (fault == NoFault) 950 paddr = req->getPaddr(); 951 952 delete req; 953 return fault; 954} 955 956template<class Impl> 957template<class T> 958inline Fault 959BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) 960{ 961 if (traceData) { 962 traceData->setAddr(addr); 963 traceData->setData(data); 964 } 965 966 reqMade = true; 967 Request *req = new Request(); 968 req->setVirt(asid, addr, sizeof(T), flags, this->PC); 969 req->setThreadContext(thread->contextId(), threadNumber); 970 971 fault = cpu->translateDataWriteReq(req, thread); 972 973 if (req->isUncacheable()) 974 isUncacheable = true; 975 976 if (fault == NoFault) { 977 effAddr = req->getVaddr(); 978 effAddrValid = true; 979 physEffAddr = req->getPaddr(); 980 memReqFlags = req->getFlags(); 981 982 if (req->isCondSwap()) { 983 assert(res); 984 req->setExtraData(*res); 985 } 986#if 0 987 if (cpu->system->memctrl->badaddr(physEffAddr)) { 988 fault = TheISA::genMachineCheckFault(); 989 } else { 990 fault = cpu->write(req, data, sqIdx); 991 } 992#else 993 fault = cpu->write(req, data, sqIdx); 994#endif 995 } else { 996 delete req; 997 } 998 999 return fault; 1000} 1001 1002#endif // __CPU_BASE_DYN_INST_HH__ 1003