base_dyn_inst.hh revision 5714
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_BASE_DYN_INST_HH__ 32#define __CPU_BASE_DYN_INST_HH__ 33 34#include <bitset> 35#include <list> 36#include <string> 37 38#include "arch/faults.hh" 39#include "base/fast_alloc.hh" 40#include "base/trace.hh" 41#include "config/full_system.hh" 42#include "cpu/o3/comm.hh" 43#include "cpu/exetrace.hh" 44#include "cpu/inst_seq.hh" 45#include "cpu/op_class.hh" 46#include "cpu/static_inst.hh" 47#include "mem/packet.hh" 48#include "sim/system.hh" 49 50/** 51 * @file 52 * Defines a dynamic instruction context. 53 */ 54 55// Forward declaration. 56class StaticInstPtr; 57 58template <class Impl> 59class BaseDynInst : public FastAlloc, public RefCounted 60{ 61 public: 62 // Typedef for the CPU. 63 typedef typename Impl::CPUType ImplCPU; 64 typedef typename ImplCPU::ImplState ImplState; 65 66 // Logical register index type. 67 typedef TheISA::RegIndex RegIndex; 68 // Integer register type. 69 typedef TheISA::IntReg IntReg; 70 // Floating point register type. 71 typedef TheISA::FloatReg FloatReg; 72 73 // The DynInstPtr type. 74 typedef typename Impl::DynInstPtr DynInstPtr; 75 76 // The list of instructions iterator type. 77 typedef typename std::list<DynInstPtr>::iterator ListIt; 78 79 enum { 80 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 81 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs 82 }; 83 84 /** The StaticInst used by this BaseDynInst. */ 85 StaticInstPtr staticInst; 86 87 //////////////////////////////////////////// 88 // 89 // INSTRUCTION EXECUTION 90 // 91 //////////////////////////////////////////// 92 /** InstRecord that tracks this instructions. */ 93 Trace::InstRecord *traceData; 94 95 void demapPage(Addr vaddr, uint64_t asn) 96 { 97 cpu->demapPage(vaddr, asn); 98 } 99 void demapInstPage(Addr vaddr, uint64_t asn) 100 { 101 cpu->demapPage(vaddr, asn); 102 } 103 void demapDataPage(Addr vaddr, uint64_t asn) 104 { 105 cpu->demapPage(vaddr, asn); 106 } 107 108 /** 109 * Does a read to a given address. 110 * @param addr The address to read. 111 * @param data The read's data is written into this parameter. 112 * @param flags The request's flags. 113 * @return Returns any fault due to the read. 114 */ 115 template <class T> 116 Fault read(Addr addr, T &data, unsigned flags); 117 118 Fault translateDataReadAddr(Addr vaddr, Addr &paddr, 119 int size, unsigned flags); 120 121 /** 122 * Does a write to a given address. 123 * @param data The data to be written. 124 * @param addr The address to write to. 125 * @param flags The request's flags. 126 * @param res The result of the write (for load locked/store conditionals). 127 * @return Returns any fault due to the write. 128 */ 129 template <class T> 130 Fault write(T data, Addr addr, unsigned flags, 131 uint64_t *res); 132 133 Fault translateDataWriteAddr(Addr vaddr, Addr &paddr, 134 int size, unsigned flags); 135 136 void prefetch(Addr addr, unsigned flags); 137 void writeHint(Addr addr, int size, unsigned flags); 138 Fault copySrcTranslate(Addr src); 139 Fault copy(Addr dest); 140 141 /** @todo: Consider making this private. */ 142 public: 143 /** The sequence number of the instruction. */ 144 InstSeqNum seqNum; 145 146 enum Status { 147 IqEntry, /// Instruction is in the IQ 148 RobEntry, /// Instruction is in the ROB 149 LsqEntry, /// Instruction is in the LSQ 150 Completed, /// Instruction has completed 151 ResultReady, /// Instruction has its result 152 CanIssue, /// Instruction can issue and execute 153 Issued, /// Instruction has issued 154 Executed, /// Instruction has executed 155 CanCommit, /// Instruction can commit 156 AtCommit, /// Instruction has reached commit 157 Committed, /// Instruction has committed 158 Squashed, /// Instruction is squashed 159 SquashedInIQ, /// Instruction is squashed in the IQ 160 SquashedInLSQ, /// Instruction is squashed in the LSQ 161 SquashedInROB, /// Instruction is squashed in the ROB 162 RecoverInst, /// Is a recover instruction 163 BlockingInst, /// Is a blocking instruction 164 ThreadsyncWait, /// Is a thread synchronization instruction 165 SerializeBefore, /// Needs to serialize on 166 /// instructions ahead of it 167 SerializeAfter, /// Needs to serialize instructions behind it 168 SerializeHandled, /// Serialization has been handled 169 NumStatus 170 }; 171 172 /** The status of this BaseDynInst. Several bits can be set. */ 173 std::bitset<NumStatus> status; 174 175 /** The thread this instruction is from. */ 176 short threadNumber; 177 178 /** data address space ID, for loads & stores. */ 179 short asid; 180 181 /** How many source registers are ready. */ 182 unsigned readyRegs; 183 184 /** Pointer to the Impl's CPU object. */ 185 ImplCPU *cpu; 186 187 /** Pointer to the thread state. */ 188 ImplState *thread; 189 190 /** The kind of fault this instruction has generated. */ 191 Fault fault; 192 193 /** Pointer to the data for the memory access. */ 194 uint8_t *memData; 195 196 /** The effective virtual address (lds & stores only). */ 197 Addr effAddr; 198 199 /** Is the effective virtual address valid. */ 200 bool effAddrValid; 201 202 /** The effective physical address. */ 203 Addr physEffAddr; 204 205 /** Effective virtual address for a copy source. */ 206 Addr copySrcEffAddr; 207 208 /** Effective physical address for a copy source. */ 209 Addr copySrcPhysEffAddr; 210 211 /** The memory request flags (from translation). */ 212 unsigned memReqFlags; 213 214 union Result { 215 uint64_t integer; 216// float fp; 217 double dbl; 218 }; 219 220 /** The result of the instruction; assumes for now that there's only one 221 * destination register. 222 */ 223 Result instResult; 224 225 /** Records changes to result? */ 226 bool recordResult; 227 228 /** PC of this instruction. */ 229 Addr PC; 230 231 /** Micro PC of this instruction. */ 232 Addr microPC; 233 234 protected: 235 /** Next non-speculative PC. It is not filled in at fetch, but rather 236 * once the target of the branch is truly known (either decode or 237 * execute). 238 */ 239 Addr nextPC; 240 241 /** Next non-speculative NPC. Target PC for Mips or Sparc. */ 242 Addr nextNPC; 243 244 /** Next non-speculative micro PC. */ 245 Addr nextMicroPC; 246 247 /** Predicted next PC. */ 248 Addr predPC; 249 250 /** Predicted next NPC. */ 251 Addr predNPC; 252 253 /** Predicted next microPC */ 254 Addr predMicroPC; 255 256 /** If this is a branch that was predicted taken */ 257 bool predTaken; 258 259 public: 260 261 /** Count of total number of dynamic instructions. */ 262 static int instcount; 263 264#ifdef DEBUG 265 void dumpSNList(); 266#endif 267 268 /** Whether or not the source register is ready. 269 * @todo: Not sure this should be here vs the derived class. 270 */ 271 bool _readySrcRegIdx[MaxInstSrcRegs]; 272 273 protected: 274 /** Flattened register index of the destination registers of this 275 * instruction. 276 */ 277 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs]; 278 279 /** Flattened register index of the source registers of this 280 * instruction. 281 */ 282 TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs]; 283 284 /** Physical register index of the destination registers of this 285 * instruction. 286 */ 287 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs]; 288 289 /** Physical register index of the source registers of this 290 * instruction. 291 */ 292 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs]; 293 294 /** Physical register index of the previous producers of the 295 * architected destinations. 296 */ 297 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs]; 298 299 public: 300 301 /** Returns the physical register index of the i'th destination 302 * register. 303 */ 304 PhysRegIndex renamedDestRegIdx(int idx) const 305 { 306 return _destRegIdx[idx]; 307 } 308 309 /** Returns the physical register index of the i'th source register. */ 310 PhysRegIndex renamedSrcRegIdx(int idx) const 311 { 312 return _srcRegIdx[idx]; 313 } 314 315 /** Returns the flattened register index of the i'th destination 316 * register. 317 */ 318 TheISA::RegIndex flattenedDestRegIdx(int idx) const 319 { 320 return _flatDestRegIdx[idx]; 321 } 322 323 /** Returns the flattened register index of the i'th source register */ 324 TheISA::RegIndex flattenedSrcRegIdx(int idx) const 325 { 326 return _flatSrcRegIdx[idx]; 327 } 328 329 /** Returns the physical register index of the previous physical register 330 * that remapped to the same logical register index. 331 */ 332 PhysRegIndex prevDestRegIdx(int idx) const 333 { 334 return _prevDestRegIdx[idx]; 335 } 336 337 /** Renames a destination register to a physical register. Also records 338 * the previous physical register that the logical register mapped to. 339 */ 340 void renameDestReg(int idx, 341 PhysRegIndex renamed_dest, 342 PhysRegIndex previous_rename) 343 { 344 _destRegIdx[idx] = renamed_dest; 345 _prevDestRegIdx[idx] = previous_rename; 346 } 347 348 /** Renames a source logical register to the physical register which 349 * has/will produce that logical register's result. 350 * @todo: add in whether or not the source register is ready. 351 */ 352 void renameSrcReg(int idx, PhysRegIndex renamed_src) 353 { 354 _srcRegIdx[idx] = renamed_src; 355 } 356 357 /** Flattens a source architectural register index into a logical index. 358 */ 359 void flattenSrcReg(int idx, TheISA::RegIndex flattened_src) 360 { 361 _flatSrcRegIdx[idx] = flattened_src; 362 } 363 364 /** Flattens a destination architectural register index into a logical 365 * index. 366 */ 367 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 368 { 369 _flatDestRegIdx[idx] = flattened_dest; 370 } 371 /** BaseDynInst constructor given a binary instruction. 372 * @param staticInst A StaticInstPtr to the underlying instruction. 373 * @param PC The PC of the instruction. 374 * @param pred_PC The predicted next PC. 375 * @param pred_NPC The predicted next NPC. 376 * @param seq_num The sequence number of the instruction. 377 * @param cpu Pointer to the instruction's CPU. 378 */ 379 BaseDynInst(StaticInstPtr staticInst, Addr PC, Addr NPC, Addr microPC, 380 Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC, 381 InstSeqNum seq_num, ImplCPU *cpu); 382 383 /** BaseDynInst constructor given a binary instruction. 384 * @param inst The binary instruction. 385 * @param PC The PC of the instruction. 386 * @param pred_PC The predicted next PC. 387 * @param pred_NPC The predicted next NPC. 388 * @param seq_num The sequence number of the instruction. 389 * @param cpu Pointer to the instruction's CPU. 390 */ 391 BaseDynInst(TheISA::ExtMachInst inst, Addr PC, Addr NPC, Addr microPC, 392 Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC, 393 InstSeqNum seq_num, ImplCPU *cpu); 394 395 /** BaseDynInst constructor given a StaticInst pointer. 396 * @param _staticInst The StaticInst for this BaseDynInst. 397 */ 398 BaseDynInst(StaticInstPtr &_staticInst); 399 400 /** BaseDynInst destructor. */ 401 ~BaseDynInst(); 402 403 private: 404 /** Function to initialize variables in the constructors. */ 405 void initVars(); 406 407 public: 408 /** Dumps out contents of this BaseDynInst. */ 409 void dump(); 410 411 /** Dumps out contents of this BaseDynInst into given string. */ 412 void dump(std::string &outstring); 413 414 /** Read this CPU's ID. */ 415 int cpuId() { return cpu->cpuId(); } 416 417 /** Read this context's system-wide ID **/ 418 int contextId() { return thread->contextId(); } 419 420 /** Returns the fault type. */ 421 Fault getFault() { return fault; } 422 423 /** Checks whether or not this instruction has had its branch target 424 * calculated yet. For now it is not utilized and is hacked to be 425 * always false. 426 * @todo: Actually use this instruction. 427 */ 428 bool doneTargCalc() { return false; } 429 430 /** Returns the next PC. This could be the speculative next PC if it is 431 * called prior to the actual branch target being calculated. 432 */ 433 Addr readNextPC() { return nextPC; } 434 435 /** Returns the next NPC. This could be the speculative next NPC if it is 436 * called prior to the actual branch target being calculated. 437 */ 438 Addr readNextNPC() 439 { 440#if ISA_HAS_DELAY_SLOT 441 return nextNPC; 442#else 443 return nextPC + sizeof(TheISA::MachInst); 444#endif 445 } 446 447 Addr readNextMicroPC() 448 { 449 return nextMicroPC; 450 } 451 452 /** Set the predicted target of this current instruction. */ 453 void setPredTarg(Addr predicted_PC, Addr predicted_NPC, 454 Addr predicted_MicroPC) 455 { 456 predPC = predicted_PC; 457 predNPC = predicted_NPC; 458 predMicroPC = predicted_MicroPC; 459 } 460 461 /** Returns the predicted PC immediately after the branch. */ 462 Addr readPredPC() { return predPC; } 463 464 /** Returns the predicted PC two instructions after the branch */ 465 Addr readPredNPC() { return predNPC; } 466 467 /** Returns the predicted micro PC after the branch */ 468 Addr readPredMicroPC() { return predMicroPC; } 469 470 /** Returns whether the instruction was predicted taken or not. */ 471 bool readPredTaken() 472 { 473 return predTaken; 474 } 475 476 void setPredTaken(bool predicted_taken) 477 { 478 predTaken = predicted_taken; 479 } 480 481 /** Returns whether the instruction mispredicted. */ 482 bool mispredicted() 483 { 484 return readPredPC() != readNextPC() || 485 readPredNPC() != readNextNPC() || 486 readPredMicroPC() != readNextMicroPC(); 487 } 488 489 // 490 // Instruction types. Forward checks to StaticInst object. 491 // 492 bool isNop() const { return staticInst->isNop(); } 493 bool isMemRef() const { return staticInst->isMemRef(); } 494 bool isLoad() const { return staticInst->isLoad(); } 495 bool isStore() const { return staticInst->isStore(); } 496 bool isStoreConditional() const 497 { return staticInst->isStoreConditional(); } 498 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 499 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 500 bool isCopy() const { return staticInst->isCopy(); } 501 bool isInteger() const { return staticInst->isInteger(); } 502 bool isFloating() const { return staticInst->isFloating(); } 503 bool isControl() const { return staticInst->isControl(); } 504 bool isCall() const { return staticInst->isCall(); } 505 bool isReturn() const { return staticInst->isReturn(); } 506 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 507 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 508 bool isCondCtrl() const { return staticInst->isCondCtrl(); } 509 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 510 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 511 bool isThreadSync() const { return staticInst->isThreadSync(); } 512 bool isSerializing() const { return staticInst->isSerializing(); } 513 bool isSerializeBefore() const 514 { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 515 bool isSerializeAfter() const 516 { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 517 bool isMemBarrier() const { return staticInst->isMemBarrier(); } 518 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 519 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 520 bool isQuiesce() const { return staticInst->isQuiesce(); } 521 bool isIprAccess() const { return staticInst->isIprAccess(); } 522 bool isUnverifiable() const { return staticInst->isUnverifiable(); } 523 bool isSyscall() const { return staticInst->isSyscall(); } 524 bool isMacroop() const { return staticInst->isMacroop(); } 525 bool isMicroop() const { return staticInst->isMicroop(); } 526 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 527 bool isLastMicroop() const { return staticInst->isLastMicroop(); } 528 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 529 bool isMicroBranch() const { return staticInst->isMicroBranch(); } 530 531 /** Temporarily sets this instruction as a serialize before instruction. */ 532 void setSerializeBefore() { status.set(SerializeBefore); } 533 534 /** Clears the serializeBefore part of this instruction. */ 535 void clearSerializeBefore() { status.reset(SerializeBefore); } 536 537 /** Checks if this serializeBefore is only temporarily set. */ 538 bool isTempSerializeBefore() { return status[SerializeBefore]; } 539 540 /** Temporarily sets this instruction as a serialize after instruction. */ 541 void setSerializeAfter() { status.set(SerializeAfter); } 542 543 /** Clears the serializeAfter part of this instruction.*/ 544 void clearSerializeAfter() { status.reset(SerializeAfter); } 545 546 /** Checks if this serializeAfter is only temporarily set. */ 547 bool isTempSerializeAfter() { return status[SerializeAfter]; } 548 549 /** Sets the serialization part of this instruction as handled. */ 550 void setSerializeHandled() { status.set(SerializeHandled); } 551 552 /** Checks if the serialization part of this instruction has been 553 * handled. This does not apply to the temporary serializing 554 * state; it only applies to this instruction's own permanent 555 * serializing state. 556 */ 557 bool isSerializeHandled() { return status[SerializeHandled]; } 558 559 /** Returns the opclass of this instruction. */ 560 OpClass opClass() const { return staticInst->opClass(); } 561 562 /** Returns the branch target address. */ 563 Addr branchTarget() const { return staticInst->branchTarget(PC); } 564 565 /** Returns the number of source registers. */ 566 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 567 568 /** Returns the number of destination registers. */ 569 int8_t numDestRegs() const { return staticInst->numDestRegs(); } 570 571 // the following are used to track physical register usage 572 // for machines with separate int & FP reg files 573 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 574 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 575 576 /** Returns the logical register index of the i'th destination register. */ 577 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 578 579 /** Returns the logical register index of the i'th source register. */ 580 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 581 582 /** Returns the result of an integer instruction. */ 583 uint64_t readIntResult() { return instResult.integer; } 584 585 /** Returns the result of a floating point instruction. */ 586 float readFloatResult() { return (float)instResult.dbl; } 587 588 /** Returns the result of a floating point (double) instruction. */ 589 double readDoubleResult() { return instResult.dbl; } 590 591 /** Records an integer register being set to a value. */ 592 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 593 { 594 if (recordResult) 595 instResult.integer = val; 596 } 597 598 /** Records an fp register being set to a value. */ 599 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 600 int width) 601 { 602 if (recordResult) { 603 if (width == 32) 604 instResult.dbl = (double)val; 605 else if (width == 64) 606 instResult.dbl = val; 607 else 608 panic("Unsupported width!"); 609 } 610 } 611 612 /** Records an fp register being set to a value. */ 613 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 614 { 615 if (recordResult) 616 instResult.dbl = (double)val; 617 } 618 619 /** Records an fp register being set to an integer value. */ 620 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val, 621 int width) 622 { 623 if (recordResult) 624 instResult.integer = val; 625 } 626 627 /** Records an fp register being set to an integer value. */ 628 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val) 629 { 630 if (recordResult) 631 instResult.integer = val; 632 } 633 634 /** Records that one of the source registers is ready. */ 635 void markSrcRegReady(); 636 637 /** Marks a specific register as ready. */ 638 void markSrcRegReady(RegIndex src_idx); 639 640 /** Returns if a source register is ready. */ 641 bool isReadySrcRegIdx(int idx) const 642 { 643 return this->_readySrcRegIdx[idx]; 644 } 645 646 /** Sets this instruction as completed. */ 647 void setCompleted() { status.set(Completed); } 648 649 /** Returns whether or not this instruction is completed. */ 650 bool isCompleted() const { return status[Completed]; } 651 652 /** Marks the result as ready. */ 653 void setResultReady() { status.set(ResultReady); } 654 655 /** Returns whether or not the result is ready. */ 656 bool isResultReady() const { return status[ResultReady]; } 657 658 /** Sets this instruction as ready to issue. */ 659 void setCanIssue() { status.set(CanIssue); } 660 661 /** Returns whether or not this instruction is ready to issue. */ 662 bool readyToIssue() const { return status[CanIssue]; } 663 664 /** Clears this instruction being able to issue. */ 665 void clearCanIssue() { status.reset(CanIssue); } 666 667 /** Sets this instruction as issued from the IQ. */ 668 void setIssued() { status.set(Issued); } 669 670 /** Returns whether or not this instruction has issued. */ 671 bool isIssued() const { return status[Issued]; } 672 673 /** Clears this instruction as being issued. */ 674 void clearIssued() { status.reset(Issued); } 675 676 /** Sets this instruction as executed. */ 677 void setExecuted() { status.set(Executed); } 678 679 /** Returns whether or not this instruction has executed. */ 680 bool isExecuted() const { return status[Executed]; } 681 682 /** Sets this instruction as ready to commit. */ 683 void setCanCommit() { status.set(CanCommit); } 684 685 /** Clears this instruction as being ready to commit. */ 686 void clearCanCommit() { status.reset(CanCommit); } 687 688 /** Returns whether or not this instruction is ready to commit. */ 689 bool readyToCommit() const { return status[CanCommit]; } 690 691 void setAtCommit() { status.set(AtCommit); } 692 693 bool isAtCommit() { return status[AtCommit]; } 694 695 /** Sets this instruction as committed. */ 696 void setCommitted() { status.set(Committed); } 697 698 /** Returns whether or not this instruction is committed. */ 699 bool isCommitted() const { return status[Committed]; } 700 701 /** Sets this instruction as squashed. */ 702 void setSquashed() { status.set(Squashed); } 703 704 /** Returns whether or not this instruction is squashed. */ 705 bool isSquashed() const { return status[Squashed]; } 706 707 //Instruction Queue Entry 708 //----------------------- 709 /** Sets this instruction as a entry the IQ. */ 710 void setInIQ() { status.set(IqEntry); } 711 712 /** Sets this instruction as a entry the IQ. */ 713 void clearInIQ() { status.reset(IqEntry); } 714 715 /** Returns whether or not this instruction has issued. */ 716 bool isInIQ() const { return status[IqEntry]; } 717 718 /** Sets this instruction as squashed in the IQ. */ 719 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 720 721 /** Returns whether or not this instruction is squashed in the IQ. */ 722 bool isSquashedInIQ() const { return status[SquashedInIQ]; } 723 724 725 //Load / Store Queue Functions 726 //----------------------- 727 /** Sets this instruction as a entry the LSQ. */ 728 void setInLSQ() { status.set(LsqEntry); } 729 730 /** Sets this instruction as a entry the LSQ. */ 731 void removeInLSQ() { status.reset(LsqEntry); } 732 733 /** Returns whether or not this instruction is in the LSQ. */ 734 bool isInLSQ() const { return status[LsqEntry]; } 735 736 /** Sets this instruction as squashed in the LSQ. */ 737 void setSquashedInLSQ() { status.set(SquashedInLSQ);} 738 739 /** Returns whether or not this instruction is squashed in the LSQ. */ 740 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 741 742 743 //Reorder Buffer Functions 744 //----------------------- 745 /** Sets this instruction as a entry the ROB. */ 746 void setInROB() { status.set(RobEntry); } 747 748 /** Sets this instruction as a entry the ROB. */ 749 void clearInROB() { status.reset(RobEntry); } 750 751 /** Returns whether or not this instruction is in the ROB. */ 752 bool isInROB() const { return status[RobEntry]; } 753 754 /** Sets this instruction as squashed in the ROB. */ 755 void setSquashedInROB() { status.set(SquashedInROB); } 756 757 /** Returns whether or not this instruction is squashed in the ROB. */ 758 bool isSquashedInROB() const { return status[SquashedInROB]; } 759 760 /** Read the PC of this instruction. */ 761 const Addr readPC() const { return PC; } 762 763 /**Read the micro PC of this instruction. */ 764 const Addr readMicroPC() const { return microPC; } 765 766 /** Set the next PC of this instruction (its actual target). */ 767 void setNextPC(Addr val) 768 { 769 nextPC = val; 770 } 771 772 /** Set the next NPC of this instruction (the target in Mips or Sparc).*/ 773 void setNextNPC(Addr val) 774 { 775#if ISA_HAS_DELAY_SLOT 776 nextNPC = val; 777#endif 778 } 779 780 void setNextMicroPC(Addr val) 781 { 782 nextMicroPC = val; 783 } 784 785 /** Sets the ASID. */ 786 void setASID(short addr_space_id) { asid = addr_space_id; } 787 788 /** Sets the thread id. */ 789 void setTid(unsigned tid) { threadNumber = tid; } 790 791 /** Sets the pointer to the thread state. */ 792 void setThreadState(ImplState *state) { thread = state; } 793 794 /** Returns the thread context. */ 795 ThreadContext *tcBase() { return thread->getTC(); } 796 797 private: 798 /** Instruction effective address. 799 * @todo: Consider if this is necessary or not. 800 */ 801 Addr instEffAddr; 802 803 /** Whether or not the effective address calculation is completed. 804 * @todo: Consider if this is necessary or not. 805 */ 806 bool eaCalcDone; 807 808 /** Is this instruction's memory access uncacheable. */ 809 bool isUncacheable; 810 811 /** Has this instruction generated a memory request. */ 812 bool reqMade; 813 814 public: 815 /** Sets the effective address. */ 816 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 817 818 /** Returns the effective address. */ 819 const Addr &getEA() const { return instEffAddr; } 820 821 /** Returns whether or not the eff. addr. calculation has been completed. */ 822 bool doneEACalc() { return eaCalcDone; } 823 824 /** Returns whether or not the eff. addr. source registers are ready. */ 825 bool eaSrcsReady(); 826 827 /** Whether or not the memory operation is done. */ 828 bool memOpDone; 829 830 /** Is this instruction's memory access uncacheable. */ 831 bool uncacheable() { return isUncacheable; } 832 833 /** Has this instruction generated a memory request. */ 834 bool hasRequest() { return reqMade; } 835 836 public: 837 /** Load queue index. */ 838 int16_t lqIdx; 839 840 /** Store queue index. */ 841 int16_t sqIdx; 842 843 /** Iterator pointing to this BaseDynInst in the list of all insts. */ 844 ListIt instListIt; 845 846 /** Returns iterator to this instruction in the list of all insts. */ 847 ListIt &getInstListIt() { return instListIt; } 848 849 /** Sets iterator for this instruction in the list of all insts. */ 850 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 851 852 public: 853 /** Returns the number of consecutive store conditional failures. */ 854 unsigned readStCondFailures() 855 { return thread->storeCondFailures; } 856 857 /** Sets the number of consecutive store conditional failures. */ 858 void setStCondFailures(unsigned sc_failures) 859 { thread->storeCondFailures = sc_failures; } 860}; 861 862template<class Impl> 863Fault 864BaseDynInst<Impl>::translateDataReadAddr(Addr vaddr, Addr &paddr, 865 int size, unsigned flags) 866{ 867 if (traceData) { 868 traceData->setAddr(vaddr); 869 } 870 871 reqMade = true; 872 Request *req = new Request(); 873 req->setVirt(asid, vaddr, size, flags, PC); 874 req->setThreadContext(thread->contextId(), threadNumber); 875 876 fault = cpu->translateDataReadReq(req, thread); 877 878 if (fault == NoFault) 879 paddr = req->getPaddr(); 880 881 delete req; 882 return fault; 883} 884 885template<class Impl> 886template<class T> 887inline Fault 888BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) 889{ 890 reqMade = true; 891 Request *req = new Request(); 892 req->setVirt(asid, addr, sizeof(T), flags, this->PC); 893 req->setThreadContext(thread->contextId(), threadNumber); 894 895 fault = cpu->translateDataReadReq(req, thread); 896 897 if (req->isUncacheable()) 898 isUncacheable = true; 899 900 if (fault == NoFault) { 901 effAddr = req->getVaddr(); 902 effAddrValid = true; 903 physEffAddr = req->getPaddr(); 904 memReqFlags = req->getFlags(); 905 906#if 0 907 if (cpu->system->memctrl->badaddr(physEffAddr)) { 908 fault = TheISA::genMachineCheckFault(); 909 data = (T)-1; 910 this->setExecuted(); 911 } else { 912 fault = cpu->read(req, data, lqIdx); 913 } 914#else 915 fault = cpu->read(req, data, lqIdx); 916#endif 917 } else { 918 // Return a fixed value to keep simulation deterministic even 919 // along misspeculated paths. 920 data = (T)-1; 921 922 // Commit will have to clean up whatever happened. Set this 923 // instruction as executed. 924 this->setExecuted(); 925 delete req; 926 } 927 928 if (traceData) { 929 traceData->setAddr(addr); 930 traceData->setData(data); 931 } 932 933 return fault; 934} 935 936template<class Impl> 937Fault 938BaseDynInst<Impl>::translateDataWriteAddr(Addr vaddr, Addr &paddr, 939 int size, unsigned flags) 940{ 941 if (traceData) { 942 traceData->setAddr(vaddr); 943 } 944 945 reqMade = true; 946 Request *req = new Request(); 947 req->setVirt(asid, vaddr, size, flags, PC); 948 req->setThreadContext(thread->contextId(), threadNumber); 949 950 fault = cpu->translateDataWriteReq(req, thread); 951 952 if (fault == NoFault) 953 paddr = req->getPaddr(); 954 955 delete req; 956 return fault; 957} 958 959template<class Impl> 960template<class T> 961inline Fault 962BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) 963{ 964 if (traceData) { 965 traceData->setAddr(addr); 966 traceData->setData(data); 967 } 968 969 reqMade = true; 970 Request *req = new Request(); 971 req->setVirt(asid, addr, sizeof(T), flags, this->PC); 972 req->setThreadContext(thread->contextId(), threadNumber); 973 974 fault = cpu->translateDataWriteReq(req, thread); 975 976 if (req->isUncacheable()) 977 isUncacheable = true; 978 979 if (fault == NoFault) { 980 effAddr = req->getVaddr(); 981 effAddrValid = true; 982 physEffAddr = req->getPaddr(); 983 memReqFlags = req->getFlags(); 984 985 if (req->isCondSwap()) { 986 assert(res); 987 req->setExtraData(*res); 988 } 989#if 0 990 if (cpu->system->memctrl->badaddr(physEffAddr)) { 991 fault = TheISA::genMachineCheckFault(); 992 } else { 993 fault = cpu->write(req, data, sqIdx); 994 } 995#else 996 fault = cpu->write(req, data, sqIdx); 997#endif 998 } else { 999 delete req; 1000 } 1001 1002 return fault; 1003} 1004 1005#endif // __CPU_BASE_DYN_INST_HH__ 1006