base_dyn_inst.hh revision 5712
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_BASE_DYN_INST_HH__ 32#define __CPU_BASE_DYN_INST_HH__ 33 34#include <bitset> 35#include <list> 36#include <string> 37 38#include "arch/faults.hh" 39#include "base/fast_alloc.hh" 40#include "base/trace.hh" 41#include "config/full_system.hh" 42#include "cpu/o3/comm.hh" 43#include "cpu/exetrace.hh" 44#include "cpu/inst_seq.hh" 45#include "cpu/op_class.hh" 46#include "cpu/static_inst.hh" 47#include "mem/packet.hh" 48#include "sim/system.hh" 49 50/** 51 * @file 52 * Defines a dynamic instruction context. 53 */ 54 55// Forward declaration. 56class StaticInstPtr; 57 58template <class Impl> 59class BaseDynInst : public FastAlloc, public RefCounted 60{ 61 public: 62 // Typedef for the CPU. 63 typedef typename Impl::CPUType ImplCPU; 64 typedef typename ImplCPU::ImplState ImplState; 65 66 // Logical register index type. 67 typedef TheISA::RegIndex RegIndex; 68 // Integer register type. 69 typedef TheISA::IntReg IntReg; 70 // Floating point register type. 71 typedef TheISA::FloatReg FloatReg; 72 73 // The DynInstPtr type. 74 typedef typename Impl::DynInstPtr DynInstPtr; 75 76 // The list of instructions iterator type. 77 typedef typename std::list<DynInstPtr>::iterator ListIt; 78 79 enum { 80 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 81 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs 82 }; 83 84 /** The StaticInst used by this BaseDynInst. */ 85 StaticInstPtr staticInst; 86 87 //////////////////////////////////////////// 88 // 89 // INSTRUCTION EXECUTION 90 // 91 //////////////////////////////////////////// 92 /** InstRecord that tracks this instructions. */ 93 Trace::InstRecord *traceData; 94 95 void demapPage(Addr vaddr, uint64_t asn) 96 { 97 cpu->demapPage(vaddr, asn); 98 } 99 void demapInstPage(Addr vaddr, uint64_t asn) 100 { 101 cpu->demapPage(vaddr, asn); 102 } 103 void demapDataPage(Addr vaddr, uint64_t asn) 104 { 105 cpu->demapPage(vaddr, asn); 106 } 107 108 /** 109 * Does a read to a given address. 110 * @param addr The address to read. 111 * @param data The read's data is written into this parameter. 112 * @param flags The request's flags. 113 * @return Returns any fault due to the read. 114 */ 115 template <class T> 116 Fault read(Addr addr, T &data, unsigned flags); 117 118 Fault translateDataReadAddr(Addr vaddr, Addr &paddr, 119 int size, unsigned flags); 120 121 /** 122 * Does a write to a given address. 123 * @param data The data to be written. 124 * @param addr The address to write to. 125 * @param flags The request's flags. 126 * @param res The result of the write (for load locked/store conditionals). 127 * @return Returns any fault due to the write. 128 */ 129 template <class T> 130 Fault write(T data, Addr addr, unsigned flags, 131 uint64_t *res); 132 133 Fault translateDataWriteAddr(Addr vaddr, Addr &paddr, 134 int size, unsigned flags); 135 136 void prefetch(Addr addr, unsigned flags); 137 void writeHint(Addr addr, int size, unsigned flags); 138 Fault copySrcTranslate(Addr src); 139 Fault copy(Addr dest); 140 141 /** @todo: Consider making this private. */ 142 public: 143 /** The sequence number of the instruction. */ 144 InstSeqNum seqNum; 145 146 enum Status { 147 IqEntry, /// Instruction is in the IQ 148 RobEntry, /// Instruction is in the ROB 149 LsqEntry, /// Instruction is in the LSQ 150 Completed, /// Instruction has completed 151 ResultReady, /// Instruction has its result 152 CanIssue, /// Instruction can issue and execute 153 Issued, /// Instruction has issued 154 Executed, /// Instruction has executed 155 CanCommit, /// Instruction can commit 156 AtCommit, /// Instruction has reached commit 157 Committed, /// Instruction has committed 158 Squashed, /// Instruction is squashed 159 SquashedInIQ, /// Instruction is squashed in the IQ 160 SquashedInLSQ, /// Instruction is squashed in the LSQ 161 SquashedInROB, /// Instruction is squashed in the ROB 162 RecoverInst, /// Is a recover instruction 163 BlockingInst, /// Is a blocking instruction 164 ThreadsyncWait, /// Is a thread synchronization instruction 165 SerializeBefore, /// Needs to serialize on 166 /// instructions ahead of it 167 SerializeAfter, /// Needs to serialize instructions behind it 168 SerializeHandled, /// Serialization has been handled 169 NumStatus 170 }; 171 172 /** The status of this BaseDynInst. Several bits can be set. */ 173 std::bitset<NumStatus> status; 174 175 /** The thread this instruction is from. */ 176 short threadNumber; 177 178 /** data address space ID, for loads & stores. */ 179 short asid; 180 181 /** How many source registers are ready. */ 182 unsigned readyRegs; 183 184 /** Pointer to the Impl's CPU object. */ 185 ImplCPU *cpu; 186 187 /** Pointer to the thread state. */ 188 ImplState *thread; 189 190 /** The kind of fault this instruction has generated. */ 191 Fault fault; 192 193 /** Pointer to the data for the memory access. */ 194 uint8_t *memData; 195 196 /** The effective virtual address (lds & stores only). */ 197 Addr effAddr; 198 199 /** Is the effective virtual address valid. */ 200 bool effAddrValid; 201 202 /** The effective physical address. */ 203 Addr physEffAddr; 204 205 /** Effective virtual address for a copy source. */ 206 Addr copySrcEffAddr; 207 208 /** Effective physical address for a copy source. */ 209 Addr copySrcPhysEffAddr; 210 211 /** The memory request flags (from translation). */ 212 unsigned memReqFlags; 213 214 union Result { 215 uint64_t integer; 216// float fp; 217 double dbl; 218 }; 219 220 /** The result of the instruction; assumes for now that there's only one 221 * destination register. 222 */ 223 Result instResult; 224 225 /** Records changes to result? */ 226 bool recordResult; 227 228 /** PC of this instruction. */ 229 Addr PC; 230 231 /** Micro PC of this instruction. */ 232 Addr microPC; 233 234 protected: 235 /** Next non-speculative PC. It is not filled in at fetch, but rather 236 * once the target of the branch is truly known (either decode or 237 * execute). 238 */ 239 Addr nextPC; 240 241 /** Next non-speculative NPC. Target PC for Mips or Sparc. */ 242 Addr nextNPC; 243 244 /** Next non-speculative micro PC. */ 245 Addr nextMicroPC; 246 247 /** Predicted next PC. */ 248 Addr predPC; 249 250 /** Predicted next NPC. */ 251 Addr predNPC; 252 253 /** Predicted next microPC */ 254 Addr predMicroPC; 255 256 /** If this is a branch that was predicted taken */ 257 bool predTaken; 258 259 public: 260 261 /** Count of total number of dynamic instructions. */ 262 static int instcount; 263 264#ifdef DEBUG 265 void dumpSNList(); 266#endif 267 268 /** Whether or not the source register is ready. 269 * @todo: Not sure this should be here vs the derived class. 270 */ 271 bool _readySrcRegIdx[MaxInstSrcRegs]; 272 273 protected: 274 /** Flattened register index of the destination registers of this 275 * instruction. 276 */ 277 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs]; 278 279 /** Flattened register index of the source registers of this 280 * instruction. 281 */ 282 TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs]; 283 284 /** Physical register index of the destination registers of this 285 * instruction. 286 */ 287 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs]; 288 289 /** Physical register index of the source registers of this 290 * instruction. 291 */ 292 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs]; 293 294 /** Physical register index of the previous producers of the 295 * architected destinations. 296 */ 297 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs]; 298 299 public: 300 301 /** Returns the physical register index of the i'th destination 302 * register. 303 */ 304 PhysRegIndex renamedDestRegIdx(int idx) const 305 { 306 return _destRegIdx[idx]; 307 } 308 309 /** Returns the physical register index of the i'th source register. */ 310 PhysRegIndex renamedSrcRegIdx(int idx) const 311 { 312 return _srcRegIdx[idx]; 313 } 314 315 /** Returns the flattened register index of the i'th destination 316 * register. 317 */ 318 TheISA::RegIndex flattenedDestRegIdx(int idx) const 319 { 320 return _flatDestRegIdx[idx]; 321 } 322 323 /** Returns the flattened register index of the i'th source register */ 324 TheISA::RegIndex flattenedSrcRegIdx(int idx) const 325 { 326 return _flatSrcRegIdx[idx]; 327 } 328 329 /** Returns the physical register index of the previous physical register 330 * that remapped to the same logical register index. 331 */ 332 PhysRegIndex prevDestRegIdx(int idx) const 333 { 334 return _prevDestRegIdx[idx]; 335 } 336 337 /** Renames a destination register to a physical register. Also records 338 * the previous physical register that the logical register mapped to. 339 */ 340 void renameDestReg(int idx, 341 PhysRegIndex renamed_dest, 342 PhysRegIndex previous_rename) 343 { 344 _destRegIdx[idx] = renamed_dest; 345 _prevDestRegIdx[idx] = previous_rename; 346 } 347 348 /** Renames a source logical register to the physical register which 349 * has/will produce that logical register's result. 350 * @todo: add in whether or not the source register is ready. 351 */ 352 void renameSrcReg(int idx, PhysRegIndex renamed_src) 353 { 354 _srcRegIdx[idx] = renamed_src; 355 } 356 357 /** Flattens a source architectural register index into a logical index. 358 */ 359 void flattenSrcReg(int idx, TheISA::RegIndex flattened_src) 360 { 361 _flatSrcRegIdx[idx] = flattened_src; 362 } 363 364 /** Flattens a destination architectural register index into a logical 365 * index. 366 */ 367 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 368 { 369 _flatDestRegIdx[idx] = flattened_dest; 370 } 371 /** BaseDynInst constructor given a binary instruction. 372 * @param staticInst A StaticInstPtr to the underlying instruction. 373 * @param PC The PC of the instruction. 374 * @param pred_PC The predicted next PC. 375 * @param pred_NPC The predicted next NPC. 376 * @param seq_num The sequence number of the instruction. 377 * @param cpu Pointer to the instruction's CPU. 378 */ 379 BaseDynInst(StaticInstPtr staticInst, Addr PC, Addr NPC, Addr microPC, 380 Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC, 381 InstSeqNum seq_num, ImplCPU *cpu); 382 383 /** BaseDynInst constructor given a binary instruction. 384 * @param inst The binary instruction. 385 * @param PC The PC of the instruction. 386 * @param pred_PC The predicted next PC. 387 * @param pred_NPC The predicted next NPC. 388 * @param seq_num The sequence number of the instruction. 389 * @param cpu Pointer to the instruction's CPU. 390 */ 391 BaseDynInst(TheISA::ExtMachInst inst, Addr PC, Addr NPC, Addr microPC, 392 Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC, 393 InstSeqNum seq_num, ImplCPU *cpu); 394 395 /** BaseDynInst constructor given a StaticInst pointer. 396 * @param _staticInst The StaticInst for this BaseDynInst. 397 */ 398 BaseDynInst(StaticInstPtr &_staticInst); 399 400 /** BaseDynInst destructor. */ 401 ~BaseDynInst(); 402 403 private: 404 /** Function to initialize variables in the constructors. */ 405 void initVars(); 406 407 public: 408 /** Dumps out contents of this BaseDynInst. */ 409 void dump(); 410 411 /** Dumps out contents of this BaseDynInst into given string. */ 412 void dump(std::string &outstring); 413 414 /** Read this CPU's ID. */ 415 int cpuId() { return cpu->cpuId(); } 416 417 /** Returns the fault type. */ 418 Fault getFault() { return fault; } 419 420 /** Checks whether or not this instruction has had its branch target 421 * calculated yet. For now it is not utilized and is hacked to be 422 * always false. 423 * @todo: Actually use this instruction. 424 */ 425 bool doneTargCalc() { return false; } 426 427 /** Returns the next PC. This could be the speculative next PC if it is 428 * called prior to the actual branch target being calculated. 429 */ 430 Addr readNextPC() { return nextPC; } 431 432 /** Returns the next NPC. This could be the speculative next NPC if it is 433 * called prior to the actual branch target being calculated. 434 */ 435 Addr readNextNPC() 436 { 437#if ISA_HAS_DELAY_SLOT 438 return nextNPC; 439#else 440 return nextPC + sizeof(TheISA::MachInst); 441#endif 442 } 443 444 Addr readNextMicroPC() 445 { 446 return nextMicroPC; 447 } 448 449 /** Set the predicted target of this current instruction. */ 450 void setPredTarg(Addr predicted_PC, Addr predicted_NPC, 451 Addr predicted_MicroPC) 452 { 453 predPC = predicted_PC; 454 predNPC = predicted_NPC; 455 predMicroPC = predicted_MicroPC; 456 } 457 458 /** Returns the predicted PC immediately after the branch. */ 459 Addr readPredPC() { return predPC; } 460 461 /** Returns the predicted PC two instructions after the branch */ 462 Addr readPredNPC() { return predNPC; } 463 464 /** Returns the predicted micro PC after the branch */ 465 Addr readPredMicroPC() { return predMicroPC; } 466 467 /** Returns whether the instruction was predicted taken or not. */ 468 bool readPredTaken() 469 { 470 return predTaken; 471 } 472 473 void setPredTaken(bool predicted_taken) 474 { 475 predTaken = predicted_taken; 476 } 477 478 /** Returns whether the instruction mispredicted. */ 479 bool mispredicted() 480 { 481 return readPredPC() != readNextPC() || 482 readPredNPC() != readNextNPC() || 483 readPredMicroPC() != readNextMicroPC(); 484 } 485 486 // 487 // Instruction types. Forward checks to StaticInst object. 488 // 489 bool isNop() const { return staticInst->isNop(); } 490 bool isMemRef() const { return staticInst->isMemRef(); } 491 bool isLoad() const { return staticInst->isLoad(); } 492 bool isStore() const { return staticInst->isStore(); } 493 bool isStoreConditional() const 494 { return staticInst->isStoreConditional(); } 495 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 496 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 497 bool isCopy() const { return staticInst->isCopy(); } 498 bool isInteger() const { return staticInst->isInteger(); } 499 bool isFloating() const { return staticInst->isFloating(); } 500 bool isControl() const { return staticInst->isControl(); } 501 bool isCall() const { return staticInst->isCall(); } 502 bool isReturn() const { return staticInst->isReturn(); } 503 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 504 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 505 bool isCondCtrl() const { return staticInst->isCondCtrl(); } 506 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 507 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 508 bool isThreadSync() const { return staticInst->isThreadSync(); } 509 bool isSerializing() const { return staticInst->isSerializing(); } 510 bool isSerializeBefore() const 511 { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 512 bool isSerializeAfter() const 513 { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 514 bool isMemBarrier() const { return staticInst->isMemBarrier(); } 515 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 516 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 517 bool isQuiesce() const { return staticInst->isQuiesce(); } 518 bool isIprAccess() const { return staticInst->isIprAccess(); } 519 bool isUnverifiable() const { return staticInst->isUnverifiable(); } 520 bool isSyscall() const { return staticInst->isSyscall(); } 521 bool isMacroop() const { return staticInst->isMacroop(); } 522 bool isMicroop() const { return staticInst->isMicroop(); } 523 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 524 bool isLastMicroop() const { return staticInst->isLastMicroop(); } 525 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 526 bool isMicroBranch() const { return staticInst->isMicroBranch(); } 527 528 /** Temporarily sets this instruction as a serialize before instruction. */ 529 void setSerializeBefore() { status.set(SerializeBefore); } 530 531 /** Clears the serializeBefore part of this instruction. */ 532 void clearSerializeBefore() { status.reset(SerializeBefore); } 533 534 /** Checks if this serializeBefore is only temporarily set. */ 535 bool isTempSerializeBefore() { return status[SerializeBefore]; } 536 537 /** Temporarily sets this instruction as a serialize after instruction. */ 538 void setSerializeAfter() { status.set(SerializeAfter); } 539 540 /** Clears the serializeAfter part of this instruction.*/ 541 void clearSerializeAfter() { status.reset(SerializeAfter); } 542 543 /** Checks if this serializeAfter is only temporarily set. */ 544 bool isTempSerializeAfter() { return status[SerializeAfter]; } 545 546 /** Sets the serialization part of this instruction as handled. */ 547 void setSerializeHandled() { status.set(SerializeHandled); } 548 549 /** Checks if the serialization part of this instruction has been 550 * handled. This does not apply to the temporary serializing 551 * state; it only applies to this instruction's own permanent 552 * serializing state. 553 */ 554 bool isSerializeHandled() { return status[SerializeHandled]; } 555 556 /** Returns the opclass of this instruction. */ 557 OpClass opClass() const { return staticInst->opClass(); } 558 559 /** Returns the branch target address. */ 560 Addr branchTarget() const { return staticInst->branchTarget(PC); } 561 562 /** Returns the number of source registers. */ 563 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 564 565 /** Returns the number of destination registers. */ 566 int8_t numDestRegs() const { return staticInst->numDestRegs(); } 567 568 // the following are used to track physical register usage 569 // for machines with separate int & FP reg files 570 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 571 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 572 573 /** Returns the logical register index of the i'th destination register. */ 574 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 575 576 /** Returns the logical register index of the i'th source register. */ 577 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 578 579 /** Returns the result of an integer instruction. */ 580 uint64_t readIntResult() { return instResult.integer; } 581 582 /** Returns the result of a floating point instruction. */ 583 float readFloatResult() { return (float)instResult.dbl; } 584 585 /** Returns the result of a floating point (double) instruction. */ 586 double readDoubleResult() { return instResult.dbl; } 587 588 /** Records an integer register being set to a value. */ 589 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 590 { 591 if (recordResult) 592 instResult.integer = val; 593 } 594 595 /** Records an fp register being set to a value. */ 596 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 597 int width) 598 { 599 if (recordResult) { 600 if (width == 32) 601 instResult.dbl = (double)val; 602 else if (width == 64) 603 instResult.dbl = val; 604 else 605 panic("Unsupported width!"); 606 } 607 } 608 609 /** Records an fp register being set to a value. */ 610 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 611 { 612 if (recordResult) 613 instResult.dbl = (double)val; 614 } 615 616 /** Records an fp register being set to an integer value. */ 617 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val, 618 int width) 619 { 620 if (recordResult) 621 instResult.integer = val; 622 } 623 624 /** Records an fp register being set to an integer value. */ 625 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val) 626 { 627 if (recordResult) 628 instResult.integer = val; 629 } 630 631 /** Records that one of the source registers is ready. */ 632 void markSrcRegReady(); 633 634 /** Marks a specific register as ready. */ 635 void markSrcRegReady(RegIndex src_idx); 636 637 /** Returns if a source register is ready. */ 638 bool isReadySrcRegIdx(int idx) const 639 { 640 return this->_readySrcRegIdx[idx]; 641 } 642 643 /** Sets this instruction as completed. */ 644 void setCompleted() { status.set(Completed); } 645 646 /** Returns whether or not this instruction is completed. */ 647 bool isCompleted() const { return status[Completed]; } 648 649 /** Marks the result as ready. */ 650 void setResultReady() { status.set(ResultReady); } 651 652 /** Returns whether or not the result is ready. */ 653 bool isResultReady() const { return status[ResultReady]; } 654 655 /** Sets this instruction as ready to issue. */ 656 void setCanIssue() { status.set(CanIssue); } 657 658 /** Returns whether or not this instruction is ready to issue. */ 659 bool readyToIssue() const { return status[CanIssue]; } 660 661 /** Clears this instruction being able to issue. */ 662 void clearCanIssue() { status.reset(CanIssue); } 663 664 /** Sets this instruction as issued from the IQ. */ 665 void setIssued() { status.set(Issued); } 666 667 /** Returns whether or not this instruction has issued. */ 668 bool isIssued() const { return status[Issued]; } 669 670 /** Clears this instruction as being issued. */ 671 void clearIssued() { status.reset(Issued); } 672 673 /** Sets this instruction as executed. */ 674 void setExecuted() { status.set(Executed); } 675 676 /** Returns whether or not this instruction has executed. */ 677 bool isExecuted() const { return status[Executed]; } 678 679 /** Sets this instruction as ready to commit. */ 680 void setCanCommit() { status.set(CanCommit); } 681 682 /** Clears this instruction as being ready to commit. */ 683 void clearCanCommit() { status.reset(CanCommit); } 684 685 /** Returns whether or not this instruction is ready to commit. */ 686 bool readyToCommit() const { return status[CanCommit]; } 687 688 void setAtCommit() { status.set(AtCommit); } 689 690 bool isAtCommit() { return status[AtCommit]; } 691 692 /** Sets this instruction as committed. */ 693 void setCommitted() { status.set(Committed); } 694 695 /** Returns whether or not this instruction is committed. */ 696 bool isCommitted() const { return status[Committed]; } 697 698 /** Sets this instruction as squashed. */ 699 void setSquashed() { status.set(Squashed); } 700 701 /** Returns whether or not this instruction is squashed. */ 702 bool isSquashed() const { return status[Squashed]; } 703 704 //Instruction Queue Entry 705 //----------------------- 706 /** Sets this instruction as a entry the IQ. */ 707 void setInIQ() { status.set(IqEntry); } 708 709 /** Sets this instruction as a entry the IQ. */ 710 void clearInIQ() { status.reset(IqEntry); } 711 712 /** Returns whether or not this instruction has issued. */ 713 bool isInIQ() const { return status[IqEntry]; } 714 715 /** Sets this instruction as squashed in the IQ. */ 716 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 717 718 /** Returns whether or not this instruction is squashed in the IQ. */ 719 bool isSquashedInIQ() const { return status[SquashedInIQ]; } 720 721 722 //Load / Store Queue Functions 723 //----------------------- 724 /** Sets this instruction as a entry the LSQ. */ 725 void setInLSQ() { status.set(LsqEntry); } 726 727 /** Sets this instruction as a entry the LSQ. */ 728 void removeInLSQ() { status.reset(LsqEntry); } 729 730 /** Returns whether or not this instruction is in the LSQ. */ 731 bool isInLSQ() const { return status[LsqEntry]; } 732 733 /** Sets this instruction as squashed in the LSQ. */ 734 void setSquashedInLSQ() { status.set(SquashedInLSQ);} 735 736 /** Returns whether or not this instruction is squashed in the LSQ. */ 737 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 738 739 740 //Reorder Buffer Functions 741 //----------------------- 742 /** Sets this instruction as a entry the ROB. */ 743 void setInROB() { status.set(RobEntry); } 744 745 /** Sets this instruction as a entry the ROB. */ 746 void clearInROB() { status.reset(RobEntry); } 747 748 /** Returns whether or not this instruction is in the ROB. */ 749 bool isInROB() const { return status[RobEntry]; } 750 751 /** Sets this instruction as squashed in the ROB. */ 752 void setSquashedInROB() { status.set(SquashedInROB); } 753 754 /** Returns whether or not this instruction is squashed in the ROB. */ 755 bool isSquashedInROB() const { return status[SquashedInROB]; } 756 757 /** Read the PC of this instruction. */ 758 const Addr readPC() const { return PC; } 759 760 /**Read the micro PC of this instruction. */ 761 const Addr readMicroPC() const { return microPC; } 762 763 /** Set the next PC of this instruction (its actual target). */ 764 void setNextPC(Addr val) 765 { 766 nextPC = val; 767 } 768 769 /** Set the next NPC of this instruction (the target in Mips or Sparc).*/ 770 void setNextNPC(Addr val) 771 { 772#if ISA_HAS_DELAY_SLOT 773 nextNPC = val; 774#endif 775 } 776 777 void setNextMicroPC(Addr val) 778 { 779 nextMicroPC = val; 780 } 781 782 /** Sets the ASID. */ 783 void setASID(short addr_space_id) { asid = addr_space_id; } 784 785 /** Sets the thread id. */ 786 void setTid(unsigned tid) { threadNumber = tid; } 787 788 /** Sets the pointer to the thread state. */ 789 void setThreadState(ImplState *state) { thread = state; } 790 791 /** Returns the thread context. */ 792 ThreadContext *tcBase() { return thread->getTC(); } 793 794 private: 795 /** Instruction effective address. 796 * @todo: Consider if this is necessary or not. 797 */ 798 Addr instEffAddr; 799 800 /** Whether or not the effective address calculation is completed. 801 * @todo: Consider if this is necessary or not. 802 */ 803 bool eaCalcDone; 804 805 /** Is this instruction's memory access uncacheable. */ 806 bool isUncacheable; 807 808 /** Has this instruction generated a memory request. */ 809 bool reqMade; 810 811 public: 812 /** Sets the effective address. */ 813 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 814 815 /** Returns the effective address. */ 816 const Addr &getEA() const { return instEffAddr; } 817 818 /** Returns whether or not the eff. addr. calculation has been completed. */ 819 bool doneEACalc() { return eaCalcDone; } 820 821 /** Returns whether or not the eff. addr. source registers are ready. */ 822 bool eaSrcsReady(); 823 824 /** Whether or not the memory operation is done. */ 825 bool memOpDone; 826 827 /** Is this instruction's memory access uncacheable. */ 828 bool uncacheable() { return isUncacheable; } 829 830 /** Has this instruction generated a memory request. */ 831 bool hasRequest() { return reqMade; } 832 833 public: 834 /** Load queue index. */ 835 int16_t lqIdx; 836 837 /** Store queue index. */ 838 int16_t sqIdx; 839 840 /** Iterator pointing to this BaseDynInst in the list of all insts. */ 841 ListIt instListIt; 842 843 /** Returns iterator to this instruction in the list of all insts. */ 844 ListIt &getInstListIt() { return instListIt; } 845 846 /** Sets iterator for this instruction in the list of all insts. */ 847 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 848 849 public: 850 /** Returns the number of consecutive store conditional failures. */ 851 unsigned readStCondFailures() 852 { return thread->storeCondFailures; } 853 854 /** Sets the number of consecutive store conditional failures. */ 855 void setStCondFailures(unsigned sc_failures) 856 { thread->storeCondFailures = sc_failures; } 857}; 858 859template<class Impl> 860Fault 861BaseDynInst<Impl>::translateDataReadAddr(Addr vaddr, Addr &paddr, 862 int size, unsigned flags) 863{ 864 if (traceData) { 865 traceData->setAddr(vaddr); 866 } 867 868 reqMade = true; 869 Request *req = new Request(); 870 req->setVirt(asid, vaddr, size, flags, PC); 871 req->setThreadContext(thread->cpuId(), threadNumber); 872 873 fault = cpu->translateDataReadReq(req, thread); 874 875 if (fault == NoFault) 876 paddr = req->getPaddr(); 877 878 delete req; 879 return fault; 880} 881 882template<class Impl> 883template<class T> 884inline Fault 885BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) 886{ 887 reqMade = true; 888 Request *req = new Request(); 889 req->setVirt(asid, addr, sizeof(T), flags, this->PC); 890 req->setThreadContext(thread->cpuId(), threadNumber); 891 892 fault = cpu->translateDataReadReq(req, thread); 893 894 if (req->isUncacheable()) 895 isUncacheable = true; 896 897 if (fault == NoFault) { 898 effAddr = req->getVaddr(); 899 effAddrValid = true; 900 physEffAddr = req->getPaddr(); 901 memReqFlags = req->getFlags(); 902 903#if 0 904 if (cpu->system->memctrl->badaddr(physEffAddr)) { 905 fault = TheISA::genMachineCheckFault(); 906 data = (T)-1; 907 this->setExecuted(); 908 } else { 909 fault = cpu->read(req, data, lqIdx); 910 } 911#else 912 fault = cpu->read(req, data, lqIdx); 913#endif 914 } else { 915 // Return a fixed value to keep simulation deterministic even 916 // along misspeculated paths. 917 data = (T)-1; 918 919 // Commit will have to clean up whatever happened. Set this 920 // instruction as executed. 921 this->setExecuted(); 922 delete req; 923 } 924 925 if (traceData) { 926 traceData->setAddr(addr); 927 traceData->setData(data); 928 } 929 930 return fault; 931} 932 933template<class Impl> 934Fault 935BaseDynInst<Impl>::translateDataWriteAddr(Addr vaddr, Addr &paddr, 936 int size, unsigned flags) 937{ 938 if (traceData) { 939 traceData->setAddr(vaddr); 940 } 941 942 reqMade = true; 943 Request *req = new Request(); 944 req->setVirt(asid, vaddr, size, flags, PC); 945 req->setThreadContext(thread->cpuId(), threadNumber); 946 947 fault = cpu->translateDataWriteReq(req, thread); 948 949 if (fault == NoFault) 950 paddr = req->getPaddr(); 951 952 delete req; 953 return fault; 954} 955 956template<class Impl> 957template<class T> 958inline Fault 959BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) 960{ 961 if (traceData) { 962 traceData->setAddr(addr); 963 traceData->setData(data); 964 } 965 966 reqMade = true; 967 Request *req = new Request(); 968 req->setVirt(asid, addr, sizeof(T), flags, this->PC); 969 req->setThreadContext(thread->cpuId(), threadNumber); 970 971 fault = cpu->translateDataWriteReq(req, thread); 972 973 if (req->isUncacheable()) 974 isUncacheable = true; 975 976 if (fault == NoFault) { 977 effAddr = req->getVaddr(); 978 effAddrValid = true; 979 physEffAddr = req->getPaddr(); 980 memReqFlags = req->getFlags(); 981 982 if (req->isCondSwap()) { 983 assert(res); 984 req->setExtraData(*res); 985 } 986#if 0 987 if (cpu->system->memctrl->badaddr(physEffAddr)) { 988 fault = TheISA::genMachineCheckFault(); 989 } else { 990 fault = cpu->write(req, data, sqIdx); 991 } 992#else 993 fault = cpu->write(req, data, sqIdx); 994#endif 995 } else { 996 delete req; 997 } 998 999 return fault; 1000} 1001 1002#endif // __CPU_BASE_DYN_INST_HH__ 1003