base_dyn_inst.hh revision 5177
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_BASE_DYN_INST_HH__ 32#define __CPU_BASE_DYN_INST_HH__ 33 34#include <bitset> 35#include <list> 36#include <string> 37 38#include "arch/faults.hh" 39#include "base/fast_alloc.hh" 40#include "base/trace.hh" 41#include "config/full_system.hh" 42#include "cpu/o3/comm.hh" 43#include "cpu/exetrace.hh" 44#include "cpu/inst_seq.hh" 45#include "cpu/op_class.hh" 46#include "cpu/static_inst.hh" 47#include "mem/packet.hh" 48#include "sim/system.hh" 49 50/** 51 * @file 52 * Defines a dynamic instruction context. 53 */ 54 55// Forward declaration. 56class StaticInstPtr; 57 58template <class Impl> 59class BaseDynInst : public FastAlloc, public RefCounted 60{ 61 public: 62 // Typedef for the CPU. 63 typedef typename Impl::CPUType ImplCPU; 64 typedef typename ImplCPU::ImplState ImplState; 65 66 // Logical register index type. 67 typedef TheISA::RegIndex RegIndex; 68 // Integer register type. 69 typedef TheISA::IntReg IntReg; 70 // Floating point register type. 71 typedef TheISA::FloatReg FloatReg; 72 73 // The DynInstPtr type. 74 typedef typename Impl::DynInstPtr DynInstPtr; 75 76 // The list of instructions iterator type. 77 typedef typename std::list<DynInstPtr>::iterator ListIt; 78 79 enum { 80 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 81 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs 82 }; 83 84 /** The StaticInst used by this BaseDynInst. */ 85 StaticInstPtr staticInst; 86 87 //////////////////////////////////////////// 88 // 89 // INSTRUCTION EXECUTION 90 // 91 //////////////////////////////////////////// 92 /** InstRecord that tracks this instructions. */ 93 Trace::InstRecord *traceData; 94 95 /** 96 * Does a read to a given address. 97 * @param addr The address to read. 98 * @param data The read's data is written into this parameter. 99 * @param flags The request's flags. 100 * @return Returns any fault due to the read. 101 */ 102 template <class T> 103 Fault read(Addr addr, T &data, unsigned flags); 104 105 Fault translateDataReadAddr(Addr vaddr, Addr &paddr, 106 int size, unsigned flags); 107 108 /** 109 * Does a write to a given address. 110 * @param data The data to be written. 111 * @param addr The address to write to. 112 * @param flags The request's flags. 113 * @param res The result of the write (for load locked/store conditionals). 114 * @return Returns any fault due to the write. 115 */ 116 template <class T> 117 Fault write(T data, Addr addr, unsigned flags, 118 uint64_t *res); 119 120 Fault translateDataWriteAddr(Addr vaddr, Addr &paddr, 121 int size, unsigned flags); 122 123 void prefetch(Addr addr, unsigned flags); 124 void writeHint(Addr addr, int size, unsigned flags); 125 Fault copySrcTranslate(Addr src); 126 Fault copy(Addr dest); 127 128 /** @todo: Consider making this private. */ 129 public: 130 /** The sequence number of the instruction. */ 131 InstSeqNum seqNum; 132 133 enum Status { 134 IqEntry, /// Instruction is in the IQ 135 RobEntry, /// Instruction is in the ROB 136 LsqEntry, /// Instruction is in the LSQ 137 Completed, /// Instruction has completed 138 ResultReady, /// Instruction has its result 139 CanIssue, /// Instruction can issue and execute 140 Issued, /// Instruction has issued 141 Executed, /// Instruction has executed 142 CanCommit, /// Instruction can commit 143 AtCommit, /// Instruction has reached commit 144 Committed, /// Instruction has committed 145 Squashed, /// Instruction is squashed 146 SquashedInIQ, /// Instruction is squashed in the IQ 147 SquashedInLSQ, /// Instruction is squashed in the LSQ 148 SquashedInROB, /// Instruction is squashed in the ROB 149 RecoverInst, /// Is a recover instruction 150 BlockingInst, /// Is a blocking instruction 151 ThreadsyncWait, /// Is a thread synchronization instruction 152 SerializeBefore, /// Needs to serialize on 153 /// instructions ahead of it 154 SerializeAfter, /// Needs to serialize instructions behind it 155 SerializeHandled, /// Serialization has been handled 156 NumStatus 157 }; 158 159 /** The status of this BaseDynInst. Several bits can be set. */ 160 std::bitset<NumStatus> status; 161 162 /** The thread this instruction is from. */ 163 short threadNumber; 164 165 /** data address space ID, for loads & stores. */ 166 short asid; 167 168 /** How many source registers are ready. */ 169 unsigned readyRegs; 170 171 /** Pointer to the Impl's CPU object. */ 172 ImplCPU *cpu; 173 174 /** Pointer to the thread state. */ 175 ImplState *thread; 176 177 /** The kind of fault this instruction has generated. */ 178 Fault fault; 179 180 /** Pointer to the data for the memory access. */ 181 uint8_t *memData; 182 183 /** The effective virtual address (lds & stores only). */ 184 Addr effAddr; 185 186 /** Is the effective virtual address valid. */ 187 bool effAddrValid; 188 189 /** The effective physical address. */ 190 Addr physEffAddr; 191 192 /** Effective virtual address for a copy source. */ 193 Addr copySrcEffAddr; 194 195 /** Effective physical address for a copy source. */ 196 Addr copySrcPhysEffAddr; 197 198 /** The memory request flags (from translation). */ 199 unsigned memReqFlags; 200 201 union Result { 202 uint64_t integer; 203// float fp; 204 double dbl; 205 }; 206 207 /** The result of the instruction; assumes for now that there's only one 208 * destination register. 209 */ 210 Result instResult; 211 212 /** Records changes to result? */ 213 bool recordResult; 214 215 /** PC of this instruction. */ 216 Addr PC; 217 218 /** Micro PC of this instruction. */ 219 Addr microPC; 220 221 protected: 222 /** Next non-speculative PC. It is not filled in at fetch, but rather 223 * once the target of the branch is truly known (either decode or 224 * execute). 225 */ 226 Addr nextPC; 227 228 /** Next non-speculative NPC. Target PC for Mips or Sparc. */ 229 Addr nextNPC; 230 231 /** Next non-speculative micro PC. */ 232 Addr nextMicroPC; 233 234 /** Predicted next PC. */ 235 Addr predPC; 236 237 /** Predicted next NPC. */ 238 Addr predNPC; 239 240 /** Predicted next microPC */ 241 Addr predMicroPC; 242 243 /** If this is a branch that was predicted taken */ 244 bool predTaken; 245 246 public: 247 248 /** Count of total number of dynamic instructions. */ 249 static int instcount; 250 251#ifdef DEBUG 252 void dumpSNList(); 253#endif 254 255 /** Whether or not the source register is ready. 256 * @todo: Not sure this should be here vs the derived class. 257 */ 258 bool _readySrcRegIdx[MaxInstSrcRegs]; 259 260 protected: 261 /** Flattened register index of the destination registers of this 262 * instruction. 263 */ 264 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs]; 265 266 /** Flattened register index of the source registers of this 267 * instruction. 268 */ 269 TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs]; 270 271 /** Physical register index of the destination registers of this 272 * instruction. 273 */ 274 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs]; 275 276 /** Physical register index of the source registers of this 277 * instruction. 278 */ 279 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs]; 280 281 /** Physical register index of the previous producers of the 282 * architected destinations. 283 */ 284 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs]; 285 286 public: 287 288 /** Returns the physical register index of the i'th destination 289 * register. 290 */ 291 PhysRegIndex renamedDestRegIdx(int idx) const 292 { 293 return _destRegIdx[idx]; 294 } 295 296 /** Returns the physical register index of the i'th source register. */ 297 PhysRegIndex renamedSrcRegIdx(int idx) const 298 { 299 return _srcRegIdx[idx]; 300 } 301 302 /** Returns the flattened register index of the i'th destination 303 * register. 304 */ 305 TheISA::RegIndex flattenedDestRegIdx(int idx) const 306 { 307 return _flatDestRegIdx[idx]; 308 } 309 310 /** Returns the flattened register index of the i'th source register */ 311 TheISA::RegIndex flattenedSrcRegIdx(int idx) const 312 { 313 return _flatSrcRegIdx[idx]; 314 } 315 316 /** Returns the physical register index of the previous physical register 317 * that remapped to the same logical register index. 318 */ 319 PhysRegIndex prevDestRegIdx(int idx) const 320 { 321 return _prevDestRegIdx[idx]; 322 } 323 324 /** Renames a destination register to a physical register. Also records 325 * the previous physical register that the logical register mapped to. 326 */ 327 void renameDestReg(int idx, 328 PhysRegIndex renamed_dest, 329 PhysRegIndex previous_rename) 330 { 331 _destRegIdx[idx] = renamed_dest; 332 _prevDestRegIdx[idx] = previous_rename; 333 } 334 335 /** Renames a source logical register to the physical register which 336 * has/will produce that logical register's result. 337 * @todo: add in whether or not the source register is ready. 338 */ 339 void renameSrcReg(int idx, PhysRegIndex renamed_src) 340 { 341 _srcRegIdx[idx] = renamed_src; 342 } 343 344 /** Flattens a source architectural register index into a logical index. 345 */ 346 void flattenSrcReg(int idx, TheISA::RegIndex flattened_src) 347 { 348 _flatSrcRegIdx[idx] = flattened_src; 349 } 350 351 /** Flattens a destination architectural register index into a logical 352 * index. 353 */ 354 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 355 { 356 _flatDestRegIdx[idx] = flattened_dest; 357 } 358 /** BaseDynInst constructor given a binary instruction. 359 * @param staticInst A StaticInstPtr to the underlying instruction. 360 * @param PC The PC of the instruction. 361 * @param pred_PC The predicted next PC. 362 * @param pred_NPC The predicted next NPC. 363 * @param seq_num The sequence number of the instruction. 364 * @param cpu Pointer to the instruction's CPU. 365 */ 366 BaseDynInst(StaticInstPtr staticInst, Addr PC, Addr NPC, Addr microPC, 367 Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC, 368 InstSeqNum seq_num, ImplCPU *cpu); 369 370 /** BaseDynInst constructor given a binary instruction. 371 * @param inst The binary instruction. 372 * @param PC The PC of the instruction. 373 * @param pred_PC The predicted next PC. 374 * @param pred_NPC The predicted next NPC. 375 * @param seq_num The sequence number of the instruction. 376 * @param cpu Pointer to the instruction's CPU. 377 */ 378 BaseDynInst(TheISA::ExtMachInst inst, Addr PC, Addr NPC, Addr microPC, 379 Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC, 380 InstSeqNum seq_num, ImplCPU *cpu); 381 382 /** BaseDynInst constructor given a StaticInst pointer. 383 * @param _staticInst The StaticInst for this BaseDynInst. 384 */ 385 BaseDynInst(StaticInstPtr &_staticInst); 386 387 /** BaseDynInst destructor. */ 388 ~BaseDynInst(); 389 390 private: 391 /** Function to initialize variables in the constructors. */ 392 void initVars(); 393 394 public: 395 /** Dumps out contents of this BaseDynInst. */ 396 void dump(); 397 398 /** Dumps out contents of this BaseDynInst into given string. */ 399 void dump(std::string &outstring); 400 401 /** Read this CPU's ID. */ 402 int readCpuId() { return cpu->readCpuId(); } 403 404 /** Returns the fault type. */ 405 Fault getFault() { return fault; } 406 407 /** Checks whether or not this instruction has had its branch target 408 * calculated yet. For now it is not utilized and is hacked to be 409 * always false. 410 * @todo: Actually use this instruction. 411 */ 412 bool doneTargCalc() { return false; } 413 414 /** Returns the next PC. This could be the speculative next PC if it is 415 * called prior to the actual branch target being calculated. 416 */ 417 Addr readNextPC() { return nextPC; } 418 419 /** Returns the next NPC. This could be the speculative next NPC if it is 420 * called prior to the actual branch target being calculated. 421 */ 422 Addr readNextNPC() 423 { 424#if ISA_HAS_DELAY_SLOT 425 return nextNPC; 426#else 427 return nextPC + sizeof(TheISA::MachInst); 428#endif 429 } 430 431 Addr readNextMicroPC() 432 { 433 return nextMicroPC; 434 } 435 436 /** Set the predicted target of this current instruction. */ 437 void setPredTarg(Addr predicted_PC, Addr predicted_NPC, 438 Addr predicted_MicroPC) 439 { 440 predPC = predicted_PC; 441 predNPC = predicted_NPC; 442 predMicroPC = predicted_MicroPC; 443 } 444 445 /** Returns the predicted PC immediately after the branch. */ 446 Addr readPredPC() { return predPC; } 447 448 /** Returns the predicted PC two instructions after the branch */ 449 Addr readPredNPC() { return predNPC; } 450 451 /** Returns the predicted micro PC after the branch */ 452 Addr readPredMicroPC() { return predMicroPC; } 453 454 /** Returns whether the instruction was predicted taken or not. */ 455 bool readPredTaken() 456 { 457 return predTaken; 458 } 459 460 void setPredTaken(bool predicted_taken) 461 { 462 predTaken = predicted_taken; 463 } 464 465 /** Returns whether the instruction mispredicted. */ 466 bool mispredicted() 467 { 468 return readPredPC() != readNextPC() || 469 readPredNPC() != readNextNPC() || 470 readPredMicroPC() != readNextMicroPC(); 471 } 472 473 // 474 // Instruction types. Forward checks to StaticInst object. 475 // 476 bool isNop() const { return staticInst->isNop(); } 477 bool isMemRef() const { return staticInst->isMemRef(); } 478 bool isLoad() const { return staticInst->isLoad(); } 479 bool isStore() const { return staticInst->isStore(); } 480 bool isStoreConditional() const 481 { return staticInst->isStoreConditional(); } 482 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 483 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 484 bool isCopy() const { return staticInst->isCopy(); } 485 bool isInteger() const { return staticInst->isInteger(); } 486 bool isFloating() const { return staticInst->isFloating(); } 487 bool isControl() const { return staticInst->isControl(); } 488 bool isCall() const { return staticInst->isCall(); } 489 bool isReturn() const { return staticInst->isReturn(); } 490 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 491 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 492 bool isCondCtrl() const { return staticInst->isCondCtrl(); } 493 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 494 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 495 bool isThreadSync() const { return staticInst->isThreadSync(); } 496 bool isSerializing() const { return staticInst->isSerializing(); } 497 bool isSerializeBefore() const 498 { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 499 bool isSerializeAfter() const 500 { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 501 bool isMemBarrier() const { return staticInst->isMemBarrier(); } 502 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 503 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 504 bool isQuiesce() const { return staticInst->isQuiesce(); } 505 bool isIprAccess() const { return staticInst->isIprAccess(); } 506 bool isUnverifiable() const { return staticInst->isUnverifiable(); } 507 bool isSyscall() const { return staticInst->isSyscall(); } 508 bool isMacroop() const { return staticInst->isMacroop(); } 509 bool isMicroop() const { return staticInst->isMicroop(); } 510 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 511 bool isLastMicroop() const { return staticInst->isLastMicroop(); } 512 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 513 bool isMicroBranch() const { return staticInst->isMicroBranch(); } 514 515 /** Temporarily sets this instruction as a serialize before instruction. */ 516 void setSerializeBefore() { status.set(SerializeBefore); } 517 518 /** Clears the serializeBefore part of this instruction. */ 519 void clearSerializeBefore() { status.reset(SerializeBefore); } 520 521 /** Checks if this serializeBefore is only temporarily set. */ 522 bool isTempSerializeBefore() { return status[SerializeBefore]; } 523 524 /** Temporarily sets this instruction as a serialize after instruction. */ 525 void setSerializeAfter() { status.set(SerializeAfter); } 526 527 /** Clears the serializeAfter part of this instruction.*/ 528 void clearSerializeAfter() { status.reset(SerializeAfter); } 529 530 /** Checks if this serializeAfter is only temporarily set. */ 531 bool isTempSerializeAfter() { return status[SerializeAfter]; } 532 533 /** Sets the serialization part of this instruction as handled. */ 534 void setSerializeHandled() { status.set(SerializeHandled); } 535 536 /** Checks if the serialization part of this instruction has been 537 * handled. This does not apply to the temporary serializing 538 * state; it only applies to this instruction's own permanent 539 * serializing state. 540 */ 541 bool isSerializeHandled() { return status[SerializeHandled]; } 542 543 /** Returns the opclass of this instruction. */ 544 OpClass opClass() const { return staticInst->opClass(); } 545 546 /** Returns the branch target address. */ 547 Addr branchTarget() const { return staticInst->branchTarget(PC); } 548 549 /** Returns the number of source registers. */ 550 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 551 552 /** Returns the number of destination registers. */ 553 int8_t numDestRegs() const { return staticInst->numDestRegs(); } 554 555 // the following are used to track physical register usage 556 // for machines with separate int & FP reg files 557 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 558 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 559 560 /** Returns the logical register index of the i'th destination register. */ 561 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 562 563 /** Returns the logical register index of the i'th source register. */ 564 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 565 566 /** Returns the result of an integer instruction. */ 567 uint64_t readIntResult() { return instResult.integer; } 568 569 /** Returns the result of a floating point instruction. */ 570 float readFloatResult() { return (float)instResult.dbl; } 571 572 /** Returns the result of a floating point (double) instruction. */ 573 double readDoubleResult() { return instResult.dbl; } 574 575 /** Records an integer register being set to a value. */ 576 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 577 { 578 if (recordResult) 579 instResult.integer = val; 580 } 581 582 /** Records an fp register being set to a value. */ 583 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 584 int width) 585 { 586 if (recordResult) { 587 if (width == 32) 588 instResult.dbl = (double)val; 589 else if (width == 64) 590 instResult.dbl = val; 591 else 592 panic("Unsupported width!"); 593 } 594 } 595 596 /** Records an fp register being set to a value. */ 597 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 598 { 599 if (recordResult) 600 instResult.dbl = (double)val; 601 } 602 603 /** Records an fp register being set to an integer value. */ 604 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val, 605 int width) 606 { 607 if (recordResult) 608 instResult.integer = val; 609 } 610 611 /** Records an fp register being set to an integer value. */ 612 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val) 613 { 614 if (recordResult) 615 instResult.integer = val; 616 } 617 618 /** Records that one of the source registers is ready. */ 619 void markSrcRegReady(); 620 621 /** Marks a specific register as ready. */ 622 void markSrcRegReady(RegIndex src_idx); 623 624 /** Returns if a source register is ready. */ 625 bool isReadySrcRegIdx(int idx) const 626 { 627 return this->_readySrcRegIdx[idx]; 628 } 629 630 /** Sets this instruction as completed. */ 631 void setCompleted() { status.set(Completed); } 632 633 /** Returns whether or not this instruction is completed. */ 634 bool isCompleted() const { return status[Completed]; } 635 636 /** Marks the result as ready. */ 637 void setResultReady() { status.set(ResultReady); } 638 639 /** Returns whether or not the result is ready. */ 640 bool isResultReady() const { return status[ResultReady]; } 641 642 /** Sets this instruction as ready to issue. */ 643 void setCanIssue() { status.set(CanIssue); } 644 645 /** Returns whether or not this instruction is ready to issue. */ 646 bool readyToIssue() const { return status[CanIssue]; } 647 648 /** Clears this instruction being able to issue. */ 649 void clearCanIssue() { status.reset(CanIssue); } 650 651 /** Sets this instruction as issued from the IQ. */ 652 void setIssued() { status.set(Issued); } 653 654 /** Returns whether or not this instruction has issued. */ 655 bool isIssued() const { return status[Issued]; } 656 657 /** Clears this instruction as being issued. */ 658 void clearIssued() { status.reset(Issued); } 659 660 /** Sets this instruction as executed. */ 661 void setExecuted() { status.set(Executed); } 662 663 /** Returns whether or not this instruction has executed. */ 664 bool isExecuted() const { return status[Executed]; } 665 666 /** Sets this instruction as ready to commit. */ 667 void setCanCommit() { status.set(CanCommit); } 668 669 /** Clears this instruction as being ready to commit. */ 670 void clearCanCommit() { status.reset(CanCommit); } 671 672 /** Returns whether or not this instruction is ready to commit. */ 673 bool readyToCommit() const { return status[CanCommit]; } 674 675 void setAtCommit() { status.set(AtCommit); } 676 677 bool isAtCommit() { return status[AtCommit]; } 678 679 /** Sets this instruction as committed. */ 680 void setCommitted() { status.set(Committed); } 681 682 /** Returns whether or not this instruction is committed. */ 683 bool isCommitted() const { return status[Committed]; } 684 685 /** Sets this instruction as squashed. */ 686 void setSquashed() { status.set(Squashed); } 687 688 /** Returns whether or not this instruction is squashed. */ 689 bool isSquashed() const { return status[Squashed]; } 690 691 //Instruction Queue Entry 692 //----------------------- 693 /** Sets this instruction as a entry the IQ. */ 694 void setInIQ() { status.set(IqEntry); } 695 696 /** Sets this instruction as a entry the IQ. */ 697 void clearInIQ() { status.reset(IqEntry); } 698 699 /** Returns whether or not this instruction has issued. */ 700 bool isInIQ() const { return status[IqEntry]; } 701 702 /** Sets this instruction as squashed in the IQ. */ 703 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 704 705 /** Returns whether or not this instruction is squashed in the IQ. */ 706 bool isSquashedInIQ() const { return status[SquashedInIQ]; } 707 708 709 //Load / Store Queue Functions 710 //----------------------- 711 /** Sets this instruction as a entry the LSQ. */ 712 void setInLSQ() { status.set(LsqEntry); } 713 714 /** Sets this instruction as a entry the LSQ. */ 715 void removeInLSQ() { status.reset(LsqEntry); } 716 717 /** Returns whether or not this instruction is in the LSQ. */ 718 bool isInLSQ() const { return status[LsqEntry]; } 719 720 /** Sets this instruction as squashed in the LSQ. */ 721 void setSquashedInLSQ() { status.set(SquashedInLSQ);} 722 723 /** Returns whether or not this instruction is squashed in the LSQ. */ 724 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 725 726 727 //Reorder Buffer Functions 728 //----------------------- 729 /** Sets this instruction as a entry the ROB. */ 730 void setInROB() { status.set(RobEntry); } 731 732 /** Sets this instruction as a entry the ROB. */ 733 void clearInROB() { status.reset(RobEntry); } 734 735 /** Returns whether or not this instruction is in the ROB. */ 736 bool isInROB() const { return status[RobEntry]; } 737 738 /** Sets this instruction as squashed in the ROB. */ 739 void setSquashedInROB() { status.set(SquashedInROB); } 740 741 /** Returns whether or not this instruction is squashed in the ROB. */ 742 bool isSquashedInROB() const { return status[SquashedInROB]; } 743 744 /** Read the PC of this instruction. */ 745 const Addr readPC() const { return PC; } 746 747 /**Read the micro PC of this instruction. */ 748 const Addr readMicroPC() const { return microPC; } 749 750 /** Set the next PC of this instruction (its actual target). */ 751 void setNextPC(Addr val) 752 { 753 nextPC = val; 754 } 755 756 /** Set the next NPC of this instruction (the target in Mips or Sparc).*/ 757 void setNextNPC(Addr val) 758 { 759#if ISA_HAS_DELAY_SLOT 760 nextNPC = val; 761#endif 762 } 763 764 void setNextMicroPC(Addr val) 765 { 766 nextMicroPC = val; 767 } 768 769 /** Sets the ASID. */ 770 void setASID(short addr_space_id) { asid = addr_space_id; } 771 772 /** Sets the thread id. */ 773 void setTid(unsigned tid) { threadNumber = tid; } 774 775 /** Sets the pointer to the thread state. */ 776 void setThreadState(ImplState *state) { thread = state; } 777 778 /** Returns the thread context. */ 779 ThreadContext *tcBase() { return thread->getTC(); } 780 781 private: 782 /** Instruction effective address. 783 * @todo: Consider if this is necessary or not. 784 */ 785 Addr instEffAddr; 786 787 /** Whether or not the effective address calculation is completed. 788 * @todo: Consider if this is necessary or not. 789 */ 790 bool eaCalcDone; 791 792 /** Is this instruction's memory access uncacheable. */ 793 bool isUncacheable; 794 795 /** Has this instruction generated a memory request. */ 796 bool reqMade; 797 798 public: 799 /** Sets the effective address. */ 800 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 801 802 /** Returns the effective address. */ 803 const Addr &getEA() const { return instEffAddr; } 804 805 /** Returns whether or not the eff. addr. calculation has been completed. */ 806 bool doneEACalc() { return eaCalcDone; } 807 808 /** Returns whether or not the eff. addr. source registers are ready. */ 809 bool eaSrcsReady(); 810 811 /** Whether or not the memory operation is done. */ 812 bool memOpDone; 813 814 /** Is this instruction's memory access uncacheable. */ 815 bool uncacheable() { return isUncacheable; } 816 817 /** Has this instruction generated a memory request. */ 818 bool hasRequest() { return reqMade; } 819 820 public: 821 /** Load queue index. */ 822 int16_t lqIdx; 823 824 /** Store queue index. */ 825 int16_t sqIdx; 826 827 /** Iterator pointing to this BaseDynInst in the list of all insts. */ 828 ListIt instListIt; 829 830 /** Returns iterator to this instruction in the list of all insts. */ 831 ListIt &getInstListIt() { return instListIt; } 832 833 /** Sets iterator for this instruction in the list of all insts. */ 834 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 835 836 public: 837 /** Returns the number of consecutive store conditional failures. */ 838 unsigned readStCondFailures() 839 { return thread->storeCondFailures; } 840 841 /** Sets the number of consecutive store conditional failures. */ 842 void setStCondFailures(unsigned sc_failures) 843 { thread->storeCondFailures = sc_failures; } 844}; 845 846template<class Impl> 847Fault 848BaseDynInst<Impl>::translateDataReadAddr(Addr vaddr, Addr &paddr, 849 int size, unsigned flags) 850{ 851 if (traceData) { 852 traceData->setAddr(vaddr); 853 } 854 855 reqMade = true; 856 Request *req = new Request(); 857 req->setVirt(asid, vaddr, size, flags, PC); 858 req->setThreadContext(thread->readCpuId(), threadNumber); 859 860 fault = cpu->translateDataReadReq(req, thread); 861 862 if (fault == NoFault) 863 paddr = req->getPaddr(); 864 865 delete req; 866 return fault; 867} 868 869template<class Impl> 870template<class T> 871inline Fault 872BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) 873{ 874 reqMade = true; 875 Request *req = new Request(); 876 req->setVirt(asid, addr, sizeof(T), flags, this->PC); 877 req->setThreadContext(thread->readCpuId(), threadNumber); 878 879 fault = cpu->translateDataReadReq(req, thread); 880 881 if (req->isUncacheable()) 882 isUncacheable = true; 883 884 if (fault == NoFault) { 885 effAddr = req->getVaddr(); 886 effAddrValid = true; 887 physEffAddr = req->getPaddr(); 888 memReqFlags = req->getFlags(); 889 890#if 0 891 if (cpu->system->memctrl->badaddr(physEffAddr)) { 892 fault = TheISA::genMachineCheckFault(); 893 data = (T)-1; 894 this->setExecuted(); 895 } else { 896 fault = cpu->read(req, data, lqIdx); 897 } 898#else 899 fault = cpu->read(req, data, lqIdx); 900#endif 901 } else { 902 // Return a fixed value to keep simulation deterministic even 903 // along misspeculated paths. 904 data = (T)-1; 905 906 // Commit will have to clean up whatever happened. Set this 907 // instruction as executed. 908 this->setExecuted(); 909 delete req; 910 } 911 912 if (traceData) { 913 traceData->setAddr(addr); 914 traceData->setData(data); 915 } 916 917 return fault; 918} 919 920template<class Impl> 921Fault 922BaseDynInst<Impl>::translateDataWriteAddr(Addr vaddr, Addr &paddr, 923 int size, unsigned flags) 924{ 925 if (traceData) { 926 traceData->setAddr(vaddr); 927 } 928 929 reqMade = true; 930 Request *req = new Request(); 931 req->setVirt(asid, vaddr, size, flags, PC); 932 req->setThreadContext(thread->readCpuId(), threadNumber); 933 934 fault = cpu->translateDataWriteReq(req, thread); 935 936 if (fault == NoFault) 937 paddr = req->getPaddr(); 938 939 delete req; 940 return fault; 941} 942 943template<class Impl> 944template<class T> 945inline Fault 946BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) 947{ 948 if (traceData) { 949 traceData->setAddr(addr); 950 traceData->setData(data); 951 } 952 953 reqMade = true; 954 Request *req = new Request(); 955 req->setVirt(asid, addr, sizeof(T), flags, this->PC); 956 req->setThreadContext(thread->readCpuId(), threadNumber); 957 958 fault = cpu->translateDataWriteReq(req, thread); 959 960 if (req->isUncacheable()) 961 isUncacheable = true; 962 963 if (fault == NoFault) { 964 effAddr = req->getVaddr(); 965 effAddrValid = true; 966 physEffAddr = req->getPaddr(); 967 memReqFlags = req->getFlags(); 968 969 if (req->isCondSwap()) { 970 assert(res); 971 req->setExtraData(*res); 972 } 973#if 0 974 if (cpu->system->memctrl->badaddr(physEffAddr)) { 975 fault = TheISA::genMachineCheckFault(); 976 } else { 977 fault = cpu->write(req, data, sqIdx); 978 } 979#else 980 fault = cpu->write(req, data, sqIdx); 981#endif 982 } else { 983 delete req; 984 } 985 986 return fault; 987} 988 989#endif // __CPU_BASE_DYN_INST_HH__ 990