base_dyn_inst.hh revision 2654:9559cfa91b9d
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __CPU_BASE_DYN_INST_HH__ 30#define __CPU_BASE_DYN_INST_HH__ 31 32#include <list> 33#include <string> 34 35#include "base/fast_alloc.hh" 36#include "base/trace.hh" 37#include "config/full_system.hh" 38#include "cpu/exetrace.hh" 39#include "cpu/inst_seq.hh" 40#include "cpu/static_inst.hh" 41#include "encumbered/cpu/full/op_class.hh" 42#include "mem/functional/memory_control.hh" 43#include "sim/system.hh" 44/* 45#include "encumbered/cpu/full/bpred_update.hh" 46#include "encumbered/cpu/full/spec_memory.hh" 47#include "encumbered/cpu/full/spec_state.hh" 48#include "encumbered/mem/functional/main.hh" 49*/ 50 51/** 52 * @file 53 * Defines a dynamic instruction context. 54 */ 55 56// Forward declaration. 57class StaticInstPtr; 58 59template <class Impl> 60class BaseDynInst : public FastAlloc, public RefCounted 61{ 62 public: 63 // Typedef for the CPU. 64 typedef typename Impl::FullCPU FullCPU; 65 typedef typename FullCPU::ImplState ImplState; 66 67 // Binary machine instruction type. 68 typedef TheISA::MachInst MachInst; 69 // Extended machine instruction type 70 typedef TheISA::ExtMachInst ExtMachInst; 71 // Logical register index type. 72 typedef TheISA::RegIndex RegIndex; 73 // Integer register index type. 74 typedef TheISA::IntReg IntReg; 75 76 // The DynInstPtr type. 77 typedef typename Impl::DynInstPtr DynInstPtr; 78 79 // The list of instructions iterator type. 80 typedef typename std::list<DynInstPtr>::iterator ListIt; 81 82 enum { 83 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 84 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs 85 }; 86 87 /** The StaticInst used by this BaseDynInst. */ 88 StaticInstPtr staticInst; 89 90 //////////////////////////////////////////// 91 // 92 // INSTRUCTION EXECUTION 93 // 94 //////////////////////////////////////////// 95 /** InstRecord that tracks this instructions. */ 96 Trace::InstRecord *traceData; 97 98 /** 99 * Does a read to a given address. 100 * @param addr The address to read. 101 * @param data The read's data is written into this parameter. 102 * @param flags The request's flags. 103 * @return Returns any fault due to the read. 104 */ 105 template <class T> 106 Fault read(Addr addr, T &data, unsigned flags); 107 108 /** 109 * Does a write to a given address. 110 * @param data The data to be written. 111 * @param addr The address to write to. 112 * @param flags The request's flags. 113 * @param res The result of the write (for load locked/store conditionals). 114 * @return Returns any fault due to the write. 115 */ 116 template <class T> 117 Fault write(T data, Addr addr, unsigned flags, 118 uint64_t *res); 119 120 void prefetch(Addr addr, unsigned flags); 121 void writeHint(Addr addr, int size, unsigned flags); 122 Fault copySrcTranslate(Addr src); 123 Fault copy(Addr dest); 124 125 /** @todo: Consider making this private. */ 126 public: 127 /** The sequence number of the instruction. */ 128 InstSeqNum seqNum; 129 130 /** Is the instruction in the IQ */ 131 bool iqEntry; 132 133 /** Is the instruction in the ROB */ 134 bool robEntry; 135 136 /** Is the instruction in the LSQ */ 137 bool lsqEntry; 138 139 /** Is the instruction completed. */ 140 bool completed; 141 142 /** Is the instruction's result ready. */ 143 bool resultReady; 144 145 /** Can this instruction issue. */ 146 bool canIssue; 147 148 /** Has this instruction issued. */ 149 bool issued; 150 151 /** Has this instruction executed (or made it through execute) yet. */ 152 bool executed; 153 154 /** Can this instruction commit. */ 155 bool canCommit; 156 157 /** Is this instruction committed. */ 158 bool committed; 159 160 /** Is this instruction squashed. */ 161 bool squashed; 162 163 /** Is this instruction squashed in the instruction queue. */ 164 bool squashedInIQ; 165 166 /** Is this instruction squashed in the instruction queue. */ 167 bool squashedInLSQ; 168 169 /** Is this instruction squashed in the instruction queue. */ 170 bool squashedInROB; 171 172 /** Is this a recover instruction. */ 173 bool recoverInst; 174 175 /** Is this a thread blocking instruction. */ 176 bool blockingInst; /* this inst has called thread_block() */ 177 178 /** Is this a thread syncrhonization instruction. */ 179 bool threadsyncWait; 180 181 /** The thread this instruction is from. */ 182 short threadNumber; 183 184 /** data address space ID, for loads & stores. */ 185 short asid; 186 187 /** How many source registers are ready. */ 188 unsigned readyRegs; 189 190 /** Pointer to the FullCPU object. */ 191 FullCPU *cpu; 192 193 /** Pointer to the exec context. */ 194 ImplState *thread; 195 196 /** The kind of fault this instruction has generated. */ 197 Fault fault; 198 199 /** The memory request. */ 200 MemReqPtr req; 201 202 /** The effective virtual address (lds & stores only). */ 203 Addr effAddr; 204 205 /** The effective physical address. */ 206 Addr physEffAddr; 207 208 /** Effective virtual address for a copy source. */ 209 Addr copySrcEffAddr; 210 211 /** Effective physical address for a copy source. */ 212 Addr copySrcPhysEffAddr; 213 214 /** The memory request flags (from translation). */ 215 unsigned memReqFlags; 216 217 /** The size of the data to be stored. */ 218 int storeSize; 219 220 /** The data to be stored. */ 221 IntReg storeData; 222 223 union Result { 224 uint64_t integer; 225 float fp; 226 double dbl; 227 }; 228 229 /** The result of the instruction; assumes for now that there's only one 230 * destination register. 231 */ 232 Result instResult; 233 234 /** PC of this instruction. */ 235 Addr PC; 236 237 /** Next non-speculative PC. It is not filled in at fetch, but rather 238 * once the target of the branch is truly known (either decode or 239 * execute). 240 */ 241 Addr nextPC; 242 243 /** Predicted next PC. */ 244 Addr predPC; 245 246 /** Count of total number of dynamic instructions. */ 247 static int instcount; 248 249#ifdef DEBUG 250 void dumpSNList(); 251#endif 252 253 /** Whether or not the source register is ready. 254 * @todo: Not sure this should be here vs the derived class. 255 */ 256 bool _readySrcRegIdx[MaxInstSrcRegs]; 257 258 public: 259 /** BaseDynInst constructor given a binary instruction. 260 * @param inst The binary instruction. 261 * @param PC The PC of the instruction. 262 * @param pred_PC The predicted next PC. 263 * @param seq_num The sequence number of the instruction. 264 * @param cpu Pointer to the instruction's CPU. 265 */ 266 BaseDynInst(ExtMachInst inst, Addr PC, Addr pred_PC, InstSeqNum seq_num, 267 FullCPU *cpu); 268 269 /** BaseDynInst constructor given a StaticInst pointer. 270 * @param _staticInst The StaticInst for this BaseDynInst. 271 */ 272 BaseDynInst(StaticInstPtr &_staticInst); 273 274 /** BaseDynInst destructor. */ 275 ~BaseDynInst(); 276 277 private: 278 /** Function to initialize variables in the constructors. */ 279 void initVars(); 280 281 public: 282 /** 283 * @todo: Make this function work; currently it is a dummy function. 284 * @param fault Last fault. 285 * @param cmd Last command. 286 * @param addr Virtual address of access. 287 * @param p Memory accessed. 288 * @param nbytes Access size. 289 */ 290 void 291 trace_mem(Fault fault, 292 MemCmd cmd, 293 Addr addr, 294 void *p, 295 int nbytes); 296 297 /** Dumps out contents of this BaseDynInst. */ 298 void dump(); 299 300 /** Dumps out contents of this BaseDynInst into given string. */ 301 void dump(std::string &outstring); 302 303 /** Returns the fault type. */ 304 Fault getFault() { return fault; } 305 306 /** Checks whether or not this instruction has had its branch target 307 * calculated yet. For now it is not utilized and is hacked to be 308 * always false. 309 * @todo: Actually use this instruction. 310 */ 311 bool doneTargCalc() { return false; } 312 313 /** Returns the next PC. This could be the speculative next PC if it is 314 * called prior to the actual branch target being calculated. 315 */ 316 Addr readNextPC() { return nextPC; } 317 318 /** Set the predicted target of this current instruction. */ 319 void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; } 320 321 /** Returns the predicted target of the branch. */ 322 Addr readPredTarg() { return predPC; } 323 324 /** Returns whether the instruction was predicted taken or not. */ 325 bool predTaken() { return predPC != (PC + sizeof(MachInst)); } 326 327 /** Returns whether the instruction mispredicted. */ 328 bool mispredicted() { return predPC != nextPC; } 329 330 // 331 // Instruction types. Forward checks to StaticInst object. 332 // 333 bool isNop() const { return staticInst->isNop(); } 334 bool isMemRef() const { return staticInst->isMemRef(); } 335 bool isLoad() const { return staticInst->isLoad(); } 336 bool isStore() const { return staticInst->isStore(); } 337 bool isStoreConditional() const 338 { return staticInst->isStoreConditional(); } 339 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 340 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 341 bool isCopy() const { return staticInst->isCopy(); } 342 bool isInteger() const { return staticInst->isInteger(); } 343 bool isFloating() const { return staticInst->isFloating(); } 344 bool isControl() const { return staticInst->isControl(); } 345 bool isCall() const { return staticInst->isCall(); } 346 bool isReturn() const { return staticInst->isReturn(); } 347 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 348 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 349 bool isCondCtrl() const { return staticInst->isCondCtrl(); } 350 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 351 bool isThreadSync() const { return staticInst->isThreadSync(); } 352 bool isSerializing() const { return staticInst->isSerializing(); } 353 bool isSerializeBefore() const 354 { return staticInst->isSerializeBefore() || serializeBefore; } 355 bool isSerializeAfter() const 356 { return staticInst->isSerializeAfter() || serializeAfter; } 357 bool isMemBarrier() const { return staticInst->isMemBarrier(); } 358 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 359 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 360 bool isQuiesce() const { return staticInst->isQuiesce(); } 361 bool isIprAccess() const { return staticInst->isIprAccess(); } 362 bool isUnverifiable() const { return staticInst->isUnverifiable(); } 363 364 /** Temporarily sets this instruction as a serialize before instruction. */ 365 void setSerializeBefore() { serializeBefore = true; } 366 367 /** Clears the serializeBefore part of this instruction. */ 368 void clearSerializeBefore() { serializeBefore = false; } 369 370 /** Checks if this serializeBefore is only temporarily set. */ 371 bool isTempSerializeBefore() { return serializeBefore; } 372 373 /** Tracks if instruction has been externally set as serializeBefore. */ 374 bool serializeBefore; 375 376 /** Temporarily sets this instruction as a serialize after instruction. */ 377 void setSerializeAfter() { serializeAfter = true; } 378 379 /** Clears the serializeAfter part of this instruction.*/ 380 void clearSerializeAfter() { serializeAfter = false; } 381 382 /** Checks if this serializeAfter is only temporarily set. */ 383 bool isTempSerializeAfter() { return serializeAfter; } 384 385 /** Tracks if instruction has been externally set as serializeAfter. */ 386 bool serializeAfter; 387 388 /** Checks if the serialization part of this instruction has been 389 * handled. This does not apply to the temporary serializing 390 * state; it only applies to this instruction's own permanent 391 * serializing state. 392 */ 393 bool isSerializeHandled() { return serializeHandled; } 394 395 /** Sets the serialization part of this instruction as handled. */ 396 void setSerializeHandled() { serializeHandled = true; } 397 398 /** Whether or not the serialization of this instruction has been handled. */ 399 bool serializeHandled; 400 401 /** Returns the opclass of this instruction. */ 402 OpClass opClass() const { return staticInst->opClass(); } 403 404 /** Returns the branch target address. */ 405 Addr branchTarget() const { return staticInst->branchTarget(PC); } 406 407 /** Returns the number of source registers. */ 408 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 409 410 /** Returns the number of destination registers. */ 411 int8_t numDestRegs() const { return staticInst->numDestRegs(); } 412 413 // the following are used to track physical register usage 414 // for machines with separate int & FP reg files 415 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 416 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 417 418 /** Returns the logical register index of the i'th destination register. */ 419 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 420 421 /** Returns the logical register index of the i'th source register. */ 422 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 423 424 /** Returns the result of an integer instruction. */ 425 uint64_t readIntResult() { return instResult.integer; } 426 427 /** Returns the result of a floating point instruction. */ 428 float readFloatResult() { return instResult.fp; } 429 430 /** Returns the result of a floating point (double) instruction. */ 431 double readDoubleResult() { return instResult.dbl; } 432 433 void setIntReg(const StaticInst *si, int idx, uint64_t val) 434 { 435 instResult.integer = val; 436 } 437 438 void setFloatRegSingle(const StaticInst *si, int idx, float val) 439 { 440 instResult.fp = val; 441 } 442 443 void setFloatRegDouble(const StaticInst *si, int idx, double val) 444 { 445 instResult.dbl = val; 446 } 447 448 void setFloatRegInt(const StaticInst *si, int idx, uint64_t val) 449 { 450 instResult.integer = val; 451 } 452 453 /** Records that one of the source registers is ready. */ 454 void markSrcRegReady(); 455 456 /** Marks a specific register as ready. */ 457 void markSrcRegReady(RegIndex src_idx); 458 459 /** Returns if a source register is ready. */ 460 bool isReadySrcRegIdx(int idx) const 461 { 462 return this->_readySrcRegIdx[idx]; 463 } 464 465 /** Sets this instruction as completed. */ 466 void setCompleted() { completed = true; } 467 468 /** Returns whether or not this instruction is completed. */ 469 bool isCompleted() const { return completed; } 470 471 void setResultReady() { resultReady = true; } 472 473 bool isResultReady() const { return resultReady; } 474 475 /** Sets this instruction as ready to issue. */ 476 void setCanIssue() { canIssue = true; } 477 478 /** Returns whether or not this instruction is ready to issue. */ 479 bool readyToIssue() const { return canIssue; } 480 481 /** Sets this instruction as issued from the IQ. */ 482 void setIssued() { issued = true; } 483 484 /** Returns whether or not this instruction has issued. */ 485 bool isIssued() const { return issued; } 486 487 /** Sets this instruction as executed. */ 488 void setExecuted() { executed = true; } 489 490 /** Returns whether or not this instruction has executed. */ 491 bool isExecuted() const { return executed; } 492 493 /** Sets this instruction as ready to commit. */ 494 void setCanCommit() { canCommit = true; } 495 496 /** Clears this instruction as being ready to commit. */ 497 void clearCanCommit() { canCommit = false; } 498 499 /** Returns whether or not this instruction is ready to commit. */ 500 bool readyToCommit() const { return canCommit; } 501 502 /** Sets this instruction as committed. */ 503 void setCommitted() { committed = true; } 504 505 /** Returns whether or not this instruction is committed. */ 506 bool isCommitted() const { return committed; } 507 508 /** Sets this instruction as squashed. */ 509 void setSquashed() { squashed = true; } 510 511 /** Returns whether or not this instruction is squashed. */ 512 bool isSquashed() const { return squashed; } 513 514 //Instruction Queue Entry 515 //----------------------- 516 /** Sets this instruction as a entry the IQ. */ 517 void setInIQ() { iqEntry = true; } 518 519 /** Sets this instruction as a entry the IQ. */ 520 void removeInIQ() { iqEntry = false; } 521 522 /** Sets this instruction as squashed in the IQ. */ 523 void setSquashedInIQ() { squashedInIQ = true; squashed = true;} 524 525 /** Returns whether or not this instruction is squashed in the IQ. */ 526 bool isSquashedInIQ() const { return squashedInIQ; } 527 528 /** Returns whether or not this instruction has issued. */ 529 bool isInIQ() const { return iqEntry; } 530 531 532 //Load / Store Queue Functions 533 //----------------------- 534 /** Sets this instruction as a entry the LSQ. */ 535 void setInLSQ() { lsqEntry = true; } 536 537 /** Sets this instruction as a entry the LSQ. */ 538 void removeInLSQ() { lsqEntry = false; } 539 540 /** Sets this instruction as squashed in the LSQ. */ 541 void setSquashedInLSQ() { squashedInLSQ = true;} 542 543 /** Returns whether or not this instruction is squashed in the LSQ. */ 544 bool isSquashedInLSQ() const { return squashedInLSQ; } 545 546 /** Returns whether or not this instruction is in the LSQ. */ 547 bool isInLSQ() const { return lsqEntry; } 548 549 550 //Reorder Buffer Functions 551 //----------------------- 552 /** Sets this instruction as a entry the ROB. */ 553 void setInROB() { robEntry = true; } 554 555 /** Sets this instruction as a entry the ROB. */ 556 void removeInROB() { robEntry = false; } 557 558 /** Sets this instruction as squashed in the ROB. */ 559 void setSquashedInROB() { squashedInROB = true; } 560 561 /** Returns whether or not this instruction is squashed in the ROB. */ 562 bool isSquashedInROB() const { return squashedInROB; } 563 564 /** Returns whether or not this instruction is in the ROB. */ 565 bool isInROB() const { return robEntry; } 566 567 /** Read the PC of this instruction. */ 568 const Addr readPC() const { return PC; } 569 570 /** Set the next PC of this instruction (its actual target). */ 571 void setNextPC(uint64_t val) 572 { 573 nextPC = val; 574// instResult.integer = val; 575 } 576 577 void setASID(short addr_space_id) { asid = addr_space_id; } 578 579 void setThread(unsigned tid) { threadNumber = tid; } 580 581 void setState(ImplState *state) { thread = state; } 582 583 /** Returns the exec context. 584 * @todo: Remove this once the ExecContext is no longer used. 585 */ 586 ExecContext *xcBase() { return thread->getXCProxy(); } 587 588 private: 589 /** Instruction effective address. 590 * @todo: Consider if this is necessary or not. 591 */ 592 Addr instEffAddr; 593 594 /** Whether or not the effective address calculation is completed. 595 * @todo: Consider if this is necessary or not. 596 */ 597 bool eaCalcDone; 598 599 public: 600 /** Sets the effective address. */ 601 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 602 603 /** Returns the effective address. */ 604 const Addr &getEA() const { return req->vaddr; } 605 606 /** Returns whether or not the eff. addr. calculation has been completed. */ 607 bool doneEACalc() { return eaCalcDone; } 608 609 /** Returns whether or not the eff. addr. source registers are ready. */ 610 bool eaSrcsReady(); 611 612 /** Whether or not the memory operation is done. */ 613 bool memOpDone; 614 615 public: 616 /** Load queue index. */ 617 int16_t lqIdx; 618 619 /** Store queue index. */ 620 int16_t sqIdx; 621 622 bool reachedCommit; 623 624 /** Iterator pointing to this BaseDynInst in the list of all insts. */ 625 ListIt instListIt; 626 627 /** Returns iterator to this instruction in the list of all insts. */ 628 ListIt &getInstListIt() { return instListIt; } 629 630 /** Sets iterator for this instruction in the list of all insts. */ 631 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 632}; 633 634template<class Impl> 635template<class T> 636inline Fault 637BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) 638{ 639 if (executed) { 640 fault = cpu->read(req, data, lqIdx); 641 return fault; 642 } 643 644 req = new MemReq(addr, thread->getXCProxy(), sizeof(T), flags); 645 req->asid = asid; 646 req->thread_num = threadNumber; 647 req->pc = this->PC; 648 649 if ((req->vaddr & (TheISA::VMPageSize - 1)) + req->size > 650 TheISA::VMPageSize) { 651 return TheISA::genAlignmentFault(); 652 } 653 654 fault = cpu->translateDataReadReq(req); 655 656 effAddr = req->vaddr; 657 physEffAddr = req->paddr; 658 memReqFlags = req->flags; 659 660 if (fault == NoFault) { 661#if FULL_SYSTEM 662 if (cpu->system->memctrl->badaddr(physEffAddr)) { 663 fault = TheISA::genMachineCheckFault(); 664 data = (T)-1; 665 this->setExecuted(); 666 } else { 667 fault = cpu->read(req, data, lqIdx); 668 } 669#else 670 fault = cpu->read(req, data, lqIdx); 671#endif 672 } else { 673 // Return a fixed value to keep simulation deterministic even 674 // along misspeculated paths. 675 data = (T)-1; 676 677 // Commit will have to clean up whatever happened. Set this 678 // instruction as executed. 679 this->setExecuted(); 680 } 681 682 if (traceData) { 683 traceData->setAddr(addr); 684 traceData->setData(data); 685 } 686 687 return fault; 688} 689 690template<class Impl> 691template<class T> 692inline Fault 693BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) 694{ 695 if (traceData) { 696 traceData->setAddr(addr); 697 traceData->setData(data); 698 } 699 700 req = new MemReq(addr, thread->getXCProxy(), sizeof(T), flags); 701 702 req->asid = asid; 703 req->thread_num = threadNumber; 704 req->pc = this->PC; 705 706 if ((req->vaddr & (TheISA::VMPageSize - 1)) + req->size > 707 TheISA::VMPageSize) { 708 return TheISA::genAlignmentFault(); 709 } 710 711 fault = cpu->translateDataWriteReq(req); 712 713 effAddr = req->vaddr; 714 physEffAddr = req->paddr; 715 memReqFlags = req->flags; 716 717 if (fault == NoFault) { 718#if FULL_SYSTEM 719 if (cpu->system->memctrl->badaddr(physEffAddr)) { 720 fault = TheISA::genMachineCheckFault(); 721 } else { 722 fault = cpu->write(req, data, sqIdx); 723 } 724#else 725 fault = cpu->write(req, data, sqIdx); 726#endif 727 } 728 729 if (res) { 730 // always return some result to keep misspeculated paths 731 // (which will ignore faults) deterministic 732 *res = (fault == NoFault) ? req->result : 0; 733 } 734 735 return fault; 736} 737 738#endif // __CPU_BASE_DYN_INST_HH__ 739