base_dyn_inst.hh revision 2190
111731Sjason@lowepower.com/* 211731Sjason@lowepower.com * Copyright (c) 2004-2005 The Regents of The University of Michigan 311731Sjason@lowepower.com * All rights reserved. 411731Sjason@lowepower.com * 511731Sjason@lowepower.com * Redistribution and use in source and binary forms, with or without 611731Sjason@lowepower.com * modification, are permitted provided that the following conditions are 711731Sjason@lowepower.com * met: redistributions of source code must retain the above copyright 811731Sjason@lowepower.com * notice, this list of conditions and the following disclaimer; 911731Sjason@lowepower.com * redistributions in binary form must reproduce the above copyright 1011731Sjason@lowepower.com * notice, this list of conditions and the following disclaimer in the 1111731Sjason@lowepower.com * documentation and/or other materials provided with the distribution; 1211731Sjason@lowepower.com * neither the name of the copyright holders nor the names of its 1311731Sjason@lowepower.com * contributors may be used to endorse or promote products derived from 1411731Sjason@lowepower.com * this software without specific prior written permission. 1511731Sjason@lowepower.com * 1611731Sjason@lowepower.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1711731Sjason@lowepower.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1811731Sjason@lowepower.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1911731Sjason@lowepower.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2011731Sjason@lowepower.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2111731Sjason@lowepower.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2211731Sjason@lowepower.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2311731Sjason@lowepower.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2411731Sjason@lowepower.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2511731Sjason@lowepower.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2611731Sjason@lowepower.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2711731Sjason@lowepower.com */ 2811731Sjason@lowepower.com 2911731Sjason@lowepower.com#ifndef __CPU_BASE_DYN_INST_HH__ 3011731Sjason@lowepower.com#define __CPU_BASE_DYN_INST_HH__ 3111731Sjason@lowepower.com 3211731Sjason@lowepower.com#include <string> 3311731Sjason@lowepower.com#include <vector> 3411731Sjason@lowepower.com 3511731Sjason@lowepower.com#include "base/fast_alloc.hh" 3611731Sjason@lowepower.com#include "base/trace.hh" 3711731Sjason@lowepower.com#include "config/full_system.hh" 3811731Sjason@lowepower.com#include "cpu/exetrace.hh" 3911731Sjason@lowepower.com#include "cpu/inst_seq.hh" 4011731Sjason@lowepower.com#include "cpu/o3/comm.hh" 4111731Sjason@lowepower.com#include "cpu/static_inst.hh" 4211731Sjason@lowepower.com#include "encumbered/cpu/full/bpred_update.hh" 4311731Sjason@lowepower.com#include "encumbered/cpu/full/op_class.hh" 4411731Sjason@lowepower.com#include "encumbered/cpu/full/spec_memory.hh" 4511731Sjason@lowepower.com#include "encumbered/cpu/full/spec_state.hh" 4611731Sjason@lowepower.com#include "encumbered/mem/functional/main.hh" 4711731Sjason@lowepower.com 4811731Sjason@lowepower.com/** 4911731Sjason@lowepower.com * @file 5011731Sjason@lowepower.com * Defines a dynamic instruction context. 5111731Sjason@lowepower.com */ 5211731Sjason@lowepower.com 5311731Sjason@lowepower.com// Forward declaration. 5411731Sjason@lowepower.comclass StaticInstPtr; 5511731Sjason@lowepower.com 5611731Sjason@lowepower.comtemplate <class Impl> 5711731Sjason@lowepower.comclass BaseDynInst : public FastAlloc, public RefCounted 5811731Sjason@lowepower.com{ 5911731Sjason@lowepower.com public: 6011731Sjason@lowepower.com // Typedef for the CPU. 6111731Sjason@lowepower.com typedef typename Impl::FullCPU FullCPU; 6211731Sjason@lowepower.com 6311731Sjason@lowepower.com /// Binary machine instruction type. 6411731Sjason@lowepower.com typedef TheISA::MachInst MachInst; 6511731Sjason@lowepower.com /// Logical register index type. 6611731Sjason@lowepower.com typedef TheISA::RegIndex RegIndex; 6711731Sjason@lowepower.com /// Integer register index type. 6811731Sjason@lowepower.com typedef TheISA::IntReg IntReg; 6911731Sjason@lowepower.com 7011731Sjason@lowepower.com enum { 7111731Sjason@lowepower.com MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 7211731Sjason@lowepower.com MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs 7311731Sjason@lowepower.com }; 7411731Sjason@lowepower.com 7511731Sjason@lowepower.com /** The static inst used by this dyn inst. */ 7611731Sjason@lowepower.com StaticInstPtr staticInst; 7711731Sjason@lowepower.com 7811731Sjason@lowepower.com //////////////////////////////////////////// 7911731Sjason@lowepower.com // 8011731Sjason@lowepower.com // INSTRUCTION EXECUTION 8111731Sjason@lowepower.com // 8211731Sjason@lowepower.com //////////////////////////////////////////// 8311731Sjason@lowepower.com Trace::InstRecord *traceData; 8411731Sjason@lowepower.com 8511731Sjason@lowepower.com template <class T> 8611731Sjason@lowepower.com Fault read(Addr addr, T &data, unsigned flags); 8711731Sjason@lowepower.com 8811731Sjason@lowepower.com template <class T> 8911731Sjason@lowepower.com Fault write(T data, Addr addr, unsigned flags, 9011731Sjason@lowepower.com uint64_t *res); 9111731Sjason@lowepower.com 9211731Sjason@lowepower.com void prefetch(Addr addr, unsigned flags); 9311731Sjason@lowepower.com void writeHint(Addr addr, int size, unsigned flags); 9411731Sjason@lowepower.com Fault copySrcTranslate(Addr src); 9511731Sjason@lowepower.com Fault copy(Addr dest); 9611731Sjason@lowepower.com 9711731Sjason@lowepower.com /** @todo: Consider making this private. */ 9811731Sjason@lowepower.com public: 9911731Sjason@lowepower.com /** Is this instruction valid. */ 10011731Sjason@lowepower.com bool valid; 10111731Sjason@lowepower.com 10211731Sjason@lowepower.com /** The sequence number of the instruction. */ 10311731Sjason@lowepower.com InstSeqNum seqNum; 10411731Sjason@lowepower.com 10511731Sjason@lowepower.com /** How many source registers are ready. */ 10611731Sjason@lowepower.com unsigned readyRegs; 10711731Sjason@lowepower.com 10811731Sjason@lowepower.com /** Is the instruction completed. */ 10911731Sjason@lowepower.com bool completed; 11011731Sjason@lowepower.com 11111731Sjason@lowepower.com /** Can this instruction issue. */ 11211731Sjason@lowepower.com bool canIssue; 11311731Sjason@lowepower.com 11411731Sjason@lowepower.com /** Has this instruction issued. */ 11511731Sjason@lowepower.com bool issued; 11611731Sjason@lowepower.com 11711731Sjason@lowepower.com /** Has this instruction executed (or made it through execute) yet. */ 11811731Sjason@lowepower.com bool executed; 11911731Sjason@lowepower.com 12011731Sjason@lowepower.com /** Can this instruction commit. */ 12111731Sjason@lowepower.com bool canCommit; 12211731Sjason@lowepower.com 12311731Sjason@lowepower.com /** Is this instruction squashed. */ 12411731Sjason@lowepower.com bool squashed; 12511731Sjason@lowepower.com 12611731Sjason@lowepower.com /** Is this instruction squashed in the instruction queue. */ 12711731Sjason@lowepower.com bool squashedInIQ; 12811731Sjason@lowepower.com 12911731Sjason@lowepower.com /** Is this a recover instruction. */ 13011731Sjason@lowepower.com bool recoverInst; 13111731Sjason@lowepower.com 13211731Sjason@lowepower.com /** Is this a thread blocking instruction. */ 13311731Sjason@lowepower.com bool blockingInst; /* this inst has called thread_block() */ 13411731Sjason@lowepower.com 13511731Sjason@lowepower.com /** Is this a thread syncrhonization instruction. */ 13611731Sjason@lowepower.com bool threadsyncWait; 13711731Sjason@lowepower.com 13811731Sjason@lowepower.com /** The thread this instruction is from. */ 13911731Sjason@lowepower.com short threadNumber; 14011731Sjason@lowepower.com 14111731Sjason@lowepower.com /** data address space ID, for loads & stores. */ 14211731Sjason@lowepower.com short asid; 14311731Sjason@lowepower.com 14411731Sjason@lowepower.com /** Pointer to the FullCPU object. */ 14511731Sjason@lowepower.com FullCPU *cpu; 14611731Sjason@lowepower.com 14711731Sjason@lowepower.com /** Pointer to the exec context. Will not exist in the final version. */ 14811731Sjason@lowepower.com CPUExecContext *cpuXC; 14911731Sjason@lowepower.com 15011731Sjason@lowepower.com /** The kind of fault this instruction has generated. */ 15111731Sjason@lowepower.com Fault fault; 15211731Sjason@lowepower.com 15311731Sjason@lowepower.com /** The effective virtual address (lds & stores only). */ 15411731Sjason@lowepower.com Addr effAddr; 15511731Sjason@lowepower.com 15611731Sjason@lowepower.com /** The effective physical address. */ 15711731Sjason@lowepower.com Addr physEffAddr; 15811731Sjason@lowepower.com 15911731Sjason@lowepower.com /** Effective virtual address for a copy source. */ 16011731Sjason@lowepower.com Addr copySrcEffAddr; 16111731Sjason@lowepower.com 16211731Sjason@lowepower.com /** Effective physical address for a copy source. */ 16311731Sjason@lowepower.com Addr copySrcPhysEffAddr; 16411731Sjason@lowepower.com 16511731Sjason@lowepower.com /** The memory request flags (from translation). */ 16611731Sjason@lowepower.com unsigned memReqFlags; 16711731Sjason@lowepower.com 16811731Sjason@lowepower.com /** The size of the data to be stored. */ 16911731Sjason@lowepower.com int storeSize; 17012137Sar4jc@virginia.edu 17112137Sar4jc@virginia.edu /** The data to be stored. */ 17211731Sjason@lowepower.com IntReg storeData; 17311731Sjason@lowepower.com 17411731Sjason@lowepower.com union Result { 17511731Sjason@lowepower.com uint64_t integer; 17611731Sjason@lowepower.com float fp; 17711731Sjason@lowepower.com double dbl; 17811731Sjason@lowepower.com }; 17911731Sjason@lowepower.com 18011731Sjason@lowepower.com /** The result of the instruction; assumes for now that there's only one 18111731Sjason@lowepower.com * destination register. 18211731Sjason@lowepower.com */ 18311731Sjason@lowepower.com Result instResult; 18411731Sjason@lowepower.com 18511731Sjason@lowepower.com /** PC of this instruction. */ 18611731Sjason@lowepower.com Addr PC; 18711731Sjason@lowepower.com 18811731Sjason@lowepower.com /** Next non-speculative PC. It is not filled in at fetch, but rather 18911731Sjason@lowepower.com * once the target of the branch is truly known (either decode or 19011731Sjason@lowepower.com * execute). 19111731Sjason@lowepower.com */ 19211731Sjason@lowepower.com Addr nextPC; 19311731Sjason@lowepower.com 19411731Sjason@lowepower.com /** Predicted next PC. */ 19511731Sjason@lowepower.com Addr predPC; 19611731Sjason@lowepower.com 19711731Sjason@lowepower.com /** Count of total number of dynamic instructions. */ 19811731Sjason@lowepower.com static int instcount; 19911731Sjason@lowepower.com 20011731Sjason@lowepower.com /** Whether or not the source register is ready. Not sure this should be 20111731Sjason@lowepower.com * here vs. the derived class. 20211731Sjason@lowepower.com */ 20311731Sjason@lowepower.com bool _readySrcRegIdx[MaxInstSrcRegs]; 20411731Sjason@lowepower.com 20511731Sjason@lowepower.com public: 20611731Sjason@lowepower.com /** BaseDynInst constructor given a binary instruction. */ 20711731Sjason@lowepower.com BaseDynInst(MachInst inst, Addr PC, Addr Pred_PC, InstSeqNum seq_num, 20811731Sjason@lowepower.com FullCPU *cpu); 20911731Sjason@lowepower.com 21011731Sjason@lowepower.com /** BaseDynInst constructor given a static inst pointer. */ 21111731Sjason@lowepower.com BaseDynInst(StaticInstPtr &_staticInst); 21211731Sjason@lowepower.com 21311731Sjason@lowepower.com /** BaseDynInst destructor. */ 21411731Sjason@lowepower.com ~BaseDynInst(); 21511731Sjason@lowepower.com 21611731Sjason@lowepower.com private: 21711731Sjason@lowepower.com /** Function to initialize variables in the constructors. */ 21811731Sjason@lowepower.com void initVars(); 21911731Sjason@lowepower.com 22011731Sjason@lowepower.com public: 22111731Sjason@lowepower.com void 22211731Sjason@lowepower.com trace_mem(Fault fault, // last fault 22311731Sjason@lowepower.com MemCmd cmd, // last command 22411731Sjason@lowepower.com Addr addr, // virtual address of access 22511731Sjason@lowepower.com void *p, // memory accessed 22611731Sjason@lowepower.com int nbytes); // access size 22711731Sjason@lowepower.com 22811731Sjason@lowepower.com /** Dumps out contents of this BaseDynInst. */ 22911731Sjason@lowepower.com void dump(); 23011731Sjason@lowepower.com 23111731Sjason@lowepower.com /** Dumps out contents of this BaseDynInst into given string. */ 23211731Sjason@lowepower.com void dump(std::string &outstring); 23311731Sjason@lowepower.com 23411731Sjason@lowepower.com /** Returns the fault type. */ 23511731Sjason@lowepower.com Fault getFault() { return fault; } 23611731Sjason@lowepower.com 23711731Sjason@lowepower.com /** Checks whether or not this instruction has had its branch target 23811731Sjason@lowepower.com * calculated yet. For now it is not utilized and is hacked to be 23911731Sjason@lowepower.com * always false. 24011731Sjason@lowepower.com */ 24111731Sjason@lowepower.com bool doneTargCalc() { return false; } 24211731Sjason@lowepower.com 24311731Sjason@lowepower.com /** Returns the next PC. This could be the speculative next PC if it is 24412137Sar4jc@virginia.edu * called prior to the actual branch target being calculated. 24512137Sar4jc@virginia.edu */ 24612137Sar4jc@virginia.edu Addr readNextPC() { return nextPC; } 24711731Sjason@lowepower.com 24811731Sjason@lowepower.com /** Set the predicted target of this current instruction. */ 24911731Sjason@lowepower.com void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; } 25011731Sjason@lowepower.com 25111731Sjason@lowepower.com /** Returns the predicted target of the branch. */ 25211731Sjason@lowepower.com Addr readPredTarg() { return predPC; } 25311731Sjason@lowepower.com 25411731Sjason@lowepower.com /** Returns whether the instruction was predicted taken or not. */ 25511731Sjason@lowepower.com bool predTaken() { 25611731Sjason@lowepower.com return( predPC != (PC + sizeof(MachInst) ) ); 25711731Sjason@lowepower.com } 25811731Sjason@lowepower.com 25911731Sjason@lowepower.com /** Returns whether the instruction mispredicted. */ 26011731Sjason@lowepower.com bool mispredicted() { return (predPC != nextPC); } 26111731Sjason@lowepower.com 26211731Sjason@lowepower.com // 26311731Sjason@lowepower.com // Instruction types. Forward checks to StaticInst object. 26411731Sjason@lowepower.com // 26511731Sjason@lowepower.com bool isNop() const { return staticInst->isNop(); } 26611731Sjason@lowepower.com bool isMemRef() const { return staticInst->isMemRef(); } 26711731Sjason@lowepower.com bool isLoad() const { return staticInst->isLoad(); } 26811731Sjason@lowepower.com bool isStore() const { return staticInst->isStore(); } 26911731Sjason@lowepower.com bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 27011731Sjason@lowepower.com bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 27111731Sjason@lowepower.com bool isCopy() const { return staticInst->isCopy(); } 27211731Sjason@lowepower.com bool isInteger() const { return staticInst->isInteger(); } 27311731Sjason@lowepower.com bool isFloating() const { return staticInst->isFloating(); } 27411731Sjason@lowepower.com bool isControl() const { return staticInst->isControl(); } 27511731Sjason@lowepower.com bool isCall() const { return staticInst->isCall(); } 27611731Sjason@lowepower.com bool isReturn() const { return staticInst->isReturn(); } 27711731Sjason@lowepower.com bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 27811731Sjason@lowepower.com bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 27911731Sjason@lowepower.com bool isCondCtrl() const { return staticInst->isCondCtrl(); } 28011731Sjason@lowepower.com bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 28111731Sjason@lowepower.com bool isThreadSync() const { return staticInst->isThreadSync(); } 28211731Sjason@lowepower.com bool isSerializing() const { return staticInst->isSerializing(); } 28311731Sjason@lowepower.com bool isMemBarrier() const { return staticInst->isMemBarrier(); } 28411731Sjason@lowepower.com bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 28511731Sjason@lowepower.com bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 28611731Sjason@lowepower.com 28711731Sjason@lowepower.com /** Returns the opclass of this instruction. */ 28811731Sjason@lowepower.com OpClass opClass() const { return staticInst->opClass(); } 28911731Sjason@lowepower.com 29011731Sjason@lowepower.com /** Returns the branch target address. */ 29111731Sjason@lowepower.com Addr branchTarget() const { return staticInst->branchTarget(PC); } 29211731Sjason@lowepower.com 29311731Sjason@lowepower.com /** Number of source registers. */ 29411731Sjason@lowepower.com int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 29511731Sjason@lowepower.com 29611731Sjason@lowepower.com /** Number of destination registers. */ 29711731Sjason@lowepower.com int8_t numDestRegs() const { return staticInst->numDestRegs(); } 29811731Sjason@lowepower.com 29911731Sjason@lowepower.com // the following are used to track physical register usage 30011731Sjason@lowepower.com // for machines with separate int & FP reg files 30111731Sjason@lowepower.com int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 30211731Sjason@lowepower.com int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 30311731Sjason@lowepower.com 30411731Sjason@lowepower.com /** Returns the logical register index of the i'th destination register. */ 30511731Sjason@lowepower.com RegIndex destRegIdx(int i) const 30611731Sjason@lowepower.com { 30711731Sjason@lowepower.com return staticInst->destRegIdx(i); 30811731Sjason@lowepower.com } 30911731Sjason@lowepower.com 31011731Sjason@lowepower.com /** Returns the logical register index of the i'th source register. */ 31111731Sjason@lowepower.com RegIndex srcRegIdx(int i) const 31211731Sjason@lowepower.com { 31311731Sjason@lowepower.com return staticInst->srcRegIdx(i); 31411731Sjason@lowepower.com } 31511731Sjason@lowepower.com 31611731Sjason@lowepower.com /** Returns the result of an integer instruction. */ 31711731Sjason@lowepower.com uint64_t readIntResult() { return instResult.integer; } 31811731Sjason@lowepower.com 31911731Sjason@lowepower.com /** Returns the result of a floating point instruction. */ 32011731Sjason@lowepower.com float readFloatResult() { return instResult.fp; } 32111731Sjason@lowepower.com 32211731Sjason@lowepower.com /** Returns the result of a floating point (double) instruction. */ 32311731Sjason@lowepower.com double readDoubleResult() { return instResult.dbl; } 32411731Sjason@lowepower.com 32511731Sjason@lowepower.com //Push to .cc file. 32611731Sjason@lowepower.com /** Records that one of the source registers is ready. */ 32711731Sjason@lowepower.com void markSrcRegReady() 32811731Sjason@lowepower.com { 32911731Sjason@lowepower.com ++readyRegs; 33011731Sjason@lowepower.com if(readyRegs == numSrcRegs()) { 33111731Sjason@lowepower.com canIssue = true; 33211731Sjason@lowepower.com } 33311731Sjason@lowepower.com } 33411731Sjason@lowepower.com 33511731Sjason@lowepower.com /** Marks a specific register as ready. 33611731Sjason@lowepower.com * @todo: Move this to .cc file. 33711731Sjason@lowepower.com */ 33811731Sjason@lowepower.com void markSrcRegReady(RegIndex src_idx) 33911731Sjason@lowepower.com { 34011731Sjason@lowepower.com ++readyRegs; 34111731Sjason@lowepower.com 34211731Sjason@lowepower.com _readySrcRegIdx[src_idx] = 1; 34311731Sjason@lowepower.com 34411731Sjason@lowepower.com if(readyRegs == numSrcRegs()) { 34511731Sjason@lowepower.com canIssue = true; 34611731Sjason@lowepower.com } 34711731Sjason@lowepower.com } 34811731Sjason@lowepower.com 34911731Sjason@lowepower.com /** Returns if a source register is ready. */ 35011731Sjason@lowepower.com bool isReadySrcRegIdx(int idx) const 35111731Sjason@lowepower.com { 35211731Sjason@lowepower.com return this->_readySrcRegIdx[idx]; 35311731Sjason@lowepower.com } 35411731Sjason@lowepower.com 35511731Sjason@lowepower.com /** Sets this instruction as completed. */ 35611731Sjason@lowepower.com void setCompleted() { completed = true; } 35711731Sjason@lowepower.com 35811731Sjason@lowepower.com /** Returns whethe or not this instruction is completed. */ 35911731Sjason@lowepower.com bool isCompleted() const { return completed; } 36011731Sjason@lowepower.com 36111731Sjason@lowepower.com /** Sets this instruction as ready to issue. */ 36211731Sjason@lowepower.com void setCanIssue() { canIssue = true; } 36311731Sjason@lowepower.com 36411731Sjason@lowepower.com /** Returns whether or not this instruction is ready to issue. */ 36511731Sjason@lowepower.com bool readyToIssue() const { return canIssue; } 36611731Sjason@lowepower.com 36711731Sjason@lowepower.com /** Sets this instruction as issued from the IQ. */ 36811731Sjason@lowepower.com void setIssued() { issued = true; } 36911731Sjason@lowepower.com 37011731Sjason@lowepower.com /** Returns whether or not this instruction has issued. */ 37111731Sjason@lowepower.com bool isIssued() const { return issued; } 37211731Sjason@lowepower.com 37311731Sjason@lowepower.com /** Sets this instruction as executed. */ 37411731Sjason@lowepower.com void setExecuted() { executed = true; } 37511731Sjason@lowepower.com 37611731Sjason@lowepower.com /** Returns whether or not this instruction has executed. */ 37711731Sjason@lowepower.com bool isExecuted() const { return executed; } 37811731Sjason@lowepower.com 37911731Sjason@lowepower.com /** Sets this instruction as ready to commit. */ 38011731Sjason@lowepower.com void setCanCommit() { canCommit = true; } 38111731Sjason@lowepower.com 38211731Sjason@lowepower.com /** Clears this instruction as being ready to commit. */ 38311731Sjason@lowepower.com void clearCanCommit() { canCommit = false; } 38411731Sjason@lowepower.com 38511731Sjason@lowepower.com /** Returns whether or not this instruction is ready to commit. */ 38611731Sjason@lowepower.com bool readyToCommit() const { return canCommit; } 38711731Sjason@lowepower.com 38811731Sjason@lowepower.com /** Sets this instruction as squashed. */ 38911731Sjason@lowepower.com void setSquashed() { squashed = true; } 39011731Sjason@lowepower.com 39111731Sjason@lowepower.com /** Returns whether or not this instruction is squashed. */ 39211731Sjason@lowepower.com bool isSquashed() const { return squashed; } 39311731Sjason@lowepower.com 39411731Sjason@lowepower.com /** Sets this instruction as squashed in the IQ. */ 39511731Sjason@lowepower.com void setSquashedInIQ() { squashedInIQ = true; } 39611731Sjason@lowepower.com 39711731Sjason@lowepower.com /** Returns whether or not this instruction is squashed in the IQ. */ 39811731Sjason@lowepower.com bool isSquashedInIQ() const { return squashedInIQ; } 39911731Sjason@lowepower.com 40011731Sjason@lowepower.com /** Read the PC of this instruction. */ 40111731Sjason@lowepower.com const Addr readPC() const { return PC; } 40211731Sjason@lowepower.com 40311731Sjason@lowepower.com /** Set the next PC of this instruction (its actual target). */ 40411731Sjason@lowepower.com void setNextPC(uint64_t val) { nextPC = val; } 40511731Sjason@lowepower.com 40611731Sjason@lowepower.com /** Returns the exec context. 40711731Sjason@lowepower.com * @todo: Remove this once the ExecContext is no longer used. 40811731Sjason@lowepower.com */ 40911731Sjason@lowepower.com ExecContext *xcBase() { return cpuXC->getProxy(); } 41011731Sjason@lowepower.com 41111731Sjason@lowepower.com private: 41211731Sjason@lowepower.com /** Instruction effective address. 41311731Sjason@lowepower.com * @todo: Consider if this is necessary or not. 41411731Sjason@lowepower.com */ 41511731Sjason@lowepower.com Addr instEffAddr; 41611731Sjason@lowepower.com /** Whether or not the effective address calculation is completed. 41711731Sjason@lowepower.com * @todo: Consider if this is necessary or not. 41811731Sjason@lowepower.com */ 41911731Sjason@lowepower.com bool eaCalcDone; 42011731Sjason@lowepower.com 42111731Sjason@lowepower.com public: 42211731Sjason@lowepower.com /** Sets the effective address. */ 42311731Sjason@lowepower.com void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 42411731Sjason@lowepower.com 42511731Sjason@lowepower.com /** Returns the effective address. */ 42611731Sjason@lowepower.com const Addr &getEA() const { return instEffAddr; } 42711731Sjason@lowepower.com 42811731Sjason@lowepower.com /** Returns whether or not the eff. addr. calculation has been completed. */ 42911731Sjason@lowepower.com bool doneEACalc() { return eaCalcDone; } 43011731Sjason@lowepower.com 43111731Sjason@lowepower.com /** Returns whether or not the eff. addr. source registers are ready. */ 43211731Sjason@lowepower.com bool eaSrcsReady(); 43311731Sjason@lowepower.com 43411731Sjason@lowepower.com public: 43511731Sjason@lowepower.com /** Load queue index. */ 43611731Sjason@lowepower.com int16_t lqIdx; 43711731Sjason@lowepower.com 43811731Sjason@lowepower.com /** Store queue index. */ 43911731Sjason@lowepower.com int16_t sqIdx; 44011731Sjason@lowepower.com}; 44111731Sjason@lowepower.com 44211731Sjason@lowepower.comtemplate<class Impl> 44311731Sjason@lowepower.comtemplate<class T> 44411731Sjason@lowepower.cominline Fault 44511731Sjason@lowepower.comBaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) 44611731Sjason@lowepower.com{ 44711731Sjason@lowepower.com MemReqPtr req = new MemReq(addr, cpuXC->getProxy(), sizeof(T), flags); 44811731Sjason@lowepower.com req->asid = asid; 44911731Sjason@lowepower.com 45011731Sjason@lowepower.com fault = cpu->translateDataReadReq(req); 45111731Sjason@lowepower.com 45211731Sjason@lowepower.com // Record key MemReq parameters so we can generate another one 45311731Sjason@lowepower.com // just like it for the timing access without calling translate() 45411731Sjason@lowepower.com // again (which might mess up the TLB). 45511731Sjason@lowepower.com // Do I ever really need this? -KTL 3/05 45611731Sjason@lowepower.com effAddr = req->vaddr; 45711731Sjason@lowepower.com physEffAddr = req->paddr; 45811731Sjason@lowepower.com memReqFlags = req->flags; 45911731Sjason@lowepower.com 46011731Sjason@lowepower.com /** 46111731Sjason@lowepower.com * @todo 46211731Sjason@lowepower.com * Replace the disjoint functional memory with a unified one and remove 46311731Sjason@lowepower.com * this hack. 46411731Sjason@lowepower.com */ 46511731Sjason@lowepower.com#if !FULL_SYSTEM 46611731Sjason@lowepower.com req->paddr = req->vaddr; 46711731Sjason@lowepower.com#endif 46811731Sjason@lowepower.com 46911731Sjason@lowepower.com if (fault == NoFault) { 47011731Sjason@lowepower.com fault = cpu->read(req, data, lqIdx); 47111731Sjason@lowepower.com } else { 47211731Sjason@lowepower.com // Return a fixed value to keep simulation deterministic even 47311731Sjason@lowepower.com // along misspeculated paths. 47411731Sjason@lowepower.com data = (T)-1; 47511731Sjason@lowepower.com } 47611731Sjason@lowepower.com 47711731Sjason@lowepower.com if (traceData) { 47811731Sjason@lowepower.com traceData->setAddr(addr); 47911731Sjason@lowepower.com traceData->setData(data); 48011731Sjason@lowepower.com } 48111731Sjason@lowepower.com 48211731Sjason@lowepower.com return fault; 48311731Sjason@lowepower.com} 48411731Sjason@lowepower.com 48511731Sjason@lowepower.comtemplate<class Impl> 48611731Sjason@lowepower.comtemplate<class T> 48711731Sjason@lowepower.cominline Fault 48811731Sjason@lowepower.comBaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) 48911731Sjason@lowepower.com{ 49011731Sjason@lowepower.com if (traceData) { 49111731Sjason@lowepower.com traceData->setAddr(addr); 49211731Sjason@lowepower.com traceData->setData(data); 49311731Sjason@lowepower.com } 49411731Sjason@lowepower.com 49511731Sjason@lowepower.com MemReqPtr req = new MemReq(addr, cpuXC->getProxy(), sizeof(T), flags); 49611731Sjason@lowepower.com 49711731Sjason@lowepower.com req->asid = asid; 49811731Sjason@lowepower.com 49911731Sjason@lowepower.com fault = cpu->translateDataWriteReq(req); 50011731Sjason@lowepower.com 50111731Sjason@lowepower.com // Record key MemReq parameters so we can generate another one 50211731Sjason@lowepower.com // just like it for the timing access without calling translate() 50311731Sjason@lowepower.com // again (which might mess up the TLB). 50411731Sjason@lowepower.com effAddr = req->vaddr; 50511731Sjason@lowepower.com physEffAddr = req->paddr; 50611731Sjason@lowepower.com memReqFlags = req->flags; 50711731Sjason@lowepower.com 50811731Sjason@lowepower.com /** 50911731Sjason@lowepower.com * @todo 51011731Sjason@lowepower.com * Replace the disjoint functional memory with a unified one and remove 51111731Sjason@lowepower.com * this hack. 51211731Sjason@lowepower.com */ 51311731Sjason@lowepower.com#if !FULL_SYSTEM 51411731Sjason@lowepower.com req->paddr = req->vaddr; 51511731Sjason@lowepower.com#endif 51611731Sjason@lowepower.com 51711731Sjason@lowepower.com if (fault == NoFault) { 51811731Sjason@lowepower.com fault = cpu->write(req, data, sqIdx); 51911731Sjason@lowepower.com } 52011731Sjason@lowepower.com 52111731Sjason@lowepower.com if (res) { 52211731Sjason@lowepower.com // always return some result to keep misspeculated paths 52311731Sjason@lowepower.com // (which will ignore faults) deterministic 52411731Sjason@lowepower.com *res = (fault == NoFault) ? req->result : 0; 52511731Sjason@lowepower.com } 52611731Sjason@lowepower.com 52711731Sjason@lowepower.com return fault; 52811731Sjason@lowepower.com} 52911731Sjason@lowepower.com 53011731Sjason@lowepower.com#endif // __CPU_BASE_DYN_INST_HH__ 53111731Sjason@lowepower.com