base_dyn_inst.hh revision 11303:f694764d656d
12315SN/A/* 22332SN/A * Copyright (c) 2011,2013 ARM Limited 32315SN/A * Copyright (c) 2013 Advanced Micro Devices, Inc. 42315SN/A * All rights reserved. 52315SN/A * 62315SN/A * The license below extends only to copyright in the software and shall 72315SN/A * not be construed as granting a license to any other intellectual 82315SN/A * property including but not limited to intellectual property relating 92315SN/A * to a hardware implementation of the functionality of the software 102315SN/A * licensed hereunder. You may use the software subject to the license 112315SN/A * terms below provided that you ensure that this notice is replicated 122315SN/A * unmodified and in its entirety in all distributions of the software, 132315SN/A * modified or unmodified, in source code or in binary form. 142315SN/A * 152315SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 162315SN/A * Copyright (c) 2009 The University of Edinburgh 172315SN/A * All rights reserved. 182315SN/A * 192315SN/A * Redistribution and use in source and binary forms, with or without 202315SN/A * modification, are permitted provided that the following conditions are 212315SN/A * met: redistributions of source code must retain the above copyright 222315SN/A * notice, this list of conditions and the following disclaimer; 232315SN/A * redistributions in binary form must reproduce the above copyright 242315SN/A * notice, this list of conditions and the following disclaimer in the 252315SN/A * documentation and/or other materials provided with the distribution; 262315SN/A * neither the name of the copyright holders nor the names of its 272689SN/A * contributors may be used to endorse or promote products derived from 282689SN/A * this software without specific prior written permission. 292315SN/A * 302315SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 312315SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 322315SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 332315SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 342315SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 356658Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 362315SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 372315SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 382683SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 392680SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 402315SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 412315SN/A * 422315SN/A * Authors: Kevin Lim 432315SN/A * Timothy M. Jones 442315SN/A */ 452315SN/A 462315SN/A#ifndef __CPU_BASE_DYN_INST_HH__ 472315SN/A#define __CPU_BASE_DYN_INST_HH__ 482315SN/A 492315SN/A#include <array> 502315SN/A#include <bitset> 512315SN/A#include <list> 522315SN/A#include <string> 532315SN/A#include <queue> 542732SN/A 552315SN/A#include "arch/generic/tlb.hh" 562315SN/A#include "arch/utility.hh" 572315SN/A#include "base/trace.hh" 582332SN/A#include "config/the_isa.hh" 592332SN/A#include "cpu/checker/cpu.hh" 602332SN/A#include "cpu/o3/comm.hh" 612332SN/A#include "cpu/exec_context.hh" 622332SN/A#include "cpu/exetrace.hh" 632315SN/A#include "cpu/inst_seq.hh" 642315SN/A#include "cpu/op_class.hh" 652315SN/A#include "cpu/static_inst.hh" 662315SN/A#include "cpu/translation.hh" 672315SN/A#include "mem/packet.hh" 682315SN/A#include "sim/byteswap.hh" 692315SN/A#include "sim/system.hh" 702315SN/A 712315SN/A/** 722315SN/A * @file 732315SN/A * Defines a dynamic instruction context. 742315SN/A */ 752315SN/A 762315SN/Atemplate <class Impl> 772315SN/Aclass BaseDynInst : public ExecContext, public RefCounted 782315SN/A{ 792315SN/A public: 802315SN/A // Typedef for the CPU. 812315SN/A typedef typename Impl::CPUType ImplCPU; 822315SN/A typedef typename ImplCPU::ImplState ImplState; 832315SN/A 842315SN/A // Logical register index type. 852315SN/A typedef TheISA::RegIndex RegIndex; 862315SN/A 872315SN/A // The DynInstPtr type. 882315SN/A typedef typename Impl::DynInstPtr DynInstPtr; 892315SN/A typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr; 902315SN/A 912315SN/A // The list of instructions iterator type. 922315SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 932315SN/A 942315SN/A enum { 952315SN/A MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 962354SN/A MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs 972354SN/A }; 982332SN/A 992332SN/A union Result { 1002332SN/A uint64_t integer; 1012315SN/A double dbl; 1022315SN/A void set(uint64_t i) { integer = i; } 1032315SN/A void set(double d) { dbl = d; } 1042315SN/A void get(uint64_t& i) { i = integer; } 1052315SN/A void get(double& d) { d = dbl; } 1062679SN/A }; 1072315SN/A 1082315SN/A protected: 1092315SN/A enum Status { 1102315SN/A IqEntry, /// Instruction is in the IQ 1112315SN/A RobEntry, /// Instruction is in the ROB 1122683SN/A LsqEntry, /// Instruction is in the LSQ 1132315SN/A Completed, /// Instruction has completed 1142683SN/A ResultReady, /// Instruction has its result 1152315SN/A CanIssue, /// Instruction can issue and execute 1162315SN/A Issued, /// Instruction has issued 1172332SN/A Executed, /// Instruction has executed 1182332SN/A CanCommit, /// Instruction can commit 1192332SN/A AtCommit, /// Instruction has reached commit 1202315SN/A Committed, /// Instruction has committed 1212315SN/A Squashed, /// Instruction is squashed 1222683SN/A SquashedInIQ, /// Instruction is squashed in the IQ 1232315SN/A SquashedInLSQ, /// Instruction is squashed in the LSQ 1242683SN/A SquashedInROB, /// Instruction is squashed in the ROB 1252315SN/A RecoverInst, /// Is a recover instruction 1262315SN/A BlockingInst, /// Is a blocking instruction 1272332SN/A ThreadsyncWait, /// Is a thread synchronization instruction 1282332SN/A SerializeBefore, /// Needs to serialize on 1297823Ssteve.reinhardt@amd.com /// instructions ahead of it 1302732SN/A SerializeAfter, /// Needs to serialize instructions behind it 1312315SN/A SerializeHandled, /// Serialization has been handled 1322315SN/A NumStatus 1332315SN/A }; 1342315SN/A 1352315SN/A enum Flags { 1362315SN/A TranslationStarted, 1372315SN/A TranslationCompleted, 1382683SN/A PossibleLoadViolation, 1392315SN/A HitExternalSnoop, 1402315SN/A EffAddrValid, 1412315SN/A RecordResult, 1422332SN/A Predicate, 1432332SN/A PredTaken, 1442332SN/A /** Whether or not the effective address calculation is completed. 1455543Ssaidi@eecs.umich.edu * @todo: Consider if this is necessary or not. 1462332SN/A */ 1475543Ssaidi@eecs.umich.edu EACalcDone, 1482332SN/A IsStrictlyOrdered, 1492332SN/A ReqMade, 1502683SN/A MemOpDone, 1512679SN/A MaxFlags 1522332SN/A }; 1532679SN/A 1542679SN/A public: 1552683SN/A /** The sequence number of the instruction. */ 1565714Shsul@eecs.umich.edu InstSeqNum seqNum; 1575714Shsul@eecs.umich.edu 1582315SN/A /** The StaticInst used by this BaseDynInst. */ 1595891Sgblack@eecs.umich.edu const StaticInstPtr staticInst; 1602315SN/A 1612315SN/A /** Pointer to the Impl's CPU object. */ 1622323SN/A ImplCPU *cpu; 1632332SN/A 1642332SN/A BaseCPU *getCpuPtr() { return cpu; } 1652332SN/A 1662332SN/A /** Pointer to the thread state. */ 1672332SN/A ImplState *thread; 1682332SN/A 1697823Ssteve.reinhardt@amd.com /** The kind of fault this instruction has generated. */ 1702732SN/A Fault fault; 1712315SN/A 1722323SN/A /** InstRecord that tracks this instructions. */ 1732683SN/A Trace::InstRecord *traceData; 1742683SN/A 1752315SN/A protected: 1762354SN/A /** The result of the instruction; assumes an instruction can have many 1772323SN/A * destination registers. 1782332SN/A */ 1792332SN/A std::queue<Result> instResult; 1802332SN/A 1812323SN/A /** PC state for this instruction. */ 1822323SN/A TheISA::PCState pc; 1832315SN/A 1842315SN/A /* An amalgamation of a lot of boolean values into one */ 1852323SN/A std::bitset<MaxFlags> instFlags; 1863349Sbinkertn@umich.edu 1872679SN/A /** The status of this BaseDynInst. Several bits can be set. */ 1882679SN/A std::bitset<NumStatus> status; 1892679SN/A 1902679SN/A /** Whether or not the source register is ready. 1912679SN/A * @todo: Not sure this should be here vs the derived class. 1922679SN/A */ 1932679SN/A std::bitset<MaxInstSrcRegs> _readySrcRegIdx; 1942315SN/A 1952332SN/A public: 1962323SN/A /** The thread this instruction is from. */ 1972315SN/A ThreadID threadNumber; 1982323SN/A 1992323SN/A /** Iterator pointing to this BaseDynInst in the list of all insts. */ 2002323SN/A ListIt instListIt; 2012323SN/A 2022323SN/A ////////////////////// Branch Data /////////////// 2032315SN/A /** Predicted PC state after this instruction. */ 2043484Sktlim@umich.edu TheISA::PCState predPC; 2053484Sktlim@umich.edu 2063484Sktlim@umich.edu /** The Macroop if one exists */ 2073484Sktlim@umich.edu const StaticInstPtr macroop; 2082332SN/A 2093120Sgblack@eecs.umich.edu /** How many source registers are ready. */ 2103484Sktlim@umich.edu uint8_t readyRegs; 2112315SN/A 2122323SN/A public: 2132323SN/A /////////////////////// Load Store Data ////////////////////// 2142315SN/A /** The effective virtual address (lds & stores only). */ 2152679SN/A Addr effAddr; 2162679SN/A 2172679SN/A /** The effective physical address. */ 2182679SN/A Addr physEffAddrLow; 2192315SN/A 2202315SN/A /** The effective physical address 2212315SN/A * of the second request for a split request 2222315SN/A */ 2232315SN/A Addr physEffAddrHigh; 2242683SN/A 2252315SN/A /** The memory request flags (from translation). */ 2262354SN/A unsigned memReqFlags; 2272354SN/A 2282315SN/A /** data address space ID, for loads & stores. */ 2292315SN/A short asid; 2302315SN/A 2312315SN/A /** The size of the request */ 2322315SN/A uint8_t effSize; 2332315SN/A 2342315SN/A /** Pointer to the data for the memory access. */ 2352315SN/A uint8_t *memData; 2362315SN/A 2372315SN/A /** Load queue index. */ 2382315SN/A int16_t lqIdx; 2397678Sgblack@eecs.umich.edu 2402315SN/A /** Store queue index. */ 2412683SN/A int16_t sqIdx; 2422315SN/A 2432838Sktlim@umich.edu 2442315SN/A /////////////////////// TLB Miss ////////////////////// 2452315SN/A /** 2462315SN/A * Saved memory requests (needed when the DTB address translation is 2472683SN/A * delayed due to a hw page table walk). 2482683SN/A */ 2492315SN/A RequestPtr savedReq; 2502315SN/A RequestPtr savedSreqLow; 2512683SN/A RequestPtr savedSreqHigh; 2522683SN/A 2532683SN/A /////////////////////// Checker ////////////////////// 2542315SN/A // Need a copy of main request pointer to verify on writes. 2552315SN/A RequestPtr reqToVerify; 2562315SN/A 2572315SN/A private: 2582315SN/A /** Instruction effective address. 2592332SN/A * @todo: Consider if this is necessary or not. 2602332SN/A */ 2612332SN/A Addr instEffAddr; 2622315SN/A 2632315SN/A protected: 2642315SN/A /** Flattened register index of the destination registers of this 2652683SN/A * instruction. 2662690SN/A */ 2672315SN/A std::array<TheISA::RegIndex, TheISA::MaxInstDestRegs> _flatDestRegIdx; 2682683SN/A 2692315SN/A /** Physical register index of the destination registers of this 2702315SN/A * instruction. 2712683SN/A */ 2722315SN/A std::array<PhysRegIndex, TheISA::MaxInstDestRegs> _destRegIdx; 2732315SN/A 2742315SN/A /** Physical register index of the source registers of this 2752315SN/A * instruction. 2762332SN/A */ 2772315SN/A std::array<PhysRegIndex, TheISA::MaxInstSrcRegs> _srcRegIdx; 2782315SN/A 2792315SN/A /** Physical register index of the previous producers of the 2802679SN/A * architected destinations. 2812679SN/A */ 2822679SN/A std::array<PhysRegIndex, TheISA::MaxInstDestRegs> _prevDestRegIdx; 2832679SN/A 2842679SN/A 2852332SN/A public: 2862332SN/A /** Records changes to result? */ 2872315SN/A void recordResult(bool f) { instFlags[RecordResult] = f; } 2882315SN/A 2892315SN/A /** Is the effective virtual address valid. */ 2902315SN/A bool effAddrValid() const { return instFlags[EffAddrValid]; } 2912315SN/A 2922315SN/A /** Whether or not the memory operation is done. */ 2932315SN/A bool memOpDone() const { return instFlags[MemOpDone]; } 2942315SN/A void memOpDone(bool f) { instFlags[MemOpDone] = f; } 2952315SN/A 2962354SN/A 2972315SN/A //////////////////////////////////////////// 2982315SN/A // 2992315SN/A // INSTRUCTION EXECUTION 3002315SN/A // 3012840Sktlim@umich.edu //////////////////////////////////////////// 3022315SN/A 3032315SN/A void demapPage(Addr vaddr, uint64_t asn) 3042315SN/A { 3052315SN/A cpu->demapPage(vaddr, asn); 3062315SN/A } 3072315SN/A void demapInstPage(Addr vaddr, uint64_t asn) 3082315SN/A { 3092315SN/A cpu->demapPage(vaddr, asn); 3102315SN/A } 3112315SN/A void demapDataPage(Addr vaddr, uint64_t asn) 3122315SN/A { 3132315SN/A cpu->demapPage(vaddr, asn); 3142315SN/A } 3152315SN/A 3162683SN/A Fault initiateMemRead(Addr addr, unsigned size, unsigned flags); 3172332SN/A 3187823Ssteve.reinhardt@amd.com Fault writeMem(uint8_t *data, unsigned size, 3192315SN/A Addr addr, unsigned flags, uint64_t *res); 3202332SN/A 3217823Ssteve.reinhardt@amd.com /** Splits a request in two if it crosses a dcache block. */ 3222315SN/A void splitRequest(RequestPtr req, RequestPtr &sreqLow, 3232732SN/A RequestPtr &sreqHigh); 3242315SN/A 3252315SN/A /** Initiate a DTB address translation. */ 3262315SN/A void initiateTranslation(RequestPtr req, RequestPtr sreqLow, 3272332SN/A RequestPtr sreqHigh, uint64_t *res, 3282332SN/A BaseTLB::Mode mode); 3292332SN/A 3302332SN/A /** Finish a DTB address translation. */ 3312332SN/A void finishTranslation(WholeTranslationState *state); 3327823Ssteve.reinhardt@amd.com 3332732SN/A /** True if the DTB address translation has started. */ 3342315SN/A bool translationStarted() const { return instFlags[TranslationStarted]; } 3352315SN/A void translationStarted(bool f) { instFlags[TranslationStarted] = f; } 3362315SN/A 3372315SN/A /** True if the DTB address translation has completed. */ 3382315SN/A bool translationCompleted() const { return instFlags[TranslationCompleted]; } 3392315SN/A void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; } 3402315SN/A 3412732SN/A /** True if this address was found to match a previous load and they issued 3422315SN/A * out of order. If that happend, then it's only a problem if an incoming 3432332SN/A * snoop invalidate modifies the line, in which case we need to squash. 3442315SN/A * If nothing modified the line the order doesn't matter. 3452332SN/A */ 3462332SN/A bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; } 3472332SN/A void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; } 3482732SN/A 3492315SN/A /** True if the address hit a external snoop while sitting in the LSQ. 3502732SN/A * If this is true and a older instruction sees it, this instruction must 3512732SN/A * reexecute 3522732SN/A */ 3532732SN/A bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; } 3542732SN/A void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; } 3552732SN/A 3562732SN/A /** 3577823Ssteve.reinhardt@amd.com * Returns true if the DTB address translation is being delayed due to a hw 3582732SN/A * page table walk. 3592732SN/A */ 3602732SN/A bool isTranslationDelayed() const 3612732SN/A { 3622732SN/A return (translationStarted() && !translationCompleted()); 3632732SN/A } 3642732SN/A 3652732SN/A public: 3662732SN/A#ifdef DEBUG 3672732SN/A void dumpSNList(); 3682315SN/A#endif 3692315SN/A 3702315SN/A /** Returns the physical register index of the i'th destination 3712683SN/A * register. 3722332SN/A */ 3732332SN/A PhysRegIndex renamedDestRegIdx(int idx) const 3747823Ssteve.reinhardt@amd.com { 3752732SN/A return _destRegIdx[idx]; 3762315SN/A } 3772315SN/A 3782315SN/A /** Returns the physical register index of the i'th source register. */ 3792315SN/A PhysRegIndex renamedSrcRegIdx(int idx) const 3802315SN/A { 3812315SN/A assert(TheISA::MaxInstSrcRegs > idx); 3822315SN/A return _srcRegIdx[idx]; 3832315SN/A } 3842315SN/A 3852315SN/A /** Returns the flattened register index of the i'th destination 3862315SN/A * register. 3874172Ssaidi@eecs.umich.edu */ 3884172Ssaidi@eecs.umich.edu TheISA::RegIndex flattenedDestRegIdx(int idx) const 3892332SN/A { 3902332SN/A return _flatDestRegIdx[idx]; 3917823Ssteve.reinhardt@amd.com } 3924172Ssaidi@eecs.umich.edu 3934172Ssaidi@eecs.umich.edu /** Returns the physical register index of the previous physical register 3942732SN/A * that remapped to the same logical register index. 3952315SN/A */ 3962315SN/A PhysRegIndex prevDestRegIdx(int idx) const 3972315SN/A { 3982315SN/A return _prevDestRegIdx[idx]; 3992315SN/A } 4002315SN/A 4012315SN/A /** Renames a destination register to a physical register. Also records 4022315SN/A * the previous physical register that the logical register mapped to. 4032354SN/A */ 4042354SN/A void renameDestReg(int idx, 4057823Ssteve.reinhardt@amd.com PhysRegIndex renamed_dest, 4062354SN/A PhysRegIndex previous_rename) 4073126Sktlim@umich.edu { 4082356SN/A _destRegIdx[idx] = renamed_dest; 4092356SN/A _prevDestRegIdx[idx] = previous_rename; 4102356SN/A } 4113126Sktlim@umich.edu 4123126Sktlim@umich.edu /** Renames a source logical register to the physical register which 4132356SN/A * has/will produce that logical register's result. 4142356SN/A * @todo: add in whether or not the source register is ready. 4153126Sktlim@umich.edu */ 4163126Sktlim@umich.edu void renameSrcReg(int idx, PhysRegIndex renamed_src) 4173126Sktlim@umich.edu { 4182356SN/A _srcRegIdx[idx] = renamed_src; 4192354SN/A } 4203126Sktlim@umich.edu 4212315SN/A /** Flattens a destination architectural register index into a logical 4222315SN/A * index. 4232315SN/A */ 4242315SN/A void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 4252732SN/A { 4262732SN/A _flatDestRegIdx[idx] = flattened_dest; 4272732SN/A } 4282732SN/A /** BaseDynInst constructor given a binary instruction. 4292732SN/A * @param staticInst A StaticInstPtr to the underlying instruction. 4302732SN/A * @param pc The PC state for the instruction. 4312732SN/A * @param predPC The predicted next PC state for the instruction. 4322732SN/A * @param seq_num The sequence number of the instruction. 4334172Ssaidi@eecs.umich.edu * @param cpu Pointer to the instruction's CPU. 4342732SN/A */ 4352732SN/A BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop, 4362732SN/A TheISA::PCState pc, TheISA::PCState predPC, 4372732SN/A InstSeqNum seq_num, ImplCPU *cpu); 4382732SN/A 4392732SN/A /** BaseDynInst constructor given a StaticInst pointer. 4402732SN/A * @param _staticInst The StaticInst for this BaseDynInst. 4412732SN/A */ 4422732SN/A BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop); 4432732SN/A 4442732SN/A /** BaseDynInst destructor. */ 4452732SN/A ~BaseDynInst(); 4462732SN/A 4472732SN/A private: 4482732SN/A /** Function to initialize variables in the constructors. */ 4492732SN/A void initVars(); 4502732SN/A 4512732SN/A public: 4522732SN/A /** Dumps out contents of this BaseDynInst. */ 4532732SN/A void dump(); 4542732SN/A 4552315SN/A /** Dumps out contents of this BaseDynInst into given string. */ 4562315SN/A void dump(std::string &outstring); 4572315SN/A 4582315SN/A /** Read this CPU's ID. */ 4592315SN/A int cpuId() const { return cpu->cpuId(); } 4602315SN/A 4612315SN/A /** Read this CPU's Socket ID. */ 4622315SN/A uint32_t socketId() const { return cpu->socketId(); } 4632315SN/A 4642315SN/A /** Read this CPU's data requestor ID */ 4652315SN/A MasterID masterId() const { return cpu->dataMasterId(); } 4662315SN/A 4672315SN/A /** Read this context's system-wide ID **/ 4682315SN/A ContextID contextId() const { return thread->contextId(); } 4692315SN/A 4702315SN/A /** Returns the fault type. */ 4712315SN/A Fault getFault() const { return fault; } 4722315SN/A 4732315SN/A /** Checks whether or not this instruction has had its branch target 4742315SN/A * calculated yet. For now it is not utilized and is hacked to be 4752315SN/A * always false. 4762315SN/A * @todo: Actually use this instruction. 4772315SN/A */ 4782315SN/A bool doneTargCalc() { return false; } 4792315SN/A 4802315SN/A /** Set the predicted target of this current instruction. */ 4812315SN/A void setPredTarg(const TheISA::PCState &_predPC) 482 { 483 predPC = _predPC; 484 } 485 486 const TheISA::PCState &readPredTarg() { return predPC; } 487 488 /** Returns the predicted PC immediately after the branch. */ 489 Addr predInstAddr() { return predPC.instAddr(); } 490 491 /** Returns the predicted PC two instructions after the branch */ 492 Addr predNextInstAddr() { return predPC.nextInstAddr(); } 493 494 /** Returns the predicted micro PC after the branch */ 495 Addr predMicroPC() { return predPC.microPC(); } 496 497 /** Returns whether the instruction was predicted taken or not. */ 498 bool readPredTaken() 499 { 500 return instFlags[PredTaken]; 501 } 502 503 void setPredTaken(bool predicted_taken) 504 { 505 instFlags[PredTaken] = predicted_taken; 506 } 507 508 /** Returns whether the instruction mispredicted. */ 509 bool mispredicted() 510 { 511 TheISA::PCState tempPC = pc; 512 TheISA::advancePC(tempPC, staticInst); 513 return !(tempPC == predPC); 514 } 515 516 // 517 // Instruction types. Forward checks to StaticInst object. 518 // 519 bool isNop() const { return staticInst->isNop(); } 520 bool isMemRef() const { return staticInst->isMemRef(); } 521 bool isLoad() const { return staticInst->isLoad(); } 522 bool isStore() const { return staticInst->isStore(); } 523 bool isStoreConditional() const 524 { return staticInst->isStoreConditional(); } 525 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 526 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 527 bool isInteger() const { return staticInst->isInteger(); } 528 bool isFloating() const { return staticInst->isFloating(); } 529 bool isControl() const { return staticInst->isControl(); } 530 bool isCall() const { return staticInst->isCall(); } 531 bool isReturn() const { return staticInst->isReturn(); } 532 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 533 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 534 bool isCondCtrl() const { return staticInst->isCondCtrl(); } 535 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 536 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 537 bool isThreadSync() const { return staticInst->isThreadSync(); } 538 bool isSerializing() const { return staticInst->isSerializing(); } 539 bool isSerializeBefore() const 540 { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 541 bool isSerializeAfter() const 542 { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 543 bool isSquashAfter() const { return staticInst->isSquashAfter(); } 544 bool isMemBarrier() const { return staticInst->isMemBarrier(); } 545 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 546 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 547 bool isQuiesce() const { return staticInst->isQuiesce(); } 548 bool isIprAccess() const { return staticInst->isIprAccess(); } 549 bool isUnverifiable() const { return staticInst->isUnverifiable(); } 550 bool isSyscall() const { return staticInst->isSyscall(); } 551 bool isMacroop() const { return staticInst->isMacroop(); } 552 bool isMicroop() const { return staticInst->isMicroop(); } 553 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 554 bool isLastMicroop() const { return staticInst->isLastMicroop(); } 555 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 556 bool isMicroBranch() const { return staticInst->isMicroBranch(); } 557 558 /** Temporarily sets this instruction as a serialize before instruction. */ 559 void setSerializeBefore() { status.set(SerializeBefore); } 560 561 /** Clears the serializeBefore part of this instruction. */ 562 void clearSerializeBefore() { status.reset(SerializeBefore); } 563 564 /** Checks if this serializeBefore is only temporarily set. */ 565 bool isTempSerializeBefore() { return status[SerializeBefore]; } 566 567 /** Temporarily sets this instruction as a serialize after instruction. */ 568 void setSerializeAfter() { status.set(SerializeAfter); } 569 570 /** Clears the serializeAfter part of this instruction.*/ 571 void clearSerializeAfter() { status.reset(SerializeAfter); } 572 573 /** Checks if this serializeAfter is only temporarily set. */ 574 bool isTempSerializeAfter() { return status[SerializeAfter]; } 575 576 /** Sets the serialization part of this instruction as handled. */ 577 void setSerializeHandled() { status.set(SerializeHandled); } 578 579 /** Checks if the serialization part of this instruction has been 580 * handled. This does not apply to the temporary serializing 581 * state; it only applies to this instruction's own permanent 582 * serializing state. 583 */ 584 bool isSerializeHandled() { return status[SerializeHandled]; } 585 586 /** Returns the opclass of this instruction. */ 587 OpClass opClass() const { return staticInst->opClass(); } 588 589 /** Returns the branch target address. */ 590 TheISA::PCState branchTarget() const 591 { return staticInst->branchTarget(pc); } 592 593 /** Returns the number of source registers. */ 594 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 595 596 /** Returns the number of destination registers. */ 597 int8_t numDestRegs() const { return staticInst->numDestRegs(); } 598 599 // the following are used to track physical register usage 600 // for machines with separate int & FP reg files 601 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 602 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 603 int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); } 604 605 /** Returns the logical register index of the i'th destination register. */ 606 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 607 608 /** Returns the logical register index of the i'th source register. */ 609 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 610 611 /** Pops a result off the instResult queue */ 612 template <class T> 613 void popResult(T& t) 614 { 615 if (!instResult.empty()) { 616 instResult.front().get(t); 617 instResult.pop(); 618 } 619 } 620 621 /** Read the most recent result stored by this instruction */ 622 template <class T> 623 void readResult(T& t) 624 { 625 instResult.back().get(t); 626 } 627 628 /** Pushes a result onto the instResult queue */ 629 template <class T> 630 void setResult(T t) 631 { 632 if (instFlags[RecordResult]) { 633 Result instRes; 634 instRes.set(t); 635 instResult.push(instRes); 636 } 637 } 638 639 /** Records an integer register being set to a value. */ 640 void setIntRegOperand(const StaticInst *si, int idx, IntReg val) 641 { 642 setResult<uint64_t>(val); 643 } 644 645 /** Records a CC register being set to a value. */ 646 void setCCRegOperand(const StaticInst *si, int idx, CCReg val) 647 { 648 setResult<uint64_t>(val); 649 } 650 651 /** Records an fp register being set to a value. */ 652 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 653 { 654 setResult<double>(val); 655 } 656 657 /** Records an fp register being set to an integer value. */ 658 void setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val) 659 { 660 setResult<uint64_t>(val); 661 } 662 663 /** Records that one of the source registers is ready. */ 664 void markSrcRegReady(); 665 666 /** Marks a specific register as ready. */ 667 void markSrcRegReady(RegIndex src_idx); 668 669 /** Returns if a source register is ready. */ 670 bool isReadySrcRegIdx(int idx) const 671 { 672 return this->_readySrcRegIdx[idx]; 673 } 674 675 /** Sets this instruction as completed. */ 676 void setCompleted() { status.set(Completed); } 677 678 /** Returns whether or not this instruction is completed. */ 679 bool isCompleted() const { return status[Completed]; } 680 681 /** Marks the result as ready. */ 682 void setResultReady() { status.set(ResultReady); } 683 684 /** Returns whether or not the result is ready. */ 685 bool isResultReady() const { return status[ResultReady]; } 686 687 /** Sets this instruction as ready to issue. */ 688 void setCanIssue() { status.set(CanIssue); } 689 690 /** Returns whether or not this instruction is ready to issue. */ 691 bool readyToIssue() const { return status[CanIssue]; } 692 693 /** Clears this instruction being able to issue. */ 694 void clearCanIssue() { status.reset(CanIssue); } 695 696 /** Sets this instruction as issued from the IQ. */ 697 void setIssued() { status.set(Issued); } 698 699 /** Returns whether or not this instruction has issued. */ 700 bool isIssued() const { return status[Issued]; } 701 702 /** Clears this instruction as being issued. */ 703 void clearIssued() { status.reset(Issued); } 704 705 /** Sets this instruction as executed. */ 706 void setExecuted() { status.set(Executed); } 707 708 /** Returns whether or not this instruction has executed. */ 709 bool isExecuted() const { return status[Executed]; } 710 711 /** Sets this instruction as ready to commit. */ 712 void setCanCommit() { status.set(CanCommit); } 713 714 /** Clears this instruction as being ready to commit. */ 715 void clearCanCommit() { status.reset(CanCommit); } 716 717 /** Returns whether or not this instruction is ready to commit. */ 718 bool readyToCommit() const { return status[CanCommit]; } 719 720 void setAtCommit() { status.set(AtCommit); } 721 722 bool isAtCommit() { return status[AtCommit]; } 723 724 /** Sets this instruction as committed. */ 725 void setCommitted() { status.set(Committed); } 726 727 /** Returns whether or not this instruction is committed. */ 728 bool isCommitted() const { return status[Committed]; } 729 730 /** Sets this instruction as squashed. */ 731 void setSquashed() { status.set(Squashed); } 732 733 /** Returns whether or not this instruction is squashed. */ 734 bool isSquashed() const { return status[Squashed]; } 735 736 //Instruction Queue Entry 737 //----------------------- 738 /** Sets this instruction as a entry the IQ. */ 739 void setInIQ() { status.set(IqEntry); } 740 741 /** Sets this instruction as a entry the IQ. */ 742 void clearInIQ() { status.reset(IqEntry); } 743 744 /** Returns whether or not this instruction has issued. */ 745 bool isInIQ() const { return status[IqEntry]; } 746 747 /** Sets this instruction as squashed in the IQ. */ 748 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 749 750 /** Returns whether or not this instruction is squashed in the IQ. */ 751 bool isSquashedInIQ() const { return status[SquashedInIQ]; } 752 753 754 //Load / Store Queue Functions 755 //----------------------- 756 /** Sets this instruction as a entry the LSQ. */ 757 void setInLSQ() { status.set(LsqEntry); } 758 759 /** Sets this instruction as a entry the LSQ. */ 760 void removeInLSQ() { status.reset(LsqEntry); } 761 762 /** Returns whether or not this instruction is in the LSQ. */ 763 bool isInLSQ() const { return status[LsqEntry]; } 764 765 /** Sets this instruction as squashed in the LSQ. */ 766 void setSquashedInLSQ() { status.set(SquashedInLSQ);} 767 768 /** Returns whether or not this instruction is squashed in the LSQ. */ 769 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 770 771 772 //Reorder Buffer Functions 773 //----------------------- 774 /** Sets this instruction as a entry the ROB. */ 775 void setInROB() { status.set(RobEntry); } 776 777 /** Sets this instruction as a entry the ROB. */ 778 void clearInROB() { status.reset(RobEntry); } 779 780 /** Returns whether or not this instruction is in the ROB. */ 781 bool isInROB() const { return status[RobEntry]; } 782 783 /** Sets this instruction as squashed in the ROB. */ 784 void setSquashedInROB() { status.set(SquashedInROB); } 785 786 /** Returns whether or not this instruction is squashed in the ROB. */ 787 bool isSquashedInROB() const { return status[SquashedInROB]; } 788 789 /** Read the PC state of this instruction. */ 790 TheISA::PCState pcState() const { return pc; } 791 792 /** Set the PC state of this instruction. */ 793 void pcState(const TheISA::PCState &val) { pc = val; } 794 795 /** Read the PC of this instruction. */ 796 Addr instAddr() const { return pc.instAddr(); } 797 798 /** Read the PC of the next instruction. */ 799 Addr nextInstAddr() const { return pc.nextInstAddr(); } 800 801 /**Read the micro PC of this instruction. */ 802 Addr microPC() const { return pc.microPC(); } 803 804 bool readPredicate() 805 { 806 return instFlags[Predicate]; 807 } 808 809 void setPredicate(bool val) 810 { 811 instFlags[Predicate] = val; 812 813 if (traceData) { 814 traceData->setPredicate(val); 815 } 816 } 817 818 /** Sets the ASID. */ 819 void setASID(short addr_space_id) { asid = addr_space_id; } 820 821 /** Sets the thread id. */ 822 void setTid(ThreadID tid) { threadNumber = tid; } 823 824 /** Sets the pointer to the thread state. */ 825 void setThreadState(ImplState *state) { thread = state; } 826 827 /** Returns the thread context. */ 828 ThreadContext *tcBase() { return thread->getTC(); } 829 830 public: 831 /** Sets the effective address. */ 832 void setEA(Addr ea) { instEffAddr = ea; instFlags[EACalcDone] = true; } 833 834 /** Returns the effective address. */ 835 Addr getEA() const { return instEffAddr; } 836 837 /** Returns whether or not the eff. addr. calculation has been completed. */ 838 bool doneEACalc() { return instFlags[EACalcDone]; } 839 840 /** Returns whether or not the eff. addr. source registers are ready. */ 841 bool eaSrcsReady(); 842 843 /** Is this instruction's memory access strictly ordered? */ 844 bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; } 845 846 /** Has this instruction generated a memory request. */ 847 bool hasRequest() { return instFlags[ReqMade]; } 848 849 /** Returns iterator to this instruction in the list of all insts. */ 850 ListIt &getInstListIt() { return instListIt; } 851 852 /** Sets iterator for this instruction in the list of all insts. */ 853 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 854 855 public: 856 /** Returns the number of consecutive store conditional failures. */ 857 unsigned int readStCondFailures() const 858 { return thread->storeCondFailures; } 859 860 /** Sets the number of consecutive store conditional failures. */ 861 void setStCondFailures(unsigned int sc_failures) 862 { thread->storeCondFailures = sc_failures; } 863 864 public: 865 // monitor/mwait funtions 866 void armMonitor(Addr address) { cpu->armMonitor(threadNumber, address); } 867 bool mwait(PacketPtr pkt) { return cpu->mwait(threadNumber, pkt); } 868 void mwaitAtomic(ThreadContext *tc) 869 { return cpu->mwaitAtomic(threadNumber, tc, cpu->dtb); } 870 AddressMonitor *getAddrMonitor() 871 { return cpu->getCpuAddrMonitor(threadNumber); } 872}; 873 874template<class Impl> 875Fault 876BaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size, unsigned flags) 877{ 878 instFlags[ReqMade] = true; 879 Request *req = NULL; 880 Request *sreqLow = NULL; 881 Request *sreqHigh = NULL; 882 883 if (instFlags[ReqMade] && translationStarted()) { 884 req = savedReq; 885 sreqLow = savedSreqLow; 886 sreqHigh = savedSreqHigh; 887 } else { 888 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(), 889 thread->contextId(), threadNumber); 890 891 req->taskId(cpu->taskId()); 892 893 // Only split the request if the ISA supports unaligned accesses. 894 if (TheISA::HasUnalignedMemAcc) { 895 splitRequest(req, sreqLow, sreqHigh); 896 } 897 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read); 898 } 899 900 if (translationCompleted()) { 901 if (fault == NoFault) { 902 effAddr = req->getVaddr(); 903 effSize = size; 904 instFlags[EffAddrValid] = true; 905 906 if (cpu->checker) { 907 if (reqToVerify != NULL) { 908 delete reqToVerify; 909 } 910 reqToVerify = new Request(*req); 911 } 912 fault = cpu->read(req, sreqLow, sreqHigh, lqIdx); 913 } else { 914 // Commit will have to clean up whatever happened. Set this 915 // instruction as executed. 916 this->setExecuted(); 917 } 918 } 919 920 if (traceData) 921 traceData->setMem(addr, size, flags); 922 923 return fault; 924} 925 926template<class Impl> 927Fault 928BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, 929 Addr addr, unsigned flags, uint64_t *res) 930{ 931 if (traceData) 932 traceData->setMem(addr, size, flags); 933 934 instFlags[ReqMade] = true; 935 Request *req = NULL; 936 Request *sreqLow = NULL; 937 Request *sreqHigh = NULL; 938 939 if (instFlags[ReqMade] && translationStarted()) { 940 req = savedReq; 941 sreqLow = savedSreqLow; 942 sreqHigh = savedSreqHigh; 943 } else { 944 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(), 945 thread->contextId(), threadNumber); 946 947 req->taskId(cpu->taskId()); 948 949 // Only split the request if the ISA supports unaligned accesses. 950 if (TheISA::HasUnalignedMemAcc) { 951 splitRequest(req, sreqLow, sreqHigh); 952 } 953 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write); 954 } 955 956 if (fault == NoFault && translationCompleted()) { 957 effAddr = req->getVaddr(); 958 effSize = size; 959 instFlags[EffAddrValid] = true; 960 961 if (cpu->checker) { 962 if (reqToVerify != NULL) { 963 delete reqToVerify; 964 } 965 reqToVerify = new Request(*req); 966 } 967 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx); 968 } 969 970 return fault; 971} 972 973template<class Impl> 974inline void 975BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow, 976 RequestPtr &sreqHigh) 977{ 978 // Check to see if the request crosses the next level block boundary. 979 unsigned block_size = cpu->cacheLineSize(); 980 Addr addr = req->getVaddr(); 981 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size); 982 assert(split_addr <= addr || split_addr - addr < block_size); 983 984 // Spans two blocks. 985 if (split_addr > addr) { 986 req->splitOnVaddr(split_addr, sreqLow, sreqHigh); 987 } 988} 989 990template<class Impl> 991inline void 992BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow, 993 RequestPtr sreqHigh, uint64_t *res, 994 BaseTLB::Mode mode) 995{ 996 translationStarted(true); 997 998 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) { 999 WholeTranslationState *state = 1000 new WholeTranslationState(req, NULL, res, mode); 1001 1002 // One translation if the request isn't split. 1003 DataTranslation<BaseDynInstPtr> *trans = 1004 new DataTranslation<BaseDynInstPtr>(this, state); 1005 1006 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode); 1007 1008 if (!translationCompleted()) { 1009 // The translation isn't yet complete, so we can't possibly have a 1010 // fault. Overwrite any existing fault we might have from a previous 1011 // execution of this instruction (e.g. an uncachable load that 1012 // couldn't execute because it wasn't at the head of the ROB). 1013 fault = NoFault; 1014 1015 // Save memory requests. 1016 savedReq = state->mainReq; 1017 savedSreqLow = state->sreqLow; 1018 savedSreqHigh = state->sreqHigh; 1019 } 1020 } else { 1021 WholeTranslationState *state = 1022 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode); 1023 1024 // Two translations when the request is split. 1025 DataTranslation<BaseDynInstPtr> *stransLow = 1026 new DataTranslation<BaseDynInstPtr>(this, state, 0); 1027 DataTranslation<BaseDynInstPtr> *stransHigh = 1028 new DataTranslation<BaseDynInstPtr>(this, state, 1); 1029 1030 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode); 1031 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode); 1032 1033 if (!translationCompleted()) { 1034 // The translation isn't yet complete, so we can't possibly have a 1035 // fault. Overwrite any existing fault we might have from a previous 1036 // execution of this instruction (e.g. an uncachable load that 1037 // couldn't execute because it wasn't at the head of the ROB). 1038 fault = NoFault; 1039 1040 // Save memory requests. 1041 savedReq = state->mainReq; 1042 savedSreqLow = state->sreqLow; 1043 savedSreqHigh = state->sreqHigh; 1044 } 1045 } 1046} 1047 1048template<class Impl> 1049inline void 1050BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state) 1051{ 1052 fault = state->getFault(); 1053 1054 instFlags[IsStrictlyOrdered] = state->isStrictlyOrdered(); 1055 1056 if (fault == NoFault) { 1057 // save Paddr for a single req 1058 physEffAddrLow = state->getPaddr(); 1059 1060 // case for the request that has been split 1061 if (state->isSplit) { 1062 physEffAddrLow = state->sreqLow->getPaddr(); 1063 physEffAddrHigh = state->sreqHigh->getPaddr(); 1064 } 1065 1066 memReqFlags = state->getFlags(); 1067 1068 if (state->mainReq->isCondSwap()) { 1069 assert(state->res); 1070 state->mainReq->setExtraData(*state->res); 1071 } 1072 1073 } else { 1074 state->deleteReqs(); 1075 } 1076 delete state; 1077 1078 translationCompleted(true); 1079} 1080 1081#endif // __CPU_BASE_DYN_INST_HH__ 1082