base_dyn_inst.hh revision 10934:5af8f40d8f2c
1/* 2 * Copyright (c) 2011,2013 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2004-2006 The Regents of The University of Michigan 16 * Copyright (c) 2009 The University of Edinburgh 17 * All rights reserved. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions are 21 * met: redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer; 23 * redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution; 26 * neither the name of the copyright holders nor the names of its 27 * contributors may be used to endorse or promote products derived from 28 * this software without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 * 42 * Authors: Kevin Lim 43 * Timothy M. Jones 44 */ 45 46#ifndef __CPU_BASE_DYN_INST_HH__ 47#define __CPU_BASE_DYN_INST_HH__ 48 49#include <array> 50#include <bitset> 51#include <list> 52#include <string> 53#include <queue> 54 55#include "arch/generic/tlb.hh" 56#include "arch/utility.hh" 57#include "base/trace.hh" 58#include "config/the_isa.hh" 59#include "cpu/checker/cpu.hh" 60#include "cpu/o3/comm.hh" 61#include "cpu/exec_context.hh" 62#include "cpu/exetrace.hh" 63#include "cpu/inst_seq.hh" 64#include "cpu/op_class.hh" 65#include "cpu/static_inst.hh" 66#include "cpu/translation.hh" 67#include "mem/packet.hh" 68#include "sim/byteswap.hh" 69#include "sim/system.hh" 70 71/** 72 * @file 73 * Defines a dynamic instruction context. 74 */ 75 76template <class Impl> 77class BaseDynInst : public ExecContext, public RefCounted 78{ 79 public: 80 // Typedef for the CPU. 81 typedef typename Impl::CPUType ImplCPU; 82 typedef typename ImplCPU::ImplState ImplState; 83 84 // Logical register index type. 85 typedef TheISA::RegIndex RegIndex; 86 87 // The DynInstPtr type. 88 typedef typename Impl::DynInstPtr DynInstPtr; 89 typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr; 90 91 // The list of instructions iterator type. 92 typedef typename std::list<DynInstPtr>::iterator ListIt; 93 94 enum { 95 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 96 MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs 97 }; 98 99 union Result { 100 uint64_t integer; 101 double dbl; 102 103 // I am assuming that vector register type is different from the two 104 // types used above. Else it seems useless to have a separate typedef 105 // for vector registers. 106 VectorReg vector; 107 108 void set(uint64_t i) { integer = i; } 109 void set(double d) { dbl = d; } 110 void set(const VectorReg &v) { vector = v; } 111 112 void get(uint64_t& i) { i = integer; } 113 void get(double& d) { d = dbl; } 114 void get(VectorReg& v) { v = vector; } 115 }; 116 117 protected: 118 enum Status { 119 IqEntry, /// Instruction is in the IQ 120 RobEntry, /// Instruction is in the ROB 121 LsqEntry, /// Instruction is in the LSQ 122 Completed, /// Instruction has completed 123 ResultReady, /// Instruction has its result 124 CanIssue, /// Instruction can issue and execute 125 Issued, /// Instruction has issued 126 Executed, /// Instruction has executed 127 CanCommit, /// Instruction can commit 128 AtCommit, /// Instruction has reached commit 129 Committed, /// Instruction has committed 130 Squashed, /// Instruction is squashed 131 SquashedInIQ, /// Instruction is squashed in the IQ 132 SquashedInLSQ, /// Instruction is squashed in the LSQ 133 SquashedInROB, /// Instruction is squashed in the ROB 134 RecoverInst, /// Is a recover instruction 135 BlockingInst, /// Is a blocking instruction 136 ThreadsyncWait, /// Is a thread synchronization instruction 137 SerializeBefore, /// Needs to serialize on 138 /// instructions ahead of it 139 SerializeAfter, /// Needs to serialize instructions behind it 140 SerializeHandled, /// Serialization has been handled 141 NumStatus 142 }; 143 144 enum Flags { 145 TranslationStarted, 146 TranslationCompleted, 147 PossibleLoadViolation, 148 HitExternalSnoop, 149 EffAddrValid, 150 RecordResult, 151 Predicate, 152 PredTaken, 153 /** Whether or not the effective address calculation is completed. 154 * @todo: Consider if this is necessary or not. 155 */ 156 EACalcDone, 157 IsStrictlyOrdered, 158 ReqMade, 159 MemOpDone, 160 MaxFlags 161 }; 162 163 public: 164 /** The sequence number of the instruction. */ 165 InstSeqNum seqNum; 166 167 /** The StaticInst used by this BaseDynInst. */ 168 const StaticInstPtr staticInst; 169 170 /** Pointer to the Impl's CPU object. */ 171 ImplCPU *cpu; 172 173 BaseCPU *getCpuPtr() { return cpu; } 174 175 /** Pointer to the thread state. */ 176 ImplState *thread; 177 178 /** The kind of fault this instruction has generated. */ 179 Fault fault; 180 181 /** InstRecord that tracks this instructions. */ 182 Trace::InstRecord *traceData; 183 184 protected: 185 /** The result of the instruction; assumes an instruction can have many 186 * destination registers. 187 */ 188 std::queue<Result> instResult; 189 190 /** PC state for this instruction. */ 191 TheISA::PCState pc; 192 193 /* An amalgamation of a lot of boolean values into one */ 194 std::bitset<MaxFlags> instFlags; 195 196 /** The status of this BaseDynInst. Several bits can be set. */ 197 std::bitset<NumStatus> status; 198 199 /** Whether or not the source register is ready. 200 * @todo: Not sure this should be here vs the derived class. 201 */ 202 std::bitset<MaxInstSrcRegs> _readySrcRegIdx; 203 204 public: 205 /** The thread this instruction is from. */ 206 ThreadID threadNumber; 207 208 /** Iterator pointing to this BaseDynInst in the list of all insts. */ 209 ListIt instListIt; 210 211 ////////////////////// Branch Data /////////////// 212 /** Predicted PC state after this instruction. */ 213 TheISA::PCState predPC; 214 215 /** The Macroop if one exists */ 216 const StaticInstPtr macroop; 217 218 /** How many source registers are ready. */ 219 uint8_t readyRegs; 220 221 public: 222 /////////////////////// Load Store Data ////////////////////// 223 /** The effective virtual address (lds & stores only). */ 224 Addr effAddr; 225 226 /** The effective physical address. */ 227 Addr physEffAddr; 228 229 /** The memory request flags (from translation). */ 230 unsigned memReqFlags; 231 232 /** data address space ID, for loads & stores. */ 233 short asid; 234 235 /** The size of the request */ 236 uint8_t effSize; 237 238 /** Pointer to the data for the memory access. */ 239 uint8_t *memData; 240 241 /** Load queue index. */ 242 int16_t lqIdx; 243 244 /** Store queue index. */ 245 int16_t sqIdx; 246 247 248 /////////////////////// TLB Miss ////////////////////// 249 /** 250 * Saved memory requests (needed when the DTB address translation is 251 * delayed due to a hw page table walk). 252 */ 253 RequestPtr savedReq; 254 RequestPtr savedSreqLow; 255 RequestPtr savedSreqHigh; 256 257 /////////////////////// Checker ////////////////////// 258 // Need a copy of main request pointer to verify on writes. 259 RequestPtr reqToVerify; 260 261 private: 262 /** Instruction effective address. 263 * @todo: Consider if this is necessary or not. 264 */ 265 Addr instEffAddr; 266 267 protected: 268 /** Flattened register index of the destination registers of this 269 * instruction. 270 */ 271 std::array<TheISA::RegIndex, TheISA::MaxInstDestRegs> _flatDestRegIdx; 272 273 /** Physical register index of the destination registers of this 274 * instruction. 275 */ 276 std::array<PhysRegIndex, TheISA::MaxInstDestRegs> _destRegIdx; 277 278 /** Physical register index of the source registers of this 279 * instruction. 280 */ 281 std::array<PhysRegIndex, TheISA::MaxInstSrcRegs> _srcRegIdx; 282 283 /** Physical register index of the previous producers of the 284 * architected destinations. 285 */ 286 std::array<PhysRegIndex, TheISA::MaxInstDestRegs> _prevDestRegIdx; 287 288 289 public: 290 /** Records changes to result? */ 291 void recordResult(bool f) { instFlags[RecordResult] = f; } 292 293 /** Is the effective virtual address valid. */ 294 bool effAddrValid() const { return instFlags[EffAddrValid]; } 295 296 /** Whether or not the memory operation is done. */ 297 bool memOpDone() const { return instFlags[MemOpDone]; } 298 void memOpDone(bool f) { instFlags[MemOpDone] = f; } 299 300 301 //////////////////////////////////////////// 302 // 303 // INSTRUCTION EXECUTION 304 // 305 //////////////////////////////////////////// 306 307 void demapPage(Addr vaddr, uint64_t asn) 308 { 309 cpu->demapPage(vaddr, asn); 310 } 311 void demapInstPage(Addr vaddr, uint64_t asn) 312 { 313 cpu->demapPage(vaddr, asn); 314 } 315 void demapDataPage(Addr vaddr, uint64_t asn) 316 { 317 cpu->demapPage(vaddr, asn); 318 } 319 320 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 321 322 Fault writeMem(uint8_t *data, unsigned size, 323 Addr addr, unsigned flags, uint64_t *res); 324 325 /** Splits a request in two if it crosses a dcache block. */ 326 void splitRequest(RequestPtr req, RequestPtr &sreqLow, 327 RequestPtr &sreqHigh); 328 329 /** Initiate a DTB address translation. */ 330 void initiateTranslation(RequestPtr req, RequestPtr sreqLow, 331 RequestPtr sreqHigh, uint64_t *res, 332 BaseTLB::Mode mode); 333 334 /** Finish a DTB address translation. */ 335 void finishTranslation(WholeTranslationState *state); 336 337 /** True if the DTB address translation has started. */ 338 bool translationStarted() const { return instFlags[TranslationStarted]; } 339 void translationStarted(bool f) { instFlags[TranslationStarted] = f; } 340 341 /** True if the DTB address translation has completed. */ 342 bool translationCompleted() const { return instFlags[TranslationCompleted]; } 343 void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; } 344 345 /** True if this address was found to match a previous load and they issued 346 * out of order. If that happend, then it's only a problem if an incoming 347 * snoop invalidate modifies the line, in which case we need to squash. 348 * If nothing modified the line the order doesn't matter. 349 */ 350 bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; } 351 void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; } 352 353 /** True if the address hit a external snoop while sitting in the LSQ. 354 * If this is true and a older instruction sees it, this instruction must 355 * reexecute 356 */ 357 bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; } 358 void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; } 359 360 /** 361 * Returns true if the DTB address translation is being delayed due to a hw 362 * page table walk. 363 */ 364 bool isTranslationDelayed() const 365 { 366 return (translationStarted() && !translationCompleted()); 367 } 368 369 public: 370#ifdef DEBUG 371 void dumpSNList(); 372#endif 373 374 /** Returns the physical register index of the i'th destination 375 * register. 376 */ 377 PhysRegIndex renamedDestRegIdx(int idx) const 378 { 379 return _destRegIdx[idx]; 380 } 381 382 /** Returns the physical register index of the i'th source register. */ 383 PhysRegIndex renamedSrcRegIdx(int idx) const 384 { 385 assert(TheISA::MaxInstSrcRegs > idx); 386 return _srcRegIdx[idx]; 387 } 388 389 /** Returns the flattened register index of the i'th destination 390 * register. 391 */ 392 TheISA::RegIndex flattenedDestRegIdx(int idx) const 393 { 394 return _flatDestRegIdx[idx]; 395 } 396 397 /** Returns the physical register index of the previous physical register 398 * that remapped to the same logical register index. 399 */ 400 PhysRegIndex prevDestRegIdx(int idx) const 401 { 402 return _prevDestRegIdx[idx]; 403 } 404 405 /** Renames a destination register to a physical register. Also records 406 * the previous physical register that the logical register mapped to. 407 */ 408 void renameDestReg(int idx, 409 PhysRegIndex renamed_dest, 410 PhysRegIndex previous_rename) 411 { 412 _destRegIdx[idx] = renamed_dest; 413 _prevDestRegIdx[idx] = previous_rename; 414 } 415 416 /** Renames a source logical register to the physical register which 417 * has/will produce that logical register's result. 418 * @todo: add in whether or not the source register is ready. 419 */ 420 void renameSrcReg(int idx, PhysRegIndex renamed_src) 421 { 422 _srcRegIdx[idx] = renamed_src; 423 } 424 425 /** Flattens a destination architectural register index into a logical 426 * index. 427 */ 428 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 429 { 430 _flatDestRegIdx[idx] = flattened_dest; 431 } 432 /** BaseDynInst constructor given a binary instruction. 433 * @param staticInst A StaticInstPtr to the underlying instruction. 434 * @param pc The PC state for the instruction. 435 * @param predPC The predicted next PC state for the instruction. 436 * @param seq_num The sequence number of the instruction. 437 * @param cpu Pointer to the instruction's CPU. 438 */ 439 BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop, 440 TheISA::PCState pc, TheISA::PCState predPC, 441 InstSeqNum seq_num, ImplCPU *cpu); 442 443 /** BaseDynInst constructor given a StaticInst pointer. 444 * @param _staticInst The StaticInst for this BaseDynInst. 445 */ 446 BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop); 447 448 /** BaseDynInst destructor. */ 449 ~BaseDynInst(); 450 451 private: 452 /** Function to initialize variables in the constructors. */ 453 void initVars(); 454 455 public: 456 /** Dumps out contents of this BaseDynInst. */ 457 void dump(); 458 459 /** Dumps out contents of this BaseDynInst into given string. */ 460 void dump(std::string &outstring); 461 462 /** Read this CPU's ID. */ 463 int cpuId() const { return cpu->cpuId(); } 464 465 /** Read this CPU's Socket ID. */ 466 uint32_t socketId() const { return cpu->socketId(); } 467 468 /** Read this CPU's data requestor ID */ 469 MasterID masterId() const { return cpu->dataMasterId(); } 470 471 /** Read this context's system-wide ID **/ 472 int contextId() const { return thread->contextId(); } 473 474 /** Returns the fault type. */ 475 Fault getFault() const { return fault; } 476 477 /** Checks whether or not this instruction has had its branch target 478 * calculated yet. For now it is not utilized and is hacked to be 479 * always false. 480 * @todo: Actually use this instruction. 481 */ 482 bool doneTargCalc() { return false; } 483 484 /** Set the predicted target of this current instruction. */ 485 void setPredTarg(const TheISA::PCState &_predPC) 486 { 487 predPC = _predPC; 488 } 489 490 const TheISA::PCState &readPredTarg() { return predPC; } 491 492 /** Returns the predicted PC immediately after the branch. */ 493 Addr predInstAddr() { return predPC.instAddr(); } 494 495 /** Returns the predicted PC two instructions after the branch */ 496 Addr predNextInstAddr() { return predPC.nextInstAddr(); } 497 498 /** Returns the predicted micro PC after the branch */ 499 Addr predMicroPC() { return predPC.microPC(); } 500 501 /** Returns whether the instruction was predicted taken or not. */ 502 bool readPredTaken() 503 { 504 return instFlags[PredTaken]; 505 } 506 507 void setPredTaken(bool predicted_taken) 508 { 509 instFlags[PredTaken] = predicted_taken; 510 } 511 512 /** Returns whether the instruction mispredicted. */ 513 bool mispredicted() 514 { 515 TheISA::PCState tempPC = pc; 516 TheISA::advancePC(tempPC, staticInst); 517 return !(tempPC == predPC); 518 } 519 520 // 521 // Instruction types. Forward checks to StaticInst object. 522 // 523 bool isNop() const { return staticInst->isNop(); } 524 bool isMemRef() const { return staticInst->isMemRef(); } 525 bool isLoad() const { return staticInst->isLoad(); } 526 bool isStore() const { return staticInst->isStore(); } 527 bool isStoreConditional() const 528 { return staticInst->isStoreConditional(); } 529 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 530 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 531 bool isInteger() const { return staticInst->isInteger(); } 532 bool isFloating() const { return staticInst->isFloating(); } 533 bool isVector() const { return staticInst->isVector(); } 534 bool isCC() const { return staticInst->isCC(); } 535 536 bool isControl() const { return staticInst->isControl(); } 537 bool isCall() const { return staticInst->isCall(); } 538 bool isReturn() const { return staticInst->isReturn(); } 539 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 540 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 541 bool isCondCtrl() const { return staticInst->isCondCtrl(); } 542 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 543 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 544 bool isThreadSync() const { return staticInst->isThreadSync(); } 545 bool isSerializing() const { return staticInst->isSerializing(); } 546 bool isSerializeBefore() const 547 { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 548 bool isSerializeAfter() const 549 { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 550 bool isSquashAfter() const { return staticInst->isSquashAfter(); } 551 bool isMemBarrier() const { return staticInst->isMemBarrier(); } 552 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 553 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 554 bool isQuiesce() const { return staticInst->isQuiesce(); } 555 bool isIprAccess() const { return staticInst->isIprAccess(); } 556 bool isUnverifiable() const { return staticInst->isUnverifiable(); } 557 bool isSyscall() const { return staticInst->isSyscall(); } 558 bool isMacroop() const { return staticInst->isMacroop(); } 559 bool isMicroop() const { return staticInst->isMicroop(); } 560 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 561 bool isLastMicroop() const { return staticInst->isLastMicroop(); } 562 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 563 bool isMicroBranch() const { return staticInst->isMicroBranch(); } 564 565 void printFlags(std::ostream &outs, const std::string &separator) const 566 { staticInst->printFlags(outs, separator); } 567 568 std::string getName() const { return staticInst->getName(); } 569 570 /** Temporarily sets this instruction as a serialize before instruction. */ 571 void setSerializeBefore() { status.set(SerializeBefore); } 572 573 /** Clears the serializeBefore part of this instruction. */ 574 void clearSerializeBefore() { status.reset(SerializeBefore); } 575 576 /** Checks if this serializeBefore is only temporarily set. */ 577 bool isTempSerializeBefore() { return status[SerializeBefore]; } 578 579 /** Temporarily sets this instruction as a serialize after instruction. */ 580 void setSerializeAfter() { status.set(SerializeAfter); } 581 582 /** Clears the serializeAfter part of this instruction.*/ 583 void clearSerializeAfter() { status.reset(SerializeAfter); } 584 585 /** Checks if this serializeAfter is only temporarily set. */ 586 bool isTempSerializeAfter() { return status[SerializeAfter]; } 587 588 /** Sets the serialization part of this instruction as handled. */ 589 void setSerializeHandled() { status.set(SerializeHandled); } 590 591 /** Checks if the serialization part of this instruction has been 592 * handled. This does not apply to the temporary serializing 593 * state; it only applies to this instruction's own permanent 594 * serializing state. 595 */ 596 bool isSerializeHandled() { return status[SerializeHandled]; } 597 598 /** Returns the opclass of this instruction. */ 599 OpClass opClass() const { return staticInst->opClass(); } 600 601 /** Returns the branch target address. */ 602 TheISA::PCState branchTarget() const 603 { return staticInst->branchTarget(pc); } 604 605 /** Returns the number of source registers. */ 606 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 607 608 /** Returns the number of destination registers. */ 609 int8_t numDestRegs() const { return staticInst->numDestRegs(); } 610 611 // the following are used to track physical register usage 612 // for machines with separate int & FP reg files 613 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 614 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 615 int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); } 616 int8_t numVectorDestRegs() const 617 { return staticInst->numVectorDestRegs(); } 618 619 /** Returns the logical register index of the i'th destination register. */ 620 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 621 622 /** Returns the logical register index of the i'th source register. */ 623 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 624 625 /** Pops a result off the instResult queue */ 626 template <class T> 627 void popResult(T& t) 628 { 629 if (!instResult.empty()) { 630 instResult.front().get(t); 631 instResult.pop(); 632 } 633 } 634 635 /** Read the most recent result stored by this instruction */ 636 template <class T> 637 void readResult(T& t) 638 { 639 instResult.back().get(t); 640 } 641 642 /** Pushes a result onto the instResult queue */ 643 template <class T> 644 void setResult(T t) 645 { 646 if (instFlags[RecordResult]) { 647 Result instRes; 648 instRes.set(t); 649 instResult.push(instRes); 650 } 651 } 652 653 /** Records an integer register being set to a value. */ 654 void setIntRegOperand(const StaticInst *si, int idx, IntReg val) 655 { 656 setResult<uint64_t>(val); 657 } 658 659 /** Records a CC register being set to a value. */ 660 void setCCRegOperand(const StaticInst *si, int idx, CCReg val) 661 { 662 setResult<uint64_t>(val); 663 } 664 665 /** Records an fp register being set to a value. */ 666 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 667 { 668 setResult<double>(val); 669 } 670 671 /** Records an fp register being set to an integer value. */ 672 void setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val) 673 { 674 setResult<uint64_t>(val); 675 } 676 677 /** Records a vector register being set to a value. */ 678 void setVectorRegOperand(const StaticInst *si, int idx, 679 const VectorReg &val) 680 { 681 setResult<const VectorReg &>(val); 682 } 683 684 /** Records that one of the source registers is ready. */ 685 void markSrcRegReady(); 686 687 /** Marks a specific register as ready. */ 688 void markSrcRegReady(RegIndex src_idx); 689 690 /** Returns if a source register is ready. */ 691 bool isReadySrcRegIdx(int idx) const 692 { 693 return this->_readySrcRegIdx[idx]; 694 } 695 696 /** Sets this instruction as completed. */ 697 void setCompleted() { status.set(Completed); } 698 699 /** Returns whether or not this instruction is completed. */ 700 bool isCompleted() const { return status[Completed]; } 701 702 /** Marks the result as ready. */ 703 void setResultReady() { status.set(ResultReady); } 704 705 /** Returns whether or not the result is ready. */ 706 bool isResultReady() const { return status[ResultReady]; } 707 708 /** Sets this instruction as ready to issue. */ 709 void setCanIssue() { status.set(CanIssue); } 710 711 /** Returns whether or not this instruction is ready to issue. */ 712 bool readyToIssue() const { return status[CanIssue]; } 713 714 /** Clears this instruction being able to issue. */ 715 void clearCanIssue() { status.reset(CanIssue); } 716 717 /** Sets this instruction as issued from the IQ. */ 718 void setIssued() { status.set(Issued); } 719 720 /** Returns whether or not this instruction has issued. */ 721 bool isIssued() const { return status[Issued]; } 722 723 /** Clears this instruction as being issued. */ 724 void clearIssued() { status.reset(Issued); } 725 726 /** Sets this instruction as executed. */ 727 void setExecuted() { status.set(Executed); } 728 729 /** Returns whether or not this instruction has executed. */ 730 bool isExecuted() const { return status[Executed]; } 731 732 /** Sets this instruction as ready to commit. */ 733 void setCanCommit() { status.set(CanCommit); } 734 735 /** Clears this instruction as being ready to commit. */ 736 void clearCanCommit() { status.reset(CanCommit); } 737 738 /** Returns whether or not this instruction is ready to commit. */ 739 bool readyToCommit() const { return status[CanCommit]; } 740 741 void setAtCommit() { status.set(AtCommit); } 742 743 bool isAtCommit() { return status[AtCommit]; } 744 745 /** Sets this instruction as committed. */ 746 void setCommitted() { status.set(Committed); } 747 748 /** Returns whether or not this instruction is committed. */ 749 bool isCommitted() const { return status[Committed]; } 750 751 /** Sets this instruction as squashed. */ 752 void setSquashed() { status.set(Squashed); } 753 754 /** Returns whether or not this instruction is squashed. */ 755 bool isSquashed() const { return status[Squashed]; } 756 757 //Instruction Queue Entry 758 //----------------------- 759 /** Sets this instruction as a entry the IQ. */ 760 void setInIQ() { status.set(IqEntry); } 761 762 /** Sets this instruction as a entry the IQ. */ 763 void clearInIQ() { status.reset(IqEntry); } 764 765 /** Returns whether or not this instruction has issued. */ 766 bool isInIQ() const { return status[IqEntry]; } 767 768 /** Sets this instruction as squashed in the IQ. */ 769 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 770 771 /** Returns whether or not this instruction is squashed in the IQ. */ 772 bool isSquashedInIQ() const { return status[SquashedInIQ]; } 773 774 775 //Load / Store Queue Functions 776 //----------------------- 777 /** Sets this instruction as a entry the LSQ. */ 778 void setInLSQ() { status.set(LsqEntry); } 779 780 /** Sets this instruction as a entry the LSQ. */ 781 void removeInLSQ() { status.reset(LsqEntry); } 782 783 /** Returns whether or not this instruction is in the LSQ. */ 784 bool isInLSQ() const { return status[LsqEntry]; } 785 786 /** Sets this instruction as squashed in the LSQ. */ 787 void setSquashedInLSQ() { status.set(SquashedInLSQ);} 788 789 /** Returns whether or not this instruction is squashed in the LSQ. */ 790 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 791 792 793 //Reorder Buffer Functions 794 //----------------------- 795 /** Sets this instruction as a entry the ROB. */ 796 void setInROB() { status.set(RobEntry); } 797 798 /** Sets this instruction as a entry the ROB. */ 799 void clearInROB() { status.reset(RobEntry); } 800 801 /** Returns whether or not this instruction is in the ROB. */ 802 bool isInROB() const { return status[RobEntry]; } 803 804 /** Sets this instruction as squashed in the ROB. */ 805 void setSquashedInROB() { status.set(SquashedInROB); } 806 807 /** Returns whether or not this instruction is squashed in the ROB. */ 808 bool isSquashedInROB() const { return status[SquashedInROB]; } 809 810 /** Read the PC state of this instruction. */ 811 TheISA::PCState pcState() const { return pc; } 812 813 /** Set the PC state of this instruction. */ 814 void pcState(const TheISA::PCState &val) { pc = val; } 815 816 /** Read the PC of this instruction. */ 817 const Addr instAddr() const { return pc.instAddr(); } 818 819 /** Read the PC of the next instruction. */ 820 const Addr nextInstAddr() const { return pc.nextInstAddr(); } 821 822 /**Read the micro PC of this instruction. */ 823 const Addr microPC() const { return pc.microPC(); } 824 825 bool readPredicate() 826 { 827 return instFlags[Predicate]; 828 } 829 830 void setPredicate(bool val) 831 { 832 instFlags[Predicate] = val; 833 834 if (traceData) { 835 traceData->setPredicate(val); 836 } 837 } 838 839 /** Sets the ASID. */ 840 void setASID(short addr_space_id) { asid = addr_space_id; } 841 842 /** Sets the thread id. */ 843 void setTid(ThreadID tid) { threadNumber = tid; } 844 845 /** Sets the pointer to the thread state. */ 846 void setThreadState(ImplState *state) { thread = state; } 847 848 /** Returns the thread context. */ 849 ThreadContext *tcBase() { return thread->getTC(); } 850 851 public: 852 /** Sets the effective address. */ 853 void setEA(Addr ea) { instEffAddr = ea; instFlags[EACalcDone] = true; } 854 855 /** Returns the effective address. */ 856 Addr getEA() const { return instEffAddr; } 857 858 /** Returns whether or not the eff. addr. calculation has been completed. */ 859 bool doneEACalc() { return instFlags[EACalcDone]; } 860 861 /** Returns whether or not the eff. addr. source registers are ready. */ 862 bool eaSrcsReady(); 863 864 /** Is this instruction's memory access strictly ordered? */ 865 bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; } 866 867 /** Has this instruction generated a memory request. */ 868 bool hasRequest() { return instFlags[ReqMade]; } 869 870 /** Returns iterator to this instruction in the list of all insts. */ 871 ListIt &getInstListIt() { return instListIt; } 872 873 /** Sets iterator for this instruction in the list of all insts. */ 874 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 875 876 public: 877 /** Returns the number of consecutive store conditional failures. */ 878 unsigned int readStCondFailures() const 879 { return thread->storeCondFailures; } 880 881 /** Sets the number of consecutive store conditional failures. */ 882 void setStCondFailures(unsigned int sc_failures) 883 { thread->storeCondFailures = sc_failures; } 884 885 public: 886 // monitor/mwait funtions 887 void armMonitor(Addr address) { cpu->armMonitor(address); } 888 bool mwait(PacketPtr pkt) { return cpu->mwait(pkt); } 889 void mwaitAtomic(ThreadContext *tc) 890 { return cpu->mwaitAtomic(tc, cpu->dtb); } 891 AddressMonitor *getAddrMonitor() { return cpu->getCpuAddrMonitor(); } 892}; 893 894template<class Impl> 895Fault 896BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data, 897 unsigned size, unsigned flags) 898{ 899 instFlags[ReqMade] = true; 900 Request *req = NULL; 901 Request *sreqLow = NULL; 902 Request *sreqHigh = NULL; 903 904 if (instFlags[ReqMade] && translationStarted()) { 905 req = savedReq; 906 sreqLow = savedSreqLow; 907 sreqHigh = savedSreqHigh; 908 } else { 909 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(), 910 thread->contextId(), threadNumber); 911 912 req->taskId(cpu->taskId()); 913 914 // Only split the request if the ISA supports unaligned accesses. 915 if (TheISA::HasUnalignedMemAcc) { 916 splitRequest(req, sreqLow, sreqHigh); 917 } 918 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read); 919 } 920 921 if (translationCompleted()) { 922 if (fault == NoFault) { 923 effAddr = req->getVaddr(); 924 effSize = size; 925 instFlags[EffAddrValid] = true; 926 927 if (cpu->checker) { 928 if (reqToVerify != NULL) { 929 delete reqToVerify; 930 } 931 reqToVerify = new Request(*req); 932 } 933 fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx); 934 } else { 935 // Commit will have to clean up whatever happened. Set this 936 // instruction as executed. 937 this->setExecuted(); 938 } 939 940 if (fault != NoFault) { 941 // Return a fixed value to keep simulation deterministic even 942 // along misspeculated paths. 943 if (data) 944 bzero(data, size); 945 } 946 } 947 948 if (traceData) 949 traceData->setMem(addr, size, flags); 950 951 return fault; 952} 953 954template<class Impl> 955Fault 956BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, 957 Addr addr, unsigned flags, uint64_t *res) 958{ 959 if (traceData) 960 traceData->setMem(addr, size, flags); 961 962 instFlags[ReqMade] = true; 963 Request *req = NULL; 964 Request *sreqLow = NULL; 965 Request *sreqHigh = NULL; 966 967 if (instFlags[ReqMade] && translationStarted()) { 968 req = savedReq; 969 sreqLow = savedSreqLow; 970 sreqHigh = savedSreqHigh; 971 } else { 972 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(), 973 thread->contextId(), threadNumber); 974 975 req->taskId(cpu->taskId()); 976 977 // Only split the request if the ISA supports unaligned accesses. 978 if (TheISA::HasUnalignedMemAcc) { 979 splitRequest(req, sreqLow, sreqHigh); 980 } 981 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write); 982 } 983 984 if (fault == NoFault && translationCompleted()) { 985 effAddr = req->getVaddr(); 986 effSize = size; 987 instFlags[EffAddrValid] = true; 988 989 if (cpu->checker) { 990 if (reqToVerify != NULL) { 991 delete reqToVerify; 992 } 993 reqToVerify = new Request(*req); 994 } 995 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx); 996 } 997 998 return fault; 999} 1000 1001template<class Impl> 1002inline void 1003BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow, 1004 RequestPtr &sreqHigh) 1005{ 1006 // Check to see if the request crosses the next level block boundary. 1007 unsigned block_size = cpu->cacheLineSize(); 1008 Addr addr = req->getVaddr(); 1009 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size); 1010 assert(split_addr <= addr || split_addr - addr < block_size); 1011 1012 // Spans two blocks. 1013 if (split_addr > addr) { 1014 req->splitOnVaddr(split_addr, sreqLow, sreqHigh); 1015 } 1016} 1017 1018template<class Impl> 1019inline void 1020BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow, 1021 RequestPtr sreqHigh, uint64_t *res, 1022 BaseTLB::Mode mode) 1023{ 1024 translationStarted(true); 1025 1026 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) { 1027 WholeTranslationState *state = 1028 new WholeTranslationState(req, NULL, res, mode); 1029 1030 // One translation if the request isn't split. 1031 DataTranslation<BaseDynInstPtr> *trans = 1032 new DataTranslation<BaseDynInstPtr>(this, state); 1033 1034 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode); 1035 1036 if (!translationCompleted()) { 1037 // The translation isn't yet complete, so we can't possibly have a 1038 // fault. Overwrite any existing fault we might have from a previous 1039 // execution of this instruction (e.g. an uncachable load that 1040 // couldn't execute because it wasn't at the head of the ROB). 1041 fault = NoFault; 1042 1043 // Save memory requests. 1044 savedReq = state->mainReq; 1045 savedSreqLow = state->sreqLow; 1046 savedSreqHigh = state->sreqHigh; 1047 } 1048 } else { 1049 WholeTranslationState *state = 1050 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode); 1051 1052 // Two translations when the request is split. 1053 DataTranslation<BaseDynInstPtr> *stransLow = 1054 new DataTranslation<BaseDynInstPtr>(this, state, 0); 1055 DataTranslation<BaseDynInstPtr> *stransHigh = 1056 new DataTranslation<BaseDynInstPtr>(this, state, 1); 1057 1058 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode); 1059 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode); 1060 1061 if (!translationCompleted()) { 1062 // The translation isn't yet complete, so we can't possibly have a 1063 // fault. Overwrite any existing fault we might have from a previous 1064 // execution of this instruction (e.g. an uncachable load that 1065 // couldn't execute because it wasn't at the head of the ROB). 1066 fault = NoFault; 1067 1068 // Save memory requests. 1069 savedReq = state->mainReq; 1070 savedSreqLow = state->sreqLow; 1071 savedSreqHigh = state->sreqHigh; 1072 } 1073 } 1074} 1075 1076template<class Impl> 1077inline void 1078BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state) 1079{ 1080 fault = state->getFault(); 1081 1082 instFlags[IsStrictlyOrdered] = state->isStrictlyOrdered(); 1083 1084 if (fault == NoFault) { 1085 physEffAddr = state->getPaddr(); 1086 memReqFlags = state->getFlags(); 1087 1088 if (state->mainReq->isCondSwap()) { 1089 assert(state->res); 1090 state->mainReq->setExtraData(*state->res); 1091 } 1092 1093 } else { 1094 state->deleteReqs(); 1095 } 1096 delete state; 1097 1098 translationCompleted(true); 1099} 1100 1101#endif // __CPU_BASE_DYN_INST_HH__ 1102