base_dyn_inst.hh revision 10474:799c8ee4ecba
1/*
2 * Copyright (c) 2011,2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * Copyright (c) 2009 The University of Edinburgh
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 *          Timothy M. Jones
44 */
45
46#ifndef __CPU_BASE_DYN_INST_HH__
47#define __CPU_BASE_DYN_INST_HH__
48
49#include <bitset>
50#include <list>
51#include <string>
52#include <queue>
53
54#include "arch/utility.hh"
55#include "base/trace.hh"
56#include "config/the_isa.hh"
57#include "cpu/checker/cpu.hh"
58#include "cpu/o3/comm.hh"
59#include "cpu/exec_context.hh"
60#include "cpu/exetrace.hh"
61#include "cpu/inst_seq.hh"
62#include "cpu/op_class.hh"
63#include "cpu/static_inst.hh"
64#include "cpu/translation.hh"
65#include "mem/packet.hh"
66#include "sim/byteswap.hh"
67#include "sim/system.hh"
68#include "sim/tlb.hh"
69
70/**
71 * @file
72 * Defines a dynamic instruction context.
73 */
74
75template <class Impl>
76class BaseDynInst : public ExecContext, public RefCounted
77{
78  public:
79    // Typedef for the CPU.
80    typedef typename Impl::CPUType ImplCPU;
81    typedef typename ImplCPU::ImplState ImplState;
82
83    // Logical register index type.
84    typedef TheISA::RegIndex RegIndex;
85
86    // The DynInstPtr type.
87    typedef typename Impl::DynInstPtr DynInstPtr;
88    typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr;
89
90    // The list of instructions iterator type.
91    typedef typename std::list<DynInstPtr>::iterator ListIt;
92
93    enum {
94        MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        /// Max source regs
95        MaxInstDestRegs = TheISA::MaxInstDestRegs       /// Max dest regs
96    };
97
98    union Result {
99        uint64_t integer;
100        double dbl;
101        void set(uint64_t i) { integer = i; }
102        void set(double d) { dbl = d; }
103        void get(uint64_t& i) { i = integer; }
104        void get(double& d) { d = dbl; }
105    };
106
107  protected:
108    enum Status {
109        IqEntry,                 /// Instruction is in the IQ
110        RobEntry,                /// Instruction is in the ROB
111        LsqEntry,                /// Instruction is in the LSQ
112        Completed,               /// Instruction has completed
113        ResultReady,             /// Instruction has its result
114        CanIssue,                /// Instruction can issue and execute
115        Issued,                  /// Instruction has issued
116        Executed,                /// Instruction has executed
117        CanCommit,               /// Instruction can commit
118        AtCommit,                /// Instruction has reached commit
119        Committed,               /// Instruction has committed
120        Squashed,                /// Instruction is squashed
121        SquashedInIQ,            /// Instruction is squashed in the IQ
122        SquashedInLSQ,           /// Instruction is squashed in the LSQ
123        SquashedInROB,           /// Instruction is squashed in the ROB
124        RecoverInst,             /// Is a recover instruction
125        BlockingInst,            /// Is a blocking instruction
126        ThreadsyncWait,          /// Is a thread synchronization instruction
127        SerializeBefore,         /// Needs to serialize on
128                                 /// instructions ahead of it
129        SerializeAfter,          /// Needs to serialize instructions behind it
130        SerializeHandled,        /// Serialization has been handled
131        NumStatus
132    };
133
134    enum Flags {
135        TranslationStarted,
136        TranslationCompleted,
137        PossibleLoadViolation,
138        HitExternalSnoop,
139        EffAddrValid,
140        RecordResult,
141        Predicate,
142        PredTaken,
143        /** Whether or not the effective address calculation is completed.
144         *  @todo: Consider if this is necessary or not.
145         */
146        EACalcDone,
147        IsUncacheable,
148        ReqMade,
149        MemOpDone,
150        MaxFlags
151    };
152
153  public:
154    /** The sequence number of the instruction. */
155    InstSeqNum seqNum;
156
157    /** The StaticInst used by this BaseDynInst. */
158    const StaticInstPtr staticInst;
159
160    /** Pointer to the Impl's CPU object. */
161    ImplCPU *cpu;
162
163    BaseCPU *getCpuPtr() { return cpu; }
164
165    /** Pointer to the thread state. */
166    ImplState *thread;
167
168    /** The kind of fault this instruction has generated. */
169    Fault fault;
170
171    /** InstRecord that tracks this instructions. */
172    Trace::InstRecord *traceData;
173
174  protected:
175    /** The result of the instruction; assumes an instruction can have many
176     *  destination registers.
177     */
178    std::queue<Result> instResult;
179
180    /** PC state for this instruction. */
181    TheISA::PCState pc;
182
183    /* An amalgamation of a lot of boolean values into one */
184    std::bitset<MaxFlags> instFlags;
185
186    /** The status of this BaseDynInst.  Several bits can be set. */
187    std::bitset<NumStatus> status;
188
189     /** Whether or not the source register is ready.
190     *  @todo: Not sure this should be here vs the derived class.
191     */
192    std::bitset<MaxInstSrcRegs> _readySrcRegIdx;
193
194  public:
195    /** The thread this instruction is from. */
196    ThreadID threadNumber;
197
198    /** Iterator pointing to this BaseDynInst in the list of all insts. */
199    ListIt instListIt;
200
201    ////////////////////// Branch Data ///////////////
202    /** Predicted PC state after this instruction. */
203    TheISA::PCState predPC;
204
205    /** The Macroop if one exists */
206    const StaticInstPtr macroop;
207
208    /** How many source registers are ready. */
209    uint8_t readyRegs;
210
211  public:
212    /////////////////////// Load Store Data //////////////////////
213    /** The effective virtual address (lds & stores only). */
214    Addr effAddr;
215
216    /** The effective physical address. */
217    Addr physEffAddr;
218
219    /** The memory request flags (from translation). */
220    unsigned memReqFlags;
221
222    /** data address space ID, for loads & stores. */
223    short asid;
224
225    /** The size of the request */
226    uint8_t effSize;
227
228    /** Pointer to the data for the memory access. */
229    uint8_t *memData;
230
231    /** Load queue index. */
232    int16_t lqIdx;
233
234    /** Store queue index. */
235    int16_t sqIdx;
236
237
238    /////////////////////// TLB Miss //////////////////////
239    /**
240     * Saved memory requests (needed when the DTB address translation is
241     * delayed due to a hw page table walk).
242     */
243    RequestPtr savedReq;
244    RequestPtr savedSreqLow;
245    RequestPtr savedSreqHigh;
246
247    /////////////////////// Checker //////////////////////
248    // Need a copy of main request pointer to verify on writes.
249    RequestPtr reqToVerify;
250
251  private:
252    /** Instruction effective address.
253     *  @todo: Consider if this is necessary or not.
254     */
255    Addr instEffAddr;
256
257  protected:
258    /** Flattened register index of the destination registers of this
259     *  instruction.
260     */
261    TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
262
263    /** Physical register index of the destination registers of this
264     *  instruction.
265     */
266    PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs];
267
268    /** Physical register index of the source registers of this
269     *  instruction.
270     */
271    PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs];
272
273    /** Physical register index of the previous producers of the
274     *  architected destinations.
275     */
276    PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs];
277
278
279  public:
280    /** Records changes to result? */
281    void recordResult(bool f) { instFlags[RecordResult] = f; }
282
283    /** Is the effective virtual address valid. */
284    bool effAddrValid() const { return instFlags[EffAddrValid]; }
285
286    /** Whether or not the memory operation is done. */
287    bool memOpDone() const { return instFlags[MemOpDone]; }
288    void memOpDone(bool f) { instFlags[MemOpDone] = f; }
289
290
291    ////////////////////////////////////////////
292    //
293    // INSTRUCTION EXECUTION
294    //
295    ////////////////////////////////////////////
296
297    void demapPage(Addr vaddr, uint64_t asn)
298    {
299        cpu->demapPage(vaddr, asn);
300    }
301    void demapInstPage(Addr vaddr, uint64_t asn)
302    {
303        cpu->demapPage(vaddr, asn);
304    }
305    void demapDataPage(Addr vaddr, uint64_t asn)
306    {
307        cpu->demapPage(vaddr, asn);
308    }
309
310    Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
311
312    Fault writeMem(uint8_t *data, unsigned size,
313                   Addr addr, unsigned flags, uint64_t *res);
314
315    /** Splits a request in two if it crosses a dcache block. */
316    void splitRequest(RequestPtr req, RequestPtr &sreqLow,
317                      RequestPtr &sreqHigh);
318
319    /** Initiate a DTB address translation. */
320    void initiateTranslation(RequestPtr req, RequestPtr sreqLow,
321                             RequestPtr sreqHigh, uint64_t *res,
322                             BaseTLB::Mode mode);
323
324    /** Finish a DTB address translation. */
325    void finishTranslation(WholeTranslationState *state);
326
327    /** True if the DTB address translation has started. */
328    bool translationStarted() const { return instFlags[TranslationStarted]; }
329    void translationStarted(bool f) { instFlags[TranslationStarted] = f; }
330
331    /** True if the DTB address translation has completed. */
332    bool translationCompleted() const { return instFlags[TranslationCompleted]; }
333    void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; }
334
335    /** True if this address was found to match a previous load and they issued
336     * out of order. If that happend, then it's only a problem if an incoming
337     * snoop invalidate modifies the line, in which case we need to squash.
338     * If nothing modified the line the order doesn't matter.
339     */
340    bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; }
341    void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; }
342
343    /** True if the address hit a external snoop while sitting in the LSQ.
344     * If this is true and a older instruction sees it, this instruction must
345     * reexecute
346     */
347    bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; }
348    void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; }
349
350    /**
351     * Returns true if the DTB address translation is being delayed due to a hw
352     * page table walk.
353     */
354    bool isTranslationDelayed() const
355    {
356        return (translationStarted() && !translationCompleted());
357    }
358
359  public:
360#ifdef DEBUG
361    void dumpSNList();
362#endif
363
364    /** Returns the physical register index of the i'th destination
365     *  register.
366     */
367    PhysRegIndex renamedDestRegIdx(int idx) const
368    {
369        return _destRegIdx[idx];
370    }
371
372    /** Returns the physical register index of the i'th source register. */
373    PhysRegIndex renamedSrcRegIdx(int idx) const
374    {
375        assert(TheISA::MaxInstSrcRegs > idx);
376        return _srcRegIdx[idx];
377    }
378
379    /** Returns the flattened register index of the i'th destination
380     *  register.
381     */
382    TheISA::RegIndex flattenedDestRegIdx(int idx) const
383    {
384        return _flatDestRegIdx[idx];
385    }
386
387    /** Returns the physical register index of the previous physical register
388     *  that remapped to the same logical register index.
389     */
390    PhysRegIndex prevDestRegIdx(int idx) const
391    {
392        return _prevDestRegIdx[idx];
393    }
394
395    /** Renames a destination register to a physical register.  Also records
396     *  the previous physical register that the logical register mapped to.
397     */
398    void renameDestReg(int idx,
399                       PhysRegIndex renamed_dest,
400                       PhysRegIndex previous_rename)
401    {
402        _destRegIdx[idx] = renamed_dest;
403        _prevDestRegIdx[idx] = previous_rename;
404    }
405
406    /** Renames a source logical register to the physical register which
407     *  has/will produce that logical register's result.
408     *  @todo: add in whether or not the source register is ready.
409     */
410    void renameSrcReg(int idx, PhysRegIndex renamed_src)
411    {
412        _srcRegIdx[idx] = renamed_src;
413    }
414
415    /** Flattens a destination architectural register index into a logical
416     * index.
417     */
418    void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
419    {
420        _flatDestRegIdx[idx] = flattened_dest;
421    }
422    /** BaseDynInst constructor given a binary instruction.
423     *  @param staticInst A StaticInstPtr to the underlying instruction.
424     *  @param pc The PC state for the instruction.
425     *  @param predPC The predicted next PC state for the instruction.
426     *  @param seq_num The sequence number of the instruction.
427     *  @param cpu Pointer to the instruction's CPU.
428     */
429    BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr &macroop,
430                TheISA::PCState pc, TheISA::PCState predPC,
431                InstSeqNum seq_num, ImplCPU *cpu);
432
433    /** BaseDynInst constructor given a StaticInst pointer.
434     *  @param _staticInst The StaticInst for this BaseDynInst.
435     */
436    BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr &macroop);
437
438    /** BaseDynInst destructor. */
439    ~BaseDynInst();
440
441  private:
442    /** Function to initialize variables in the constructors. */
443    void initVars();
444
445  public:
446    /** Dumps out contents of this BaseDynInst. */
447    void dump();
448
449    /** Dumps out contents of this BaseDynInst into given string. */
450    void dump(std::string &outstring);
451
452    /** Read this CPU's ID. */
453    int cpuId() const { return cpu->cpuId(); }
454
455    /** Read this CPU's Socket ID. */
456    uint32_t socketId() const { return cpu->socketId(); }
457
458    /** Read this CPU's data requestor ID */
459    MasterID masterId() const { return cpu->dataMasterId(); }
460
461    /** Read this context's system-wide ID **/
462    int contextId() const { return thread->contextId(); }
463
464    /** Returns the fault type. */
465    Fault getFault() const { return fault; }
466
467    /** Checks whether or not this instruction has had its branch target
468     *  calculated yet.  For now it is not utilized and is hacked to be
469     *  always false.
470     *  @todo: Actually use this instruction.
471     */
472    bool doneTargCalc() { return false; }
473
474    /** Set the predicted target of this current instruction. */
475    void setPredTarg(const TheISA::PCState &_predPC)
476    {
477        predPC = _predPC;
478    }
479
480    const TheISA::PCState &readPredTarg() { return predPC; }
481
482    /** Returns the predicted PC immediately after the branch. */
483    Addr predInstAddr() { return predPC.instAddr(); }
484
485    /** Returns the predicted PC two instructions after the branch */
486    Addr predNextInstAddr() { return predPC.nextInstAddr(); }
487
488    /** Returns the predicted micro PC after the branch */
489    Addr predMicroPC() { return predPC.microPC(); }
490
491    /** Returns whether the instruction was predicted taken or not. */
492    bool readPredTaken()
493    {
494        return instFlags[PredTaken];
495    }
496
497    void setPredTaken(bool predicted_taken)
498    {
499        instFlags[PredTaken] = predicted_taken;
500    }
501
502    /** Returns whether the instruction mispredicted. */
503    bool mispredicted()
504    {
505        TheISA::PCState tempPC = pc;
506        TheISA::advancePC(tempPC, staticInst);
507        return !(tempPC == predPC);
508    }
509
510    //
511    //  Instruction types.  Forward checks to StaticInst object.
512    //
513    bool isNop()          const { return staticInst->isNop(); }
514    bool isMemRef()       const { return staticInst->isMemRef(); }
515    bool isLoad()         const { return staticInst->isLoad(); }
516    bool isStore()        const { return staticInst->isStore(); }
517    bool isStoreConditional() const
518    { return staticInst->isStoreConditional(); }
519    bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
520    bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
521    bool isInteger()      const { return staticInst->isInteger(); }
522    bool isFloating()     const { return staticInst->isFloating(); }
523    bool isControl()      const { return staticInst->isControl(); }
524    bool isCall()         const { return staticInst->isCall(); }
525    bool isReturn()       const { return staticInst->isReturn(); }
526    bool isDirectCtrl()   const { return staticInst->isDirectCtrl(); }
527    bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
528    bool isCondCtrl()     const { return staticInst->isCondCtrl(); }
529    bool isUncondCtrl()   const { return staticInst->isUncondCtrl(); }
530    bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
531    bool isThreadSync()   const { return staticInst->isThreadSync(); }
532    bool isSerializing()  const { return staticInst->isSerializing(); }
533    bool isSerializeBefore() const
534    { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
535    bool isSerializeAfter() const
536    { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
537    bool isSquashAfter() const { return staticInst->isSquashAfter(); }
538    bool isMemBarrier()   const { return staticInst->isMemBarrier(); }
539    bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
540    bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
541    bool isQuiesce() const { return staticInst->isQuiesce(); }
542    bool isIprAccess() const { return staticInst->isIprAccess(); }
543    bool isUnverifiable() const { return staticInst->isUnverifiable(); }
544    bool isSyscall() const { return staticInst->isSyscall(); }
545    bool isMacroop() const { return staticInst->isMacroop(); }
546    bool isMicroop() const { return staticInst->isMicroop(); }
547    bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
548    bool isLastMicroop() const { return staticInst->isLastMicroop(); }
549    bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
550    bool isMicroBranch() const { return staticInst->isMicroBranch(); }
551
552    /** Temporarily sets this instruction as a serialize before instruction. */
553    void setSerializeBefore() { status.set(SerializeBefore); }
554
555    /** Clears the serializeBefore part of this instruction. */
556    void clearSerializeBefore() { status.reset(SerializeBefore); }
557
558    /** Checks if this serializeBefore is only temporarily set. */
559    bool isTempSerializeBefore() { return status[SerializeBefore]; }
560
561    /** Temporarily sets this instruction as a serialize after instruction. */
562    void setSerializeAfter() { status.set(SerializeAfter); }
563
564    /** Clears the serializeAfter part of this instruction.*/
565    void clearSerializeAfter() { status.reset(SerializeAfter); }
566
567    /** Checks if this serializeAfter is only temporarily set. */
568    bool isTempSerializeAfter() { return status[SerializeAfter]; }
569
570    /** Sets the serialization part of this instruction as handled. */
571    void setSerializeHandled() { status.set(SerializeHandled); }
572
573    /** Checks if the serialization part of this instruction has been
574     *  handled.  This does not apply to the temporary serializing
575     *  state; it only applies to this instruction's own permanent
576     *  serializing state.
577     */
578    bool isSerializeHandled() { return status[SerializeHandled]; }
579
580    /** Returns the opclass of this instruction. */
581    OpClass opClass() const { return staticInst->opClass(); }
582
583    /** Returns the branch target address. */
584    TheISA::PCState branchTarget() const
585    { return staticInst->branchTarget(pc); }
586
587    /** Returns the number of source registers. */
588    int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
589
590    /** Returns the number of destination registers. */
591    int8_t numDestRegs() const { return staticInst->numDestRegs(); }
592
593    // the following are used to track physical register usage
594    // for machines with separate int & FP reg files
595    int8_t numFPDestRegs()  const { return staticInst->numFPDestRegs(); }
596    int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
597
598    /** Returns the logical register index of the i'th destination register. */
599    RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
600
601    /** Returns the logical register index of the i'th source register. */
602    RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
603
604    /** Pops a result off the instResult queue */
605    template <class T>
606    void popResult(T& t)
607    {
608        if (!instResult.empty()) {
609            instResult.front().get(t);
610            instResult.pop();
611        }
612    }
613
614    /** Read the most recent result stored by this instruction */
615    template <class T>
616    void readResult(T& t)
617    {
618        instResult.back().get(t);
619    }
620
621    /** Pushes a result onto the instResult queue */
622    template <class T>
623    void setResult(T t)
624    {
625        if (instFlags[RecordResult]) {
626            Result instRes;
627            instRes.set(t);
628            instResult.push(instRes);
629        }
630    }
631
632    /** Records an integer register being set to a value. */
633    void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
634    {
635        setResult<uint64_t>(val);
636    }
637
638    /** Records a CC register being set to a value. */
639    void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
640    {
641        setResult<uint64_t>(val);
642    }
643
644    /** Records an fp register being set to a value. */
645    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
646    {
647        setResult<double>(val);
648    }
649
650    /** Records an fp register being set to an integer value. */
651    void setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val)
652    {
653        setResult<uint64_t>(val);
654    }
655
656    /** Records that one of the source registers is ready. */
657    void markSrcRegReady();
658
659    /** Marks a specific register as ready. */
660    void markSrcRegReady(RegIndex src_idx);
661
662    /** Returns if a source register is ready. */
663    bool isReadySrcRegIdx(int idx) const
664    {
665        return this->_readySrcRegIdx[idx];
666    }
667
668    /** Sets this instruction as completed. */
669    void setCompleted() { status.set(Completed); }
670
671    /** Returns whether or not this instruction is completed. */
672    bool isCompleted() const { return status[Completed]; }
673
674    /** Marks the result as ready. */
675    void setResultReady() { status.set(ResultReady); }
676
677    /** Returns whether or not the result is ready. */
678    bool isResultReady() const { return status[ResultReady]; }
679
680    /** Sets this instruction as ready to issue. */
681    void setCanIssue() { status.set(CanIssue); }
682
683    /** Returns whether or not this instruction is ready to issue. */
684    bool readyToIssue() const { return status[CanIssue]; }
685
686    /** Clears this instruction being able to issue. */
687    void clearCanIssue() { status.reset(CanIssue); }
688
689    /** Sets this instruction as issued from the IQ. */
690    void setIssued() { status.set(Issued); }
691
692    /** Returns whether or not this instruction has issued. */
693    bool isIssued() const { return status[Issued]; }
694
695    /** Clears this instruction as being issued. */
696    void clearIssued() { status.reset(Issued); }
697
698    /** Sets this instruction as executed. */
699    void setExecuted() { status.set(Executed); }
700
701    /** Returns whether or not this instruction has executed. */
702    bool isExecuted() const { return status[Executed]; }
703
704    /** Sets this instruction as ready to commit. */
705    void setCanCommit() { status.set(CanCommit); }
706
707    /** Clears this instruction as being ready to commit. */
708    void clearCanCommit() { status.reset(CanCommit); }
709
710    /** Returns whether or not this instruction is ready to commit. */
711    bool readyToCommit() const { return status[CanCommit]; }
712
713    void setAtCommit() { status.set(AtCommit); }
714
715    bool isAtCommit() { return status[AtCommit]; }
716
717    /** Sets this instruction as committed. */
718    void setCommitted() { status.set(Committed); }
719
720    /** Returns whether or not this instruction is committed. */
721    bool isCommitted() const { return status[Committed]; }
722
723    /** Sets this instruction as squashed. */
724    void setSquashed() { status.set(Squashed); }
725
726    /** Returns whether or not this instruction is squashed. */
727    bool isSquashed() const { return status[Squashed]; }
728
729    //Instruction Queue Entry
730    //-----------------------
731    /** Sets this instruction as a entry the IQ. */
732    void setInIQ() { status.set(IqEntry); }
733
734    /** Sets this instruction as a entry the IQ. */
735    void clearInIQ() { status.reset(IqEntry); }
736
737    /** Returns whether or not this instruction has issued. */
738    bool isInIQ() const { return status[IqEntry]; }
739
740    /** Sets this instruction as squashed in the IQ. */
741    void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
742
743    /** Returns whether or not this instruction is squashed in the IQ. */
744    bool isSquashedInIQ() const { return status[SquashedInIQ]; }
745
746
747    //Load / Store Queue Functions
748    //-----------------------
749    /** Sets this instruction as a entry the LSQ. */
750    void setInLSQ() { status.set(LsqEntry); }
751
752    /** Sets this instruction as a entry the LSQ. */
753    void removeInLSQ() { status.reset(LsqEntry); }
754
755    /** Returns whether or not this instruction is in the LSQ. */
756    bool isInLSQ() const { return status[LsqEntry]; }
757
758    /** Sets this instruction as squashed in the LSQ. */
759    void setSquashedInLSQ() { status.set(SquashedInLSQ);}
760
761    /** Returns whether or not this instruction is squashed in the LSQ. */
762    bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
763
764
765    //Reorder Buffer Functions
766    //-----------------------
767    /** Sets this instruction as a entry the ROB. */
768    void setInROB() { status.set(RobEntry); }
769
770    /** Sets this instruction as a entry the ROB. */
771    void clearInROB() { status.reset(RobEntry); }
772
773    /** Returns whether or not this instruction is in the ROB. */
774    bool isInROB() const { return status[RobEntry]; }
775
776    /** Sets this instruction as squashed in the ROB. */
777    void setSquashedInROB() { status.set(SquashedInROB); }
778
779    /** Returns whether or not this instruction is squashed in the ROB. */
780    bool isSquashedInROB() const { return status[SquashedInROB]; }
781
782    /** Read the PC state of this instruction. */
783    TheISA::PCState pcState() const { return pc; }
784
785    /** Set the PC state of this instruction. */
786    void pcState(const TheISA::PCState &val) { pc = val; }
787
788    /** Read the PC of this instruction. */
789    const Addr instAddr() const { return pc.instAddr(); }
790
791    /** Read the PC of the next instruction. */
792    const Addr nextInstAddr() const { return pc.nextInstAddr(); }
793
794    /**Read the micro PC of this instruction. */
795    const Addr microPC() const { return pc.microPC(); }
796
797    bool readPredicate()
798    {
799        return instFlags[Predicate];
800    }
801
802    void setPredicate(bool val)
803    {
804        instFlags[Predicate] = val;
805
806        if (traceData) {
807            traceData->setPredicate(val);
808        }
809    }
810
811    /** Sets the ASID. */
812    void setASID(short addr_space_id) { asid = addr_space_id; }
813
814    /** Sets the thread id. */
815    void setTid(ThreadID tid) { threadNumber = tid; }
816
817    /** Sets the pointer to the thread state. */
818    void setThreadState(ImplState *state) { thread = state; }
819
820    /** Returns the thread context. */
821    ThreadContext *tcBase() { return thread->getTC(); }
822
823  public:
824    /** Sets the effective address. */
825    void setEA(Addr ea) { instEffAddr = ea; instFlags[EACalcDone] = true; }
826
827    /** Returns the effective address. */
828    Addr getEA() const { return instEffAddr; }
829
830    /** Returns whether or not the eff. addr. calculation has been completed. */
831    bool doneEACalc() { return instFlags[EACalcDone]; }
832
833    /** Returns whether or not the eff. addr. source registers are ready. */
834    bool eaSrcsReady();
835
836    /** Is this instruction's memory access uncacheable. */
837    bool uncacheable() { return instFlags[IsUncacheable]; }
838
839    /** Has this instruction generated a memory request. */
840    bool hasRequest() { return instFlags[ReqMade]; }
841
842    /** Returns iterator to this instruction in the list of all insts. */
843    ListIt &getInstListIt() { return instListIt; }
844
845    /** Sets iterator for this instruction in the list of all insts. */
846    void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
847
848  public:
849    /** Returns the number of consecutive store conditional failures. */
850    unsigned int readStCondFailures() const
851    { return thread->storeCondFailures; }
852
853    /** Sets the number of consecutive store conditional failures. */
854    void setStCondFailures(unsigned int sc_failures)
855    { thread->storeCondFailures = sc_failures; }
856};
857
858template<class Impl>
859Fault
860BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data,
861                           unsigned size, unsigned flags)
862{
863    instFlags[ReqMade] = true;
864    Request *req = NULL;
865    Request *sreqLow = NULL;
866    Request *sreqHigh = NULL;
867
868    if (instFlags[ReqMade] && translationStarted()) {
869        req = savedReq;
870        sreqLow = savedSreqLow;
871        sreqHigh = savedSreqHigh;
872    } else {
873        req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
874                          thread->contextId(), threadNumber);
875
876        req->taskId(cpu->taskId());
877
878        // Only split the request if the ISA supports unaligned accesses.
879        if (TheISA::HasUnalignedMemAcc) {
880            splitRequest(req, sreqLow, sreqHigh);
881        }
882        initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
883    }
884
885    if (translationCompleted()) {
886        if (fault == NoFault) {
887            effAddr = req->getVaddr();
888            effSize = size;
889            instFlags[EffAddrValid] = true;
890
891            if (cpu->checker) {
892                if (reqToVerify != NULL) {
893                    delete reqToVerify;
894                }
895                reqToVerify = new Request(*req);
896            }
897            fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx);
898        } else {
899            // Commit will have to clean up whatever happened.  Set this
900            // instruction as executed.
901            this->setExecuted();
902        }
903
904        if (fault != NoFault) {
905            // Return a fixed value to keep simulation deterministic even
906            // along misspeculated paths.
907            if (data)
908                bzero(data, size);
909        }
910    }
911
912    if (traceData) {
913        traceData->setAddr(addr);
914    }
915
916    return fault;
917}
918
919template<class Impl>
920Fault
921BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size,
922                            Addr addr, unsigned flags, uint64_t *res)
923{
924    if (traceData) {
925        traceData->setAddr(addr);
926    }
927
928    instFlags[ReqMade] = true;
929    Request *req = NULL;
930    Request *sreqLow = NULL;
931    Request *sreqHigh = NULL;
932
933    if (instFlags[ReqMade] && translationStarted()) {
934        req = savedReq;
935        sreqLow = savedSreqLow;
936        sreqHigh = savedSreqHigh;
937    } else {
938        req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
939                          thread->contextId(), threadNumber);
940
941        req->taskId(cpu->taskId());
942
943        // Only split the request if the ISA supports unaligned accesses.
944        if (TheISA::HasUnalignedMemAcc) {
945            splitRequest(req, sreqLow, sreqHigh);
946        }
947        initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write);
948    }
949
950    if (fault == NoFault && translationCompleted()) {
951        effAddr = req->getVaddr();
952        effSize = size;
953        instFlags[EffAddrValid] = true;
954
955        if (cpu->checker) {
956            if (reqToVerify != NULL) {
957                delete reqToVerify;
958            }
959            reqToVerify = new Request(*req);
960        }
961        fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
962    }
963
964    return fault;
965}
966
967template<class Impl>
968inline void
969BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow,
970                                RequestPtr &sreqHigh)
971{
972    // Check to see if the request crosses the next level block boundary.
973    unsigned block_size = cpu->cacheLineSize();
974    Addr addr = req->getVaddr();
975    Addr split_addr = roundDown(addr + req->getSize() - 1, block_size);
976    assert(split_addr <= addr || split_addr - addr < block_size);
977
978    // Spans two blocks.
979    if (split_addr > addr) {
980        req->splitOnVaddr(split_addr, sreqLow, sreqHigh);
981    }
982}
983
984template<class Impl>
985inline void
986BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow,
987                                       RequestPtr sreqHigh, uint64_t *res,
988                                       BaseTLB::Mode mode)
989{
990    translationStarted(true);
991
992    if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) {
993        WholeTranslationState *state =
994            new WholeTranslationState(req, NULL, res, mode);
995
996        // One translation if the request isn't split.
997        DataTranslation<BaseDynInstPtr> *trans =
998            new DataTranslation<BaseDynInstPtr>(this, state);
999
1000        cpu->dtb->translateTiming(req, thread->getTC(), trans, mode);
1001
1002        if (!translationCompleted()) {
1003            // The translation isn't yet complete, so we can't possibly have a
1004            // fault. Overwrite any existing fault we might have from a previous
1005            // execution of this instruction (e.g. an uncachable load that
1006            // couldn't execute because it wasn't at the head of the ROB).
1007            fault = NoFault;
1008
1009            // Save memory requests.
1010            savedReq = state->mainReq;
1011            savedSreqLow = state->sreqLow;
1012            savedSreqHigh = state->sreqHigh;
1013        }
1014    } else {
1015        WholeTranslationState *state =
1016            new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode);
1017
1018        // Two translations when the request is split.
1019        DataTranslation<BaseDynInstPtr> *stransLow =
1020            new DataTranslation<BaseDynInstPtr>(this, state, 0);
1021        DataTranslation<BaseDynInstPtr> *stransHigh =
1022            new DataTranslation<BaseDynInstPtr>(this, state, 1);
1023
1024        cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode);
1025        cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode);
1026
1027        if (!translationCompleted()) {
1028            // The translation isn't yet complete, so we can't possibly have a
1029            // fault. Overwrite any existing fault we might have from a previous
1030            // execution of this instruction (e.g. an uncachable load that
1031            // couldn't execute because it wasn't at the head of the ROB).
1032            fault = NoFault;
1033
1034            // Save memory requests.
1035            savedReq = state->mainReq;
1036            savedSreqLow = state->sreqLow;
1037            savedSreqHigh = state->sreqHigh;
1038        }
1039    }
1040}
1041
1042template<class Impl>
1043inline void
1044BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state)
1045{
1046    fault = state->getFault();
1047
1048    instFlags[IsUncacheable] = state->isUncacheable();
1049
1050    if (fault == NoFault) {
1051        physEffAddr = state->getPaddr();
1052        memReqFlags = state->getFlags();
1053
1054        if (state->mainReq->isCondSwap()) {
1055            assert(state->res);
1056            state->mainReq->setExtraData(*state->res);
1057        }
1058
1059    } else {
1060        state->deleteReqs();
1061    }
1062    delete state;
1063
1064    translationCompleted(true);
1065}
1066
1067#endif // __CPU_BASE_DYN_INST_HH__
1068