base_dyn_inst.hh revision 8733
1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan 15 * Copyright (c) 2009 The University of Edinburgh 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 * Timothy M. Jones 43 */ 44 45#ifndef __CPU_BASE_DYN_INST_HH__ 46#define __CPU_BASE_DYN_INST_HH__ 47 48#include <bitset> 49#include <list> 50#include <string> 51#include <queue> 52 53#include "arch/faults.hh" 54#include "arch/utility.hh" 55#include "base/fast_alloc.hh" 56#include "base/trace.hh" 57#include "config/full_system.hh" 58#include "config/the_isa.hh" 59#include "config/use_checker.hh" 60#include "cpu/o3/comm.hh" 61#include "cpu/exetrace.hh" 62#include "cpu/inst_seq.hh" 63#include "cpu/op_class.hh" 64#include "cpu/static_inst.hh" 65#include "cpu/translation.hh" 66#include "mem/packet.hh" 67#include "sim/byteswap.hh" 68#include "sim/system.hh" 69#include "sim/tlb.hh" 70 71/** 72 * @file 73 * Defines a dynamic instruction context. 74 */ 75 76template <class Impl> 77class BaseDynInst : public FastAlloc, public RefCounted 78{ 79 public: 80 // Typedef for the CPU. 81 typedef typename Impl::CPUType ImplCPU; 82 typedef typename ImplCPU::ImplState ImplState; 83 84 // Logical register index type. 85 typedef TheISA::RegIndex RegIndex; 86 // Integer register type. 87 typedef TheISA::IntReg IntReg; 88 // Floating point register type. 89 typedef TheISA::FloatReg FloatReg; 90 91 // The DynInstPtr type. 92 typedef typename Impl::DynInstPtr DynInstPtr; 93 typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr; 94 95 // The list of instructions iterator type. 96 typedef typename std::list<DynInstPtr>::iterator ListIt; 97 98 enum { 99 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 100 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs 101 }; 102 103 /** The StaticInst used by this BaseDynInst. */ 104 StaticInstPtr staticInst; 105 StaticInstPtr macroop; 106 107 //////////////////////////////////////////// 108 // 109 // INSTRUCTION EXECUTION 110 // 111 //////////////////////////////////////////// 112 /** InstRecord that tracks this instructions. */ 113 Trace::InstRecord *traceData; 114 115 void demapPage(Addr vaddr, uint64_t asn) 116 { 117 cpu->demapPage(vaddr, asn); 118 } 119 void demapInstPage(Addr vaddr, uint64_t asn) 120 { 121 cpu->demapPage(vaddr, asn); 122 } 123 void demapDataPage(Addr vaddr, uint64_t asn) 124 { 125 cpu->demapPage(vaddr, asn); 126 } 127 128 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 129 130 Fault writeMem(uint8_t *data, unsigned size, 131 Addr addr, unsigned flags, uint64_t *res); 132 133 /** Splits a request in two if it crosses a dcache block. */ 134 void splitRequest(RequestPtr req, RequestPtr &sreqLow, 135 RequestPtr &sreqHigh); 136 137 /** Initiate a DTB address translation. */ 138 void initiateTranslation(RequestPtr req, RequestPtr sreqLow, 139 RequestPtr sreqHigh, uint64_t *res, 140 BaseTLB::Mode mode); 141 142 /** Finish a DTB address translation. */ 143 void finishTranslation(WholeTranslationState *state); 144 145 /** True if the DTB address translation has started. */ 146 bool translationStarted; 147 148 /** True if the DTB address translation has completed. */ 149 bool translationCompleted; 150 151 /** True if this address was found to match a previous load and they issued 152 * out of order. If that happend, then it's only a problem if an incoming 153 * snoop invalidate modifies the line, in which case we need to squash. 154 * If nothing modified the line the order doesn't matter. 155 */ 156 bool possibleLoadViolation; 157 158 /** True if the address hit a external snoop while sitting in the LSQ. 159 * If this is true and a older instruction sees it, this instruction must 160 * reexecute 161 */ 162 bool hitExternalSnoop; 163 164 /** 165 * Returns true if the DTB address translation is being delayed due to a hw 166 * page table walk. 167 */ 168 bool isTranslationDelayed() const 169 { 170 return (translationStarted && !translationCompleted); 171 } 172 173 /** 174 * Saved memory requests (needed when the DTB address translation is 175 * delayed due to a hw page table walk). 176 */ 177 RequestPtr savedReq; 178 RequestPtr savedSreqLow; 179 RequestPtr savedSreqHigh; 180 181#if USE_CHECKER 182 // Need a copy of main request pointer to verify on writes. 183 RequestPtr reqToVerify; 184#endif //USE_CHECKER 185 186 /** @todo: Consider making this private. */ 187 public: 188 /** The sequence number of the instruction. */ 189 InstSeqNum seqNum; 190 191 enum Status { 192 IqEntry, /// Instruction is in the IQ 193 RobEntry, /// Instruction is in the ROB 194 LsqEntry, /// Instruction is in the LSQ 195 Completed, /// Instruction has completed 196 ResultReady, /// Instruction has its result 197 CanIssue, /// Instruction can issue and execute 198 Issued, /// Instruction has issued 199 Executed, /// Instruction has executed 200 CanCommit, /// Instruction can commit 201 AtCommit, /// Instruction has reached commit 202 Committed, /// Instruction has committed 203 Squashed, /// Instruction is squashed 204 SquashedInIQ, /// Instruction is squashed in the IQ 205 SquashedInLSQ, /// Instruction is squashed in the LSQ 206 SquashedInROB, /// Instruction is squashed in the ROB 207 RecoverInst, /// Is a recover instruction 208 BlockingInst, /// Is a blocking instruction 209 ThreadsyncWait, /// Is a thread synchronization instruction 210 SerializeBefore, /// Needs to serialize on 211 /// instructions ahead of it 212 SerializeAfter, /// Needs to serialize instructions behind it 213 SerializeHandled, /// Serialization has been handled 214 NumStatus 215 }; 216 217 /** The status of this BaseDynInst. Several bits can be set. */ 218 std::bitset<NumStatus> status; 219 220 /** The thread this instruction is from. */ 221 ThreadID threadNumber; 222 223 /** data address space ID, for loads & stores. */ 224 short asid; 225 226 /** How many source registers are ready. */ 227 unsigned readyRegs; 228 229 /** Pointer to the Impl's CPU object. */ 230 ImplCPU *cpu; 231 232 /** Pointer to the thread state. */ 233 ImplState *thread; 234 235 /** The kind of fault this instruction has generated. */ 236 Fault fault; 237 238 /** Pointer to the data for the memory access. */ 239 uint8_t *memData; 240 241 /** The effective virtual address (lds & stores only). */ 242 Addr effAddr; 243 244 /** The size of the request */ 245 Addr effSize; 246 247 /** Is the effective virtual address valid. */ 248 bool effAddrValid; 249 250 /** The effective physical address. */ 251 Addr physEffAddr; 252 253 /** The memory request flags (from translation). */ 254 unsigned memReqFlags; 255 256 union Result { 257 uint64_t integer; 258 double dbl; 259 void set(uint64_t i) { integer = i; } 260 void set(double d) { dbl = d; } 261 void get(uint64_t& i) { i = integer; } 262 void get(double& d) { d = dbl; } 263 }; 264 265 /** The result of the instruction; assumes an instruction can have many 266 * destination registers. 267 */ 268 std::queue<Result> instResult; 269 270 /** Records changes to result? */ 271 bool recordResult; 272 273 /** Did this instruction execute, or is it predicated false */ 274 bool predicate; 275 276 protected: 277 /** PC state for this instruction. */ 278 TheISA::PCState pc; 279 280 /** Predicted PC state after this instruction. */ 281 TheISA::PCState predPC; 282 283 /** If this is a branch that was predicted taken */ 284 bool predTaken; 285 286 public: 287 288#ifdef DEBUG 289 void dumpSNList(); 290#endif 291 292 /** Whether or not the source register is ready. 293 * @todo: Not sure this should be here vs the derived class. 294 */ 295 bool _readySrcRegIdx[MaxInstSrcRegs]; 296 297 protected: 298 /** Flattened register index of the destination registers of this 299 * instruction. 300 */ 301 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs]; 302 303 /** Flattened register index of the source registers of this 304 * instruction. 305 */ 306 TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs]; 307 308 /** Physical register index of the destination registers of this 309 * instruction. 310 */ 311 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs]; 312 313 /** Physical register index of the source registers of this 314 * instruction. 315 */ 316 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs]; 317 318 /** Physical register index of the previous producers of the 319 * architected destinations. 320 */ 321 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs]; 322 323 public: 324 325 /** Returns the physical register index of the i'th destination 326 * register. 327 */ 328 PhysRegIndex renamedDestRegIdx(int idx) const 329 { 330 return _destRegIdx[idx]; 331 } 332 333 /** Returns the physical register index of the i'th source register. */ 334 PhysRegIndex renamedSrcRegIdx(int idx) const 335 { 336 return _srcRegIdx[idx]; 337 } 338 339 /** Returns the flattened register index of the i'th destination 340 * register. 341 */ 342 TheISA::RegIndex flattenedDestRegIdx(int idx) const 343 { 344 return _flatDestRegIdx[idx]; 345 } 346 347 /** Returns the flattened register index of the i'th source register */ 348 TheISA::RegIndex flattenedSrcRegIdx(int idx) const 349 { 350 return _flatSrcRegIdx[idx]; 351 } 352 353 /** Returns the physical register index of the previous physical register 354 * that remapped to the same logical register index. 355 */ 356 PhysRegIndex prevDestRegIdx(int idx) const 357 { 358 return _prevDestRegIdx[idx]; 359 } 360 361 /** Renames a destination register to a physical register. Also records 362 * the previous physical register that the logical register mapped to. 363 */ 364 void renameDestReg(int idx, 365 PhysRegIndex renamed_dest, 366 PhysRegIndex previous_rename) 367 { 368 _destRegIdx[idx] = renamed_dest; 369 _prevDestRegIdx[idx] = previous_rename; 370 } 371 372 /** Renames a source logical register to the physical register which 373 * has/will produce that logical register's result. 374 * @todo: add in whether or not the source register is ready. 375 */ 376 void renameSrcReg(int idx, PhysRegIndex renamed_src) 377 { 378 _srcRegIdx[idx] = renamed_src; 379 } 380 381 /** Flattens a source architectural register index into a logical index. 382 */ 383 void flattenSrcReg(int idx, TheISA::RegIndex flattened_src) 384 { 385 _flatSrcRegIdx[idx] = flattened_src; 386 } 387 388 /** Flattens a destination architectural register index into a logical 389 * index. 390 */ 391 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 392 { 393 _flatDestRegIdx[idx] = flattened_dest; 394 } 395 /** BaseDynInst constructor given a binary instruction. 396 * @param staticInst A StaticInstPtr to the underlying instruction. 397 * @param pc The PC state for the instruction. 398 * @param predPC The predicted next PC state for the instruction. 399 * @param seq_num The sequence number of the instruction. 400 * @param cpu Pointer to the instruction's CPU. 401 */ 402 BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop, 403 TheISA::PCState pc, TheISA::PCState predPC, 404 InstSeqNum seq_num, ImplCPU *cpu); 405 406 /** BaseDynInst constructor given a StaticInst pointer. 407 * @param _staticInst The StaticInst for this BaseDynInst. 408 */ 409 BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop); 410 411 /** BaseDynInst destructor. */ 412 ~BaseDynInst(); 413 414 private: 415 /** Function to initialize variables in the constructors. */ 416 void initVars(); 417 418 public: 419 /** Dumps out contents of this BaseDynInst. */ 420 void dump(); 421 422 /** Dumps out contents of this BaseDynInst into given string. */ 423 void dump(std::string &outstring); 424 425 /** Read this CPU's ID. */ 426 int cpuId() { return cpu->cpuId(); } 427 428 /** Read this context's system-wide ID **/ 429 int contextId() { return thread->contextId(); } 430 431 /** Returns the fault type. */ 432 Fault getFault() { return fault; } 433 434 /** Checks whether or not this instruction has had its branch target 435 * calculated yet. For now it is not utilized and is hacked to be 436 * always false. 437 * @todo: Actually use this instruction. 438 */ 439 bool doneTargCalc() { return false; } 440 441 /** Set the predicted target of this current instruction. */ 442 void setPredTarg(const TheISA::PCState &_predPC) 443 { 444 predPC = _predPC; 445 } 446 447 const TheISA::PCState &readPredTarg() { return predPC; } 448 449 /** Returns the predicted PC immediately after the branch. */ 450 Addr predInstAddr() { return predPC.instAddr(); } 451 452 /** Returns the predicted PC two instructions after the branch */ 453 Addr predNextInstAddr() { return predPC.nextInstAddr(); } 454 455 /** Returns the predicted micro PC after the branch */ 456 Addr predMicroPC() { return predPC.microPC(); } 457 458 /** Returns whether the instruction was predicted taken or not. */ 459 bool readPredTaken() 460 { 461 return predTaken; 462 } 463 464 void setPredTaken(bool predicted_taken) 465 { 466 predTaken = predicted_taken; 467 } 468 469 /** Returns whether the instruction mispredicted. */ 470 bool mispredicted() 471 { 472 TheISA::PCState tempPC = pc; 473 TheISA::advancePC(tempPC, staticInst); 474 return !(tempPC == predPC); 475 } 476 477 // 478 // Instruction types. Forward checks to StaticInst object. 479 // 480 bool isNop() const { return staticInst->isNop(); } 481 bool isMemRef() const { return staticInst->isMemRef(); } 482 bool isLoad() const { return staticInst->isLoad(); } 483 bool isStore() const { return staticInst->isStore(); } 484 bool isStoreConditional() const 485 { return staticInst->isStoreConditional(); } 486 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 487 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 488 bool isInteger() const { return staticInst->isInteger(); } 489 bool isFloating() const { return staticInst->isFloating(); } 490 bool isControl() const { return staticInst->isControl(); } 491 bool isCall() const { return staticInst->isCall(); } 492 bool isReturn() const { return staticInst->isReturn(); } 493 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 494 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 495 bool isCondCtrl() const { return staticInst->isCondCtrl(); } 496 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 497 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 498 bool isThreadSync() const { return staticInst->isThreadSync(); } 499 bool isSerializing() const { return staticInst->isSerializing(); } 500 bool isSerializeBefore() const 501 { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 502 bool isSerializeAfter() const 503 { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 504 bool isSquashAfter() const { return staticInst->isSquashAfter(); } 505 bool isMemBarrier() const { return staticInst->isMemBarrier(); } 506 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 507 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 508 bool isQuiesce() const { return staticInst->isQuiesce(); } 509 bool isIprAccess() const { return staticInst->isIprAccess(); } 510 bool isUnverifiable() const { return staticInst->isUnverifiable(); } 511 bool isSyscall() const { return staticInst->isSyscall(); } 512 bool isMacroop() const { return staticInst->isMacroop(); } 513 bool isMicroop() const { return staticInst->isMicroop(); } 514 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 515 bool isLastMicroop() const { return staticInst->isLastMicroop(); } 516 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 517 bool isMicroBranch() const { return staticInst->isMicroBranch(); } 518 519 /** Temporarily sets this instruction as a serialize before instruction. */ 520 void setSerializeBefore() { status.set(SerializeBefore); } 521 522 /** Clears the serializeBefore part of this instruction. */ 523 void clearSerializeBefore() { status.reset(SerializeBefore); } 524 525 /** Checks if this serializeBefore is only temporarily set. */ 526 bool isTempSerializeBefore() { return status[SerializeBefore]; } 527 528 /** Temporarily sets this instruction as a serialize after instruction. */ 529 void setSerializeAfter() { status.set(SerializeAfter); } 530 531 /** Clears the serializeAfter part of this instruction.*/ 532 void clearSerializeAfter() { status.reset(SerializeAfter); } 533 534 /** Checks if this serializeAfter is only temporarily set. */ 535 bool isTempSerializeAfter() { return status[SerializeAfter]; } 536 537 /** Sets the serialization part of this instruction as handled. */ 538 void setSerializeHandled() { status.set(SerializeHandled); } 539 540 /** Checks if the serialization part of this instruction has been 541 * handled. This does not apply to the temporary serializing 542 * state; it only applies to this instruction's own permanent 543 * serializing state. 544 */ 545 bool isSerializeHandled() { return status[SerializeHandled]; } 546 547 /** Returns the opclass of this instruction. */ 548 OpClass opClass() const { return staticInst->opClass(); } 549 550 /** Returns the branch target address. */ 551 TheISA::PCState branchTarget() const 552 { return staticInst->branchTarget(pc); } 553 554 /** Returns the number of source registers. */ 555 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 556 557 /** Returns the number of destination registers. */ 558 int8_t numDestRegs() const { return staticInst->numDestRegs(); } 559 560 // the following are used to track physical register usage 561 // for machines with separate int & FP reg files 562 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 563 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 564 565 /** Returns the logical register index of the i'th destination register. */ 566 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 567 568 /** Returns the logical register index of the i'th source register. */ 569 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 570 571 /** Pops a result off the instResult queue */ 572 template <class T> 573 void popResult(T& t) 574 { 575 if (!instResult.empty()) { 576 instResult.front().get(t); 577 instResult.pop(); 578 } 579 } 580 581 /** Read the most recent result stored by this instruction */ 582 template <class T> 583 void readResult(T& t) 584 { 585 instResult.back().get(t); 586 } 587 588 /** Pushes a result onto the instResult queue */ 589 template <class T> 590 void setResult(T t) 591 { 592 if (recordResult) { 593 Result instRes; 594 instRes.set(t); 595 instResult.push(instRes); 596 } 597 } 598 599 /** Records an integer register being set to a value. */ 600 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 601 { 602 setResult<uint64_t>(val); 603 } 604 605 /** Records an fp register being set to a value. */ 606 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 607 int width) 608 { 609 if (width == 32 || width == 64) { 610 setResult<double>(val); 611 } else { 612 panic("Unsupported width!"); 613 } 614 } 615 616 /** Records an fp register being set to a value. */ 617 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 618 { 619 setResult<double>(val); 620 } 621 622 /** Records an fp register being set to an integer value. */ 623 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val, 624 int width) 625 { 626 setResult<uint64_t>(val); 627 } 628 629 /** Records an fp register being set to an integer value. */ 630 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val) 631 { 632 setResult<uint64_t>(val); 633 } 634 635 /** Records that one of the source registers is ready. */ 636 void markSrcRegReady(); 637 638 /** Marks a specific register as ready. */ 639 void markSrcRegReady(RegIndex src_idx); 640 641 /** Returns if a source register is ready. */ 642 bool isReadySrcRegIdx(int idx) const 643 { 644 return this->_readySrcRegIdx[idx]; 645 } 646 647 /** Sets this instruction as completed. */ 648 void setCompleted() { status.set(Completed); } 649 650 /** Returns whether or not this instruction is completed. */ 651 bool isCompleted() const { return status[Completed]; } 652 653 /** Marks the result as ready. */ 654 void setResultReady() { status.set(ResultReady); } 655 656 /** Returns whether or not the result is ready. */ 657 bool isResultReady() const { return status[ResultReady]; } 658 659 /** Sets this instruction as ready to issue. */ 660 void setCanIssue() { status.set(CanIssue); } 661 662 /** Returns whether or not this instruction is ready to issue. */ 663 bool readyToIssue() const { return status[CanIssue]; } 664 665 /** Clears this instruction being able to issue. */ 666 void clearCanIssue() { status.reset(CanIssue); } 667 668 /** Sets this instruction as issued from the IQ. */ 669 void setIssued() { status.set(Issued); } 670 671 /** Returns whether or not this instruction has issued. */ 672 bool isIssued() const { return status[Issued]; } 673 674 /** Clears this instruction as being issued. */ 675 void clearIssued() { status.reset(Issued); } 676 677 /** Sets this instruction as executed. */ 678 void setExecuted() { status.set(Executed); } 679 680 /** Returns whether or not this instruction has executed. */ 681 bool isExecuted() const { return status[Executed]; } 682 683 /** Sets this instruction as ready to commit. */ 684 void setCanCommit() { status.set(CanCommit); } 685 686 /** Clears this instruction as being ready to commit. */ 687 void clearCanCommit() { status.reset(CanCommit); } 688 689 /** Returns whether or not this instruction is ready to commit. */ 690 bool readyToCommit() const { return status[CanCommit]; } 691 692 void setAtCommit() { status.set(AtCommit); } 693 694 bool isAtCommit() { return status[AtCommit]; } 695 696 /** Sets this instruction as committed. */ 697 void setCommitted() { status.set(Committed); } 698 699 /** Returns whether or not this instruction is committed. */ 700 bool isCommitted() const { return status[Committed]; } 701 702 /** Sets this instruction as squashed. */ 703 void setSquashed() { status.set(Squashed); } 704 705 /** Returns whether or not this instruction is squashed. */ 706 bool isSquashed() const { return status[Squashed]; } 707 708 //Instruction Queue Entry 709 //----------------------- 710 /** Sets this instruction as a entry the IQ. */ 711 void setInIQ() { status.set(IqEntry); } 712 713 /** Sets this instruction as a entry the IQ. */ 714 void clearInIQ() { status.reset(IqEntry); } 715 716 /** Returns whether or not this instruction has issued. */ 717 bool isInIQ() const { return status[IqEntry]; } 718 719 /** Sets this instruction as squashed in the IQ. */ 720 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 721 722 /** Returns whether or not this instruction is squashed in the IQ. */ 723 bool isSquashedInIQ() const { return status[SquashedInIQ]; } 724 725 726 //Load / Store Queue Functions 727 //----------------------- 728 /** Sets this instruction as a entry the LSQ. */ 729 void setInLSQ() { status.set(LsqEntry); } 730 731 /** Sets this instruction as a entry the LSQ. */ 732 void removeInLSQ() { status.reset(LsqEntry); } 733 734 /** Returns whether or not this instruction is in the LSQ. */ 735 bool isInLSQ() const { return status[LsqEntry]; } 736 737 /** Sets this instruction as squashed in the LSQ. */ 738 void setSquashedInLSQ() { status.set(SquashedInLSQ);} 739 740 /** Returns whether or not this instruction is squashed in the LSQ. */ 741 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 742 743 744 //Reorder Buffer Functions 745 //----------------------- 746 /** Sets this instruction as a entry the ROB. */ 747 void setInROB() { status.set(RobEntry); } 748 749 /** Sets this instruction as a entry the ROB. */ 750 void clearInROB() { status.reset(RobEntry); } 751 752 /** Returns whether or not this instruction is in the ROB. */ 753 bool isInROB() const { return status[RobEntry]; } 754 755 /** Sets this instruction as squashed in the ROB. */ 756 void setSquashedInROB() { status.set(SquashedInROB); } 757 758 /** Returns whether or not this instruction is squashed in the ROB. */ 759 bool isSquashedInROB() const { return status[SquashedInROB]; } 760 761 /** Read the PC state of this instruction. */ 762 const TheISA::PCState pcState() const { return pc; } 763 764 /** Set the PC state of this instruction. */ 765 const void pcState(const TheISA::PCState &val) { pc = val; } 766 767 /** Read the PC of this instruction. */ 768 const Addr instAddr() const { return pc.instAddr(); } 769 770 /** Read the PC of the next instruction. */ 771 const Addr nextInstAddr() const { return pc.nextInstAddr(); } 772 773 /**Read the micro PC of this instruction. */ 774 const Addr microPC() const { return pc.microPC(); } 775 776 bool readPredicate() 777 { 778 return predicate; 779 } 780 781 void setPredicate(bool val) 782 { 783 predicate = val; 784 785 if (traceData) { 786 traceData->setPredicate(val); 787 } 788 } 789 790 /** Sets the ASID. */ 791 void setASID(short addr_space_id) { asid = addr_space_id; } 792 793 /** Sets the thread id. */ 794 void setTid(ThreadID tid) { threadNumber = tid; } 795 796 /** Sets the pointer to the thread state. */ 797 void setThreadState(ImplState *state) { thread = state; } 798 799 /** Returns the thread context. */ 800 ThreadContext *tcBase() { return thread->getTC(); } 801 802 private: 803 /** Instruction effective address. 804 * @todo: Consider if this is necessary or not. 805 */ 806 Addr instEffAddr; 807 808 /** Whether or not the effective address calculation is completed. 809 * @todo: Consider if this is necessary or not. 810 */ 811 bool eaCalcDone; 812 813 /** Is this instruction's memory access uncacheable. */ 814 bool isUncacheable; 815 816 /** Has this instruction generated a memory request. */ 817 bool reqMade; 818 819 public: 820 /** Sets the effective address. */ 821 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 822 823 /** Returns the effective address. */ 824 const Addr &getEA() const { return instEffAddr; } 825 826 /** Returns whether or not the eff. addr. calculation has been completed. */ 827 bool doneEACalc() { return eaCalcDone; } 828 829 /** Returns whether or not the eff. addr. source registers are ready. */ 830 bool eaSrcsReady(); 831 832 /** Whether or not the memory operation is done. */ 833 bool memOpDone; 834 835 /** Is this instruction's memory access uncacheable. */ 836 bool uncacheable() { return isUncacheable; } 837 838 /** Has this instruction generated a memory request. */ 839 bool hasRequest() { return reqMade; } 840 841 public: 842 /** Load queue index. */ 843 int16_t lqIdx; 844 845 /** Store queue index. */ 846 int16_t sqIdx; 847 848 /** Iterator pointing to this BaseDynInst in the list of all insts. */ 849 ListIt instListIt; 850 851 /** Returns iterator to this instruction in the list of all insts. */ 852 ListIt &getInstListIt() { return instListIt; } 853 854 /** Sets iterator for this instruction in the list of all insts. */ 855 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 856 857 public: 858 /** Returns the number of consecutive store conditional failures. */ 859 unsigned readStCondFailures() 860 { return thread->storeCondFailures; } 861 862 /** Sets the number of consecutive store conditional failures. */ 863 void setStCondFailures(unsigned sc_failures) 864 { thread->storeCondFailures = sc_failures; } 865}; 866 867template<class Impl> 868Fault 869BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data, 870 unsigned size, unsigned flags) 871{ 872 reqMade = true; 873 Request *req = NULL; 874 Request *sreqLow = NULL; 875 Request *sreqHigh = NULL; 876 877 if (reqMade && translationStarted) { 878 req = savedReq; 879 sreqLow = savedSreqLow; 880 sreqHigh = savedSreqHigh; 881 } else { 882 req = new Request(asid, addr, size, flags, this->pc.instAddr(), 883 thread->contextId(), threadNumber); 884 885 // Only split the request if the ISA supports unaligned accesses. 886 if (TheISA::HasUnalignedMemAcc) { 887 splitRequest(req, sreqLow, sreqHigh); 888 } 889 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read); 890 } 891 892 if (translationCompleted) { 893 if (fault == NoFault) { 894 effAddr = req->getVaddr(); 895 effSize = size; 896 effAddrValid = true; 897#if USE_CHECKER 898 if (reqToVerify != NULL) { 899 delete reqToVerify; 900 } 901 reqToVerify = new Request(*req); 902#endif //USE_CHECKER 903 fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx); 904 } else { 905 // Commit will have to clean up whatever happened. Set this 906 // instruction as executed. 907 this->setExecuted(); 908 } 909 910 if (fault != NoFault) { 911 // Return a fixed value to keep simulation deterministic even 912 // along misspeculated paths. 913 if (data) 914 bzero(data, size); 915 } 916 } 917 918 if (traceData) { 919 traceData->setAddr(addr); 920 } 921 922 return fault; 923} 924 925template<class Impl> 926Fault 927BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, 928 Addr addr, unsigned flags, uint64_t *res) 929{ 930 if (traceData) { 931 traceData->setAddr(addr); 932 } 933 934 reqMade = true; 935 Request *req = NULL; 936 Request *sreqLow = NULL; 937 Request *sreqHigh = NULL; 938 939 if (reqMade && translationStarted) { 940 req = savedReq; 941 sreqLow = savedSreqLow; 942 sreqHigh = savedSreqHigh; 943 } else { 944 req = new Request(asid, addr, size, flags, this->pc.instAddr(), 945 thread->contextId(), threadNumber); 946 947 // Only split the request if the ISA supports unaligned accesses. 948 if (TheISA::HasUnalignedMemAcc) { 949 splitRequest(req, sreqLow, sreqHigh); 950 } 951 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write); 952 } 953 954 if (fault == NoFault && translationCompleted) { 955 effAddr = req->getVaddr(); 956 effSize = size; 957 effAddrValid = true; 958#if USE_CHECKER 959 if (reqToVerify != NULL) { 960 delete reqToVerify; 961 } 962 reqToVerify = new Request(*req); 963#endif // USE_CHECKER 964 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx); 965 } 966 967 return fault; 968} 969 970template<class Impl> 971inline void 972BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow, 973 RequestPtr &sreqHigh) 974{ 975 // Check to see if the request crosses the next level block boundary. 976 unsigned block_size = cpu->getDcachePort()->peerBlockSize(); 977 Addr addr = req->getVaddr(); 978 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size); 979 assert(split_addr <= addr || split_addr - addr < block_size); 980 981 // Spans two blocks. 982 if (split_addr > addr) { 983 req->splitOnVaddr(split_addr, sreqLow, sreqHigh); 984 } 985} 986 987template<class Impl> 988inline void 989BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow, 990 RequestPtr sreqHigh, uint64_t *res, 991 BaseTLB::Mode mode) 992{ 993 translationStarted = true; 994 995 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) { 996 WholeTranslationState *state = 997 new WholeTranslationState(req, NULL, res, mode); 998 999 // One translation if the request isn't split. 1000 DataTranslation<BaseDynInstPtr> *trans = 1001 new DataTranslation<BaseDynInstPtr>(this, state); 1002 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode); 1003 if (!translationCompleted) { 1004 // Save memory requests. 1005 savedReq = state->mainReq; 1006 savedSreqLow = state->sreqLow; 1007 savedSreqHigh = state->sreqHigh; 1008 } 1009 } else { 1010 WholeTranslationState *state = 1011 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode); 1012 1013 // Two translations when the request is split. 1014 DataTranslation<BaseDynInstPtr> *stransLow = 1015 new DataTranslation<BaseDynInstPtr>(this, state, 0); 1016 DataTranslation<BaseDynInstPtr> *stransHigh = 1017 new DataTranslation<BaseDynInstPtr>(this, state, 1); 1018 1019 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode); 1020 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode); 1021 if (!translationCompleted) { 1022 // Save memory requests. 1023 savedReq = state->mainReq; 1024 savedSreqLow = state->sreqLow; 1025 savedSreqHigh = state->sreqHigh; 1026 } 1027 } 1028} 1029 1030template<class Impl> 1031inline void 1032BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state) 1033{ 1034 fault = state->getFault(); 1035 1036 if (state->isUncacheable()) 1037 isUncacheable = true; 1038 1039 if (fault == NoFault) { 1040 physEffAddr = state->getPaddr(); 1041 memReqFlags = state->getFlags(); 1042 1043 if (state->mainReq->isCondSwap()) { 1044 assert(state->res); 1045 state->mainReq->setExtraData(*state->res); 1046 } 1047 1048 } else { 1049 state->deleteReqs(); 1050 } 1051 delete state; 1052 1053 translationCompleted = true; 1054} 1055 1056#endif // __CPU_BASE_DYN_INST_HH__ 1057