base_dyn_inst.hh revision 8444
11060SN/A/* 27944SGiacomo.Gabrielli@arm.com * Copyright (c) 2011 ARM Limited 37944SGiacomo.Gabrielli@arm.com * All rights reserved. 47944SGiacomo.Gabrielli@arm.com * 57944SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 67944SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 77944SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 87944SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 97944SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 107944SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 117944SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 127944SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 137944SGiacomo.Gabrielli@arm.com * 142702Sktlim@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 156973Stjones1@inf.ed.ac.uk * Copyright (c) 2009 The University of Edinburgh 161060SN/A * All rights reserved. 171060SN/A * 181060SN/A * Redistribution and use in source and binary forms, with or without 191060SN/A * modification, are permitted provided that the following conditions are 201060SN/A * met: redistributions of source code must retain the above copyright 211060SN/A * notice, this list of conditions and the following disclaimer; 221060SN/A * redistributions in binary form must reproduce the above copyright 231060SN/A * notice, this list of conditions and the following disclaimer in the 241060SN/A * documentation and/or other materials provided with the distribution; 251060SN/A * neither the name of the copyright holders nor the names of its 261060SN/A * contributors may be used to endorse or promote products derived from 271060SN/A * this software without specific prior written permission. 281060SN/A * 291060SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301060SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311060SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321060SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341060SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351060SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371060SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381060SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391060SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 426973Stjones1@inf.ed.ac.uk * Timothy M. Jones 431060SN/A */ 441060SN/A 451464SN/A#ifndef __CPU_BASE_DYN_INST_HH__ 461464SN/A#define __CPU_BASE_DYN_INST_HH__ 471060SN/A 482731Sktlim@umich.edu#include <bitset> 492292SN/A#include <list> 501464SN/A#include <string> 511060SN/A 522669Sktlim@umich.edu#include "arch/faults.hh" 537720Sgblack@eecs.umich.edu#include "arch/utility.hh" 541060SN/A#include "base/fast_alloc.hh" 551060SN/A#include "base/trace.hh" 561858SN/A#include "config/full_system.hh" 576658Snate@binkert.org#include "config/the_isa.hh" 583770Sgblack@eecs.umich.edu#include "cpu/o3/comm.hh" 591464SN/A#include "cpu/exetrace.hh" 601464SN/A#include "cpu/inst_seq.hh" 612669Sktlim@umich.edu#include "cpu/op_class.hh" 621060SN/A#include "cpu/static_inst.hh" 636973Stjones1@inf.ed.ac.uk#include "cpu/translation.hh" 642669Sktlim@umich.edu#include "mem/packet.hh" 657678Sgblack@eecs.umich.edu#include "sim/byteswap.hh" 662292SN/A#include "sim/system.hh" 676023Snate@binkert.org#include "sim/tlb.hh" 681060SN/A 691060SN/A/** 701060SN/A * @file 711060SN/A * Defines a dynamic instruction context. 721060SN/A */ 731060SN/A 741061SN/A// Forward declaration. 751061SN/Aclass StaticInstPtr; 761060SN/A 771060SN/Atemplate <class Impl> 781061SN/Aclass BaseDynInst : public FastAlloc, public RefCounted 791060SN/A{ 801060SN/A public: 811060SN/A // Typedef for the CPU. 822733Sktlim@umich.edu typedef typename Impl::CPUType ImplCPU; 832733Sktlim@umich.edu typedef typename ImplCPU::ImplState ImplState; 841060SN/A 852292SN/A // Logical register index type. 862107SN/A typedef TheISA::RegIndex RegIndex; 872690Sktlim@umich.edu // Integer register type. 882107SN/A typedef TheISA::IntReg IntReg; 892690Sktlim@umich.edu // Floating point register type. 902690Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 911060SN/A 922292SN/A // The DynInstPtr type. 932292SN/A typedef typename Impl::DynInstPtr DynInstPtr; 942292SN/A 952292SN/A // The list of instructions iterator type. 962292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 972292SN/A 981060SN/A enum { 995543Ssaidi@eecs.umich.edu MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 1005543Ssaidi@eecs.umich.edu MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs 1011060SN/A }; 1021060SN/A 1032292SN/A /** The StaticInst used by this BaseDynInst. */ 1042107SN/A StaticInstPtr staticInst; 1051060SN/A 1061060SN/A //////////////////////////////////////////// 1071060SN/A // 1081060SN/A // INSTRUCTION EXECUTION 1091060SN/A // 1101060SN/A //////////////////////////////////////////// 1112292SN/A /** InstRecord that tracks this instructions. */ 1121060SN/A Trace::InstRecord *traceData; 1131060SN/A 1145358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 1155358Sgblack@eecs.umich.edu { 1165358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 1175358Sgblack@eecs.umich.edu } 1185358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 1195358Sgblack@eecs.umich.edu { 1205358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 1215358Sgblack@eecs.umich.edu } 1225358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 1235358Sgblack@eecs.umich.edu { 1245358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 1255358Sgblack@eecs.umich.edu } 1265358Sgblack@eecs.umich.edu 1278444Sgblack@eecs.umich.edu Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); 1287520Sgblack@eecs.umich.edu 1298444Sgblack@eecs.umich.edu Fault writeMem(uint8_t *data, unsigned size, 1308444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res); 1317520Sgblack@eecs.umich.edu 1326974Stjones1@inf.ed.ac.uk /** Splits a request in two if it crosses a dcache block. */ 1336974Stjones1@inf.ed.ac.uk void splitRequest(RequestPtr req, RequestPtr &sreqLow, 1346974Stjones1@inf.ed.ac.uk RequestPtr &sreqHigh); 1356974Stjones1@inf.ed.ac.uk 1366973Stjones1@inf.ed.ac.uk /** Initiate a DTB address translation. */ 1376974Stjones1@inf.ed.ac.uk void initiateTranslation(RequestPtr req, RequestPtr sreqLow, 1386974Stjones1@inf.ed.ac.uk RequestPtr sreqHigh, uint64_t *res, 1396973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode); 1406973Stjones1@inf.ed.ac.uk 1416973Stjones1@inf.ed.ac.uk /** Finish a DTB address translation. */ 1426973Stjones1@inf.ed.ac.uk void finishTranslation(WholeTranslationState *state); 1431060SN/A 1447944SGiacomo.Gabrielli@arm.com /** True if the DTB address translation has started. */ 1457944SGiacomo.Gabrielli@arm.com bool translationStarted; 1467944SGiacomo.Gabrielli@arm.com 1477944SGiacomo.Gabrielli@arm.com /** True if the DTB address translation has completed. */ 1487944SGiacomo.Gabrielli@arm.com bool translationCompleted; 1497944SGiacomo.Gabrielli@arm.com 1507944SGiacomo.Gabrielli@arm.com /** 1517944SGiacomo.Gabrielli@arm.com * Returns true if the DTB address translation is being delayed due to a hw 1527944SGiacomo.Gabrielli@arm.com * page table walk. 1537944SGiacomo.Gabrielli@arm.com */ 1547944SGiacomo.Gabrielli@arm.com bool isTranslationDelayed() const 1557944SGiacomo.Gabrielli@arm.com { 1567944SGiacomo.Gabrielli@arm.com return (translationStarted && !translationCompleted); 1577944SGiacomo.Gabrielli@arm.com } 1587944SGiacomo.Gabrielli@arm.com 1597944SGiacomo.Gabrielli@arm.com /** 1607944SGiacomo.Gabrielli@arm.com * Saved memory requests (needed when the DTB address translation is 1617944SGiacomo.Gabrielli@arm.com * delayed due to a hw page table walk). 1627944SGiacomo.Gabrielli@arm.com */ 1637944SGiacomo.Gabrielli@arm.com RequestPtr savedReq; 1647944SGiacomo.Gabrielli@arm.com RequestPtr savedSreqLow; 1657944SGiacomo.Gabrielli@arm.com RequestPtr savedSreqHigh; 1667944SGiacomo.Gabrielli@arm.com 1671684SN/A /** @todo: Consider making this private. */ 1681060SN/A public: 1691060SN/A /** The sequence number of the instruction. */ 1701060SN/A InstSeqNum seqNum; 1711060SN/A 1722731Sktlim@umich.edu enum Status { 1732731Sktlim@umich.edu IqEntry, /// Instruction is in the IQ 1742731Sktlim@umich.edu RobEntry, /// Instruction is in the ROB 1752731Sktlim@umich.edu LsqEntry, /// Instruction is in the LSQ 1762731Sktlim@umich.edu Completed, /// Instruction has completed 1772731Sktlim@umich.edu ResultReady, /// Instruction has its result 1782731Sktlim@umich.edu CanIssue, /// Instruction can issue and execute 1792731Sktlim@umich.edu Issued, /// Instruction has issued 1802731Sktlim@umich.edu Executed, /// Instruction has executed 1812731Sktlim@umich.edu CanCommit, /// Instruction can commit 1822731Sktlim@umich.edu AtCommit, /// Instruction has reached commit 1832731Sktlim@umich.edu Committed, /// Instruction has committed 1842731Sktlim@umich.edu Squashed, /// Instruction is squashed 1852731Sktlim@umich.edu SquashedInIQ, /// Instruction is squashed in the IQ 1862731Sktlim@umich.edu SquashedInLSQ, /// Instruction is squashed in the LSQ 1872731Sktlim@umich.edu SquashedInROB, /// Instruction is squashed in the ROB 1882731Sktlim@umich.edu RecoverInst, /// Is a recover instruction 1892731Sktlim@umich.edu BlockingInst, /// Is a blocking instruction 1902731Sktlim@umich.edu ThreadsyncWait, /// Is a thread synchronization instruction 1912731Sktlim@umich.edu SerializeBefore, /// Needs to serialize on 1922731Sktlim@umich.edu /// instructions ahead of it 1932731Sktlim@umich.edu SerializeAfter, /// Needs to serialize instructions behind it 1942731Sktlim@umich.edu SerializeHandled, /// Serialization has been handled 1952731Sktlim@umich.edu NumStatus 1962731Sktlim@umich.edu }; 1972292SN/A 1982731Sktlim@umich.edu /** The status of this BaseDynInst. Several bits can be set. */ 1992731Sktlim@umich.edu std::bitset<NumStatus> status; 2001060SN/A 2011060SN/A /** The thread this instruction is from. */ 2026221Snate@binkert.org ThreadID threadNumber; 2031060SN/A 2041060SN/A /** data address space ID, for loads & stores. */ 2051060SN/A short asid; 2061060SN/A 2072292SN/A /** How many source registers are ready. */ 2082292SN/A unsigned readyRegs; 2092292SN/A 2102733Sktlim@umich.edu /** Pointer to the Impl's CPU object. */ 2112733Sktlim@umich.edu ImplCPU *cpu; 2121060SN/A 2132680Sktlim@umich.edu /** Pointer to the thread state. */ 2142292SN/A ImplState *thread; 2151060SN/A 2161060SN/A /** The kind of fault this instruction has generated. */ 2172132SN/A Fault fault; 2181060SN/A 2192702Sktlim@umich.edu /** Pointer to the data for the memory access. */ 2202669Sktlim@umich.edu uint8_t *memData; 2212292SN/A 2221060SN/A /** The effective virtual address (lds & stores only). */ 2231060SN/A Addr effAddr; 2241060SN/A 2258199SAli.Saidi@ARM.com /** The size of the request */ 2268199SAli.Saidi@ARM.com Addr effSize; 2278199SAli.Saidi@ARM.com 2284032Sktlim@umich.edu /** Is the effective virtual address valid. */ 2294032Sktlim@umich.edu bool effAddrValid; 2304032Sktlim@umich.edu 2311060SN/A /** The effective physical address. */ 2321060SN/A Addr physEffAddr; 2331060SN/A 2341060SN/A /** The memory request flags (from translation). */ 2351060SN/A unsigned memReqFlags; 2361060SN/A 2371464SN/A union Result { 2381464SN/A uint64_t integer; 2392356SN/A// float fp; 2401464SN/A double dbl; 2411464SN/A }; 2421060SN/A 2431464SN/A /** The result of the instruction; assumes for now that there's only one 2441464SN/A * destination register. 2451464SN/A */ 2461464SN/A Result instResult; 2471060SN/A 2483326Sktlim@umich.edu /** Records changes to result? */ 2493326Sktlim@umich.edu bool recordResult; 2503326Sktlim@umich.edu 2517597Sminkyu.jeong@arm.com /** Did this instruction execute, or is it predicated false */ 2527597Sminkyu.jeong@arm.com bool predicate; 2537597Sminkyu.jeong@arm.com 2543965Sgblack@eecs.umich.edu protected: 2557720Sgblack@eecs.umich.edu /** PC state for this instruction. */ 2567720Sgblack@eecs.umich.edu TheISA::PCState pc; 2571060SN/A 2587720Sgblack@eecs.umich.edu /** Predicted PC state after this instruction. */ 2597720Sgblack@eecs.umich.edu TheISA::PCState predPC; 2604636Sgblack@eecs.umich.edu 2613794Sgblack@eecs.umich.edu /** If this is a branch that was predicted taken */ 2623794Sgblack@eecs.umich.edu bool predTaken; 2633794Sgblack@eecs.umich.edu 2643965Sgblack@eecs.umich.edu public: 2653965Sgblack@eecs.umich.edu 2662292SN/A#ifdef DEBUG 2672292SN/A void dumpSNList(); 2682292SN/A#endif 2692292SN/A 2702292SN/A /** Whether or not the source register is ready. 2712292SN/A * @todo: Not sure this should be here vs the derived class. 2721060SN/A */ 2731060SN/A bool _readySrcRegIdx[MaxInstSrcRegs]; 2741060SN/A 2753770Sgblack@eecs.umich.edu protected: 2763770Sgblack@eecs.umich.edu /** Flattened register index of the destination registers of this 2773770Sgblack@eecs.umich.edu * instruction. 2783770Sgblack@eecs.umich.edu */ 2793770Sgblack@eecs.umich.edu TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs]; 2803770Sgblack@eecs.umich.edu 2813770Sgblack@eecs.umich.edu /** Flattened register index of the source registers of this 2823770Sgblack@eecs.umich.edu * instruction. 2833770Sgblack@eecs.umich.edu */ 2843770Sgblack@eecs.umich.edu TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs]; 2853770Sgblack@eecs.umich.edu 2863770Sgblack@eecs.umich.edu /** Physical register index of the destination registers of this 2873770Sgblack@eecs.umich.edu * instruction. 2883770Sgblack@eecs.umich.edu */ 2893770Sgblack@eecs.umich.edu PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs]; 2903770Sgblack@eecs.umich.edu 2913770Sgblack@eecs.umich.edu /** Physical register index of the source registers of this 2923770Sgblack@eecs.umich.edu * instruction. 2933770Sgblack@eecs.umich.edu */ 2943770Sgblack@eecs.umich.edu PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs]; 2953770Sgblack@eecs.umich.edu 2963770Sgblack@eecs.umich.edu /** Physical register index of the previous producers of the 2973770Sgblack@eecs.umich.edu * architected destinations. 2983770Sgblack@eecs.umich.edu */ 2993770Sgblack@eecs.umich.edu PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs]; 3003770Sgblack@eecs.umich.edu 3011060SN/A public: 3023770Sgblack@eecs.umich.edu 3033770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th destination 3043770Sgblack@eecs.umich.edu * register. 3053770Sgblack@eecs.umich.edu */ 3063770Sgblack@eecs.umich.edu PhysRegIndex renamedDestRegIdx(int idx) const 3073770Sgblack@eecs.umich.edu { 3083770Sgblack@eecs.umich.edu return _destRegIdx[idx]; 3093770Sgblack@eecs.umich.edu } 3103770Sgblack@eecs.umich.edu 3113770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th source register. */ 3123770Sgblack@eecs.umich.edu PhysRegIndex renamedSrcRegIdx(int idx) const 3133770Sgblack@eecs.umich.edu { 3143770Sgblack@eecs.umich.edu return _srcRegIdx[idx]; 3153770Sgblack@eecs.umich.edu } 3163770Sgblack@eecs.umich.edu 3173770Sgblack@eecs.umich.edu /** Returns the flattened register index of the i'th destination 3183770Sgblack@eecs.umich.edu * register. 3193770Sgblack@eecs.umich.edu */ 3203770Sgblack@eecs.umich.edu TheISA::RegIndex flattenedDestRegIdx(int idx) const 3213770Sgblack@eecs.umich.edu { 3223770Sgblack@eecs.umich.edu return _flatDestRegIdx[idx]; 3233770Sgblack@eecs.umich.edu } 3243770Sgblack@eecs.umich.edu 3253770Sgblack@eecs.umich.edu /** Returns the flattened register index of the i'th source register */ 3263770Sgblack@eecs.umich.edu TheISA::RegIndex flattenedSrcRegIdx(int idx) const 3273770Sgblack@eecs.umich.edu { 3283770Sgblack@eecs.umich.edu return _flatSrcRegIdx[idx]; 3293770Sgblack@eecs.umich.edu } 3303770Sgblack@eecs.umich.edu 3313770Sgblack@eecs.umich.edu /** Returns the physical register index of the previous physical register 3323770Sgblack@eecs.umich.edu * that remapped to the same logical register index. 3333770Sgblack@eecs.umich.edu */ 3343770Sgblack@eecs.umich.edu PhysRegIndex prevDestRegIdx(int idx) const 3353770Sgblack@eecs.umich.edu { 3363770Sgblack@eecs.umich.edu return _prevDestRegIdx[idx]; 3373770Sgblack@eecs.umich.edu } 3383770Sgblack@eecs.umich.edu 3393770Sgblack@eecs.umich.edu /** Renames a destination register to a physical register. Also records 3403770Sgblack@eecs.umich.edu * the previous physical register that the logical register mapped to. 3413770Sgblack@eecs.umich.edu */ 3423770Sgblack@eecs.umich.edu void renameDestReg(int idx, 3433770Sgblack@eecs.umich.edu PhysRegIndex renamed_dest, 3443770Sgblack@eecs.umich.edu PhysRegIndex previous_rename) 3453770Sgblack@eecs.umich.edu { 3463770Sgblack@eecs.umich.edu _destRegIdx[idx] = renamed_dest; 3473770Sgblack@eecs.umich.edu _prevDestRegIdx[idx] = previous_rename; 3483770Sgblack@eecs.umich.edu } 3493770Sgblack@eecs.umich.edu 3503770Sgblack@eecs.umich.edu /** Renames a source logical register to the physical register which 3513770Sgblack@eecs.umich.edu * has/will produce that logical register's result. 3523770Sgblack@eecs.umich.edu * @todo: add in whether or not the source register is ready. 3533770Sgblack@eecs.umich.edu */ 3543770Sgblack@eecs.umich.edu void renameSrcReg(int idx, PhysRegIndex renamed_src) 3553770Sgblack@eecs.umich.edu { 3563770Sgblack@eecs.umich.edu _srcRegIdx[idx] = renamed_src; 3573770Sgblack@eecs.umich.edu } 3583770Sgblack@eecs.umich.edu 3593770Sgblack@eecs.umich.edu /** Flattens a source architectural register index into a logical index. 3603770Sgblack@eecs.umich.edu */ 3613770Sgblack@eecs.umich.edu void flattenSrcReg(int idx, TheISA::RegIndex flattened_src) 3623770Sgblack@eecs.umich.edu { 3633770Sgblack@eecs.umich.edu _flatSrcRegIdx[idx] = flattened_src; 3643770Sgblack@eecs.umich.edu } 3653770Sgblack@eecs.umich.edu 3663770Sgblack@eecs.umich.edu /** Flattens a destination architectural register index into a logical 3673770Sgblack@eecs.umich.edu * index. 3683770Sgblack@eecs.umich.edu */ 3693770Sgblack@eecs.umich.edu void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 3703770Sgblack@eecs.umich.edu { 3713770Sgblack@eecs.umich.edu _flatDestRegIdx[idx] = flattened_dest; 3723770Sgblack@eecs.umich.edu } 3734636Sgblack@eecs.umich.edu /** BaseDynInst constructor given a binary instruction. 3744636Sgblack@eecs.umich.edu * @param staticInst A StaticInstPtr to the underlying instruction. 3757720Sgblack@eecs.umich.edu * @param pc The PC state for the instruction. 3767720Sgblack@eecs.umich.edu * @param predPC The predicted next PC state for the instruction. 3774636Sgblack@eecs.umich.edu * @param seq_num The sequence number of the instruction. 3784636Sgblack@eecs.umich.edu * @param cpu Pointer to the instruction's CPU. 3794636Sgblack@eecs.umich.edu */ 3807720Sgblack@eecs.umich.edu BaseDynInst(StaticInstPtr staticInst, TheISA::PCState pc, 3817720Sgblack@eecs.umich.edu TheISA::PCState predPC, InstSeqNum seq_num, ImplCPU *cpu); 3823770Sgblack@eecs.umich.edu 3832292SN/A /** BaseDynInst constructor given a binary instruction. 3842292SN/A * @param inst The binary instruction. 3857720Sgblack@eecs.umich.edu * @param _pc The PC state for the instruction. 3867720Sgblack@eecs.umich.edu * @param _predPC The predicted next PC state for the instruction. 3872292SN/A * @param seq_num The sequence number of the instruction. 3882292SN/A * @param cpu Pointer to the instruction's CPU. 3892292SN/A */ 3907720Sgblack@eecs.umich.edu BaseDynInst(TheISA::ExtMachInst inst, TheISA::PCState pc, 3917720Sgblack@eecs.umich.edu TheISA::PCState predPC, InstSeqNum seq_num, ImplCPU *cpu); 3921060SN/A 3932292SN/A /** BaseDynInst constructor given a StaticInst pointer. 3942292SN/A * @param _staticInst The StaticInst for this BaseDynInst. 3952292SN/A */ 3962107SN/A BaseDynInst(StaticInstPtr &_staticInst); 3971060SN/A 3981060SN/A /** BaseDynInst destructor. */ 3991060SN/A ~BaseDynInst(); 4001060SN/A 4011464SN/A private: 4021684SN/A /** Function to initialize variables in the constructors. */ 4031464SN/A void initVars(); 4041060SN/A 4051464SN/A public: 4061060SN/A /** Dumps out contents of this BaseDynInst. */ 4071060SN/A void dump(); 4081060SN/A 4091060SN/A /** Dumps out contents of this BaseDynInst into given string. */ 4101060SN/A void dump(std::string &outstring); 4111060SN/A 4123326Sktlim@umich.edu /** Read this CPU's ID. */ 4135712Shsul@eecs.umich.edu int cpuId() { return cpu->cpuId(); } 4143326Sktlim@umich.edu 4155714Shsul@eecs.umich.edu /** Read this context's system-wide ID **/ 4165714Shsul@eecs.umich.edu int contextId() { return thread->contextId(); } 4175714Shsul@eecs.umich.edu 4181060SN/A /** Returns the fault type. */ 4192132SN/A Fault getFault() { return fault; } 4201060SN/A 4211060SN/A /** Checks whether or not this instruction has had its branch target 4221060SN/A * calculated yet. For now it is not utilized and is hacked to be 4231060SN/A * always false. 4242292SN/A * @todo: Actually use this instruction. 4251060SN/A */ 4261060SN/A bool doneTargCalc() { return false; } 4271060SN/A 4287720Sgblack@eecs.umich.edu /** Set the predicted target of this current instruction. */ 4297720Sgblack@eecs.umich.edu void setPredTarg(const TheISA::PCState &_predPC) 4303965Sgblack@eecs.umich.edu { 4317720Sgblack@eecs.umich.edu predPC = _predPC; 4323965Sgblack@eecs.umich.edu } 4332935Sksewell@umich.edu 4347720Sgblack@eecs.umich.edu const TheISA::PCState &readPredTarg() { return predPC; } 4351060SN/A 4363794Sgblack@eecs.umich.edu /** Returns the predicted PC immediately after the branch. */ 4377720Sgblack@eecs.umich.edu Addr predInstAddr() { return predPC.instAddr(); } 4383794Sgblack@eecs.umich.edu 4393794Sgblack@eecs.umich.edu /** Returns the predicted PC two instructions after the branch */ 4407720Sgblack@eecs.umich.edu Addr predNextInstAddr() { return predPC.nextInstAddr(); } 4411060SN/A 4424636Sgblack@eecs.umich.edu /** Returns the predicted micro PC after the branch */ 4437720Sgblack@eecs.umich.edu Addr predMicroPC() { return predPC.microPC(); } 4444636Sgblack@eecs.umich.edu 4451060SN/A /** Returns whether the instruction was predicted taken or not. */ 4463794Sgblack@eecs.umich.edu bool readPredTaken() 4473794Sgblack@eecs.umich.edu { 4483794Sgblack@eecs.umich.edu return predTaken; 4493794Sgblack@eecs.umich.edu } 4503794Sgblack@eecs.umich.edu 4513794Sgblack@eecs.umich.edu void setPredTaken(bool predicted_taken) 4523794Sgblack@eecs.umich.edu { 4533794Sgblack@eecs.umich.edu predTaken = predicted_taken; 4543794Sgblack@eecs.umich.edu } 4551060SN/A 4561060SN/A /** Returns whether the instruction mispredicted. */ 4572935Sksewell@umich.edu bool mispredicted() 4583794Sgblack@eecs.umich.edu { 4597720Sgblack@eecs.umich.edu TheISA::PCState tempPC = pc; 4607720Sgblack@eecs.umich.edu TheISA::advancePC(tempPC, staticInst); 4617720Sgblack@eecs.umich.edu return !(tempPC == predPC); 4623794Sgblack@eecs.umich.edu } 4633794Sgblack@eecs.umich.edu 4641060SN/A // 4651060SN/A // Instruction types. Forward checks to StaticInst object. 4661060SN/A // 4675543Ssaidi@eecs.umich.edu bool isNop() const { return staticInst->isNop(); } 4685543Ssaidi@eecs.umich.edu bool isMemRef() const { return staticInst->isMemRef(); } 4695543Ssaidi@eecs.umich.edu bool isLoad() const { return staticInst->isLoad(); } 4705543Ssaidi@eecs.umich.edu bool isStore() const { return staticInst->isStore(); } 4712336SN/A bool isStoreConditional() const 4722336SN/A { return staticInst->isStoreConditional(); } 4731060SN/A bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 4741060SN/A bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 4755543Ssaidi@eecs.umich.edu bool isInteger() const { return staticInst->isInteger(); } 4765543Ssaidi@eecs.umich.edu bool isFloating() const { return staticInst->isFloating(); } 4775543Ssaidi@eecs.umich.edu bool isControl() const { return staticInst->isControl(); } 4785543Ssaidi@eecs.umich.edu bool isCall() const { return staticInst->isCall(); } 4795543Ssaidi@eecs.umich.edu bool isReturn() const { return staticInst->isReturn(); } 4805543Ssaidi@eecs.umich.edu bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 4811060SN/A bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 4825543Ssaidi@eecs.umich.edu bool isCondCtrl() const { return staticInst->isCondCtrl(); } 4835543Ssaidi@eecs.umich.edu bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 4842935Sksewell@umich.edu bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 4851060SN/A bool isThreadSync() const { return staticInst->isThreadSync(); } 4861060SN/A bool isSerializing() const { return staticInst->isSerializing(); } 4872292SN/A bool isSerializeBefore() const 4882731Sktlim@umich.edu { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 4892292SN/A bool isSerializeAfter() const 4902731Sktlim@umich.edu { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 4917784SAli.Saidi@ARM.com bool isSquashAfter() const { return staticInst->isSquashAfter(); } 4921060SN/A bool isMemBarrier() const { return staticInst->isMemBarrier(); } 4931060SN/A bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 4941060SN/A bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 4952292SN/A bool isQuiesce() const { return staticInst->isQuiesce(); } 4962336SN/A bool isIprAccess() const { return staticInst->isIprAccess(); } 4972308SN/A bool isUnverifiable() const { return staticInst->isUnverifiable(); } 4984828Sgblack@eecs.umich.edu bool isSyscall() const { return staticInst->isSyscall(); } 4994654Sgblack@eecs.umich.edu bool isMacroop() const { return staticInst->isMacroop(); } 5004654Sgblack@eecs.umich.edu bool isMicroop() const { return staticInst->isMicroop(); } 5014636Sgblack@eecs.umich.edu bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 5024654Sgblack@eecs.umich.edu bool isLastMicroop() const { return staticInst->isLastMicroop(); } 5034654Sgblack@eecs.umich.edu bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 5044636Sgblack@eecs.umich.edu bool isMicroBranch() const { return staticInst->isMicroBranch(); } 5052292SN/A 5062292SN/A /** Temporarily sets this instruction as a serialize before instruction. */ 5072731Sktlim@umich.edu void setSerializeBefore() { status.set(SerializeBefore); } 5082292SN/A 5092292SN/A /** Clears the serializeBefore part of this instruction. */ 5102731Sktlim@umich.edu void clearSerializeBefore() { status.reset(SerializeBefore); } 5112292SN/A 5122292SN/A /** Checks if this serializeBefore is only temporarily set. */ 5132731Sktlim@umich.edu bool isTempSerializeBefore() { return status[SerializeBefore]; } 5142292SN/A 5152292SN/A /** Temporarily sets this instruction as a serialize after instruction. */ 5162731Sktlim@umich.edu void setSerializeAfter() { status.set(SerializeAfter); } 5172292SN/A 5182292SN/A /** Clears the serializeAfter part of this instruction.*/ 5192731Sktlim@umich.edu void clearSerializeAfter() { status.reset(SerializeAfter); } 5202292SN/A 5212292SN/A /** Checks if this serializeAfter is only temporarily set. */ 5222731Sktlim@umich.edu bool isTempSerializeAfter() { return status[SerializeAfter]; } 5232292SN/A 5242731Sktlim@umich.edu /** Sets the serialization part of this instruction as handled. */ 5252731Sktlim@umich.edu void setSerializeHandled() { status.set(SerializeHandled); } 5262292SN/A 5272292SN/A /** Checks if the serialization part of this instruction has been 5282292SN/A * handled. This does not apply to the temporary serializing 5292292SN/A * state; it only applies to this instruction's own permanent 5302292SN/A * serializing state. 5312292SN/A */ 5322731Sktlim@umich.edu bool isSerializeHandled() { return status[SerializeHandled]; } 5331060SN/A 5341464SN/A /** Returns the opclass of this instruction. */ 5351464SN/A OpClass opClass() const { return staticInst->opClass(); } 5361464SN/A 5371464SN/A /** Returns the branch target address. */ 5387720Sgblack@eecs.umich.edu TheISA::PCState branchTarget() const 5397720Sgblack@eecs.umich.edu { return staticInst->branchTarget(pc); } 5401464SN/A 5412292SN/A /** Returns the number of source registers. */ 5425543Ssaidi@eecs.umich.edu int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 5431684SN/A 5442292SN/A /** Returns the number of destination registers. */ 5451060SN/A int8_t numDestRegs() const { return staticInst->numDestRegs(); } 5461060SN/A 5471060SN/A // the following are used to track physical register usage 5481060SN/A // for machines with separate int & FP reg files 5491060SN/A int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 5501060SN/A int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 5511060SN/A 5521060SN/A /** Returns the logical register index of the i'th destination register. */ 5532292SN/A RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 5541060SN/A 5551060SN/A /** Returns the logical register index of the i'th source register. */ 5562292SN/A RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 5571060SN/A 5581684SN/A /** Returns the result of an integer instruction. */ 5591464SN/A uint64_t readIntResult() { return instResult.integer; } 5601684SN/A 5611684SN/A /** Returns the result of a floating point instruction. */ 5622356SN/A float readFloatResult() { return (float)instResult.dbl; } 5631684SN/A 5641684SN/A /** Returns the result of a floating point (double) instruction. */ 5651464SN/A double readDoubleResult() { return instResult.dbl; } 5661060SN/A 5672702Sktlim@umich.edu /** Records an integer register being set to a value. */ 5683735Sstever@eecs.umich.edu void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 5691060SN/A { 5703326Sktlim@umich.edu if (recordResult) 5713326Sktlim@umich.edu instResult.integer = val; 5721060SN/A } 5731060SN/A 5742702Sktlim@umich.edu /** Records an fp register being set to a value. */ 5753735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 5763735Sstever@eecs.umich.edu int width) 5772690Sktlim@umich.edu { 5783326Sktlim@umich.edu if (recordResult) { 5793326Sktlim@umich.edu if (width == 32) 5803326Sktlim@umich.edu instResult.dbl = (double)val; 5813326Sktlim@umich.edu else if (width == 64) 5823326Sktlim@umich.edu instResult.dbl = val; 5833326Sktlim@umich.edu else 5843326Sktlim@umich.edu panic("Unsupported width!"); 5853326Sktlim@umich.edu } 5862690Sktlim@umich.edu } 5872690Sktlim@umich.edu 5882702Sktlim@umich.edu /** Records an fp register being set to a value. */ 5893735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 5901060SN/A { 5913326Sktlim@umich.edu if (recordResult) 5923326Sktlim@umich.edu instResult.dbl = (double)val; 5932308SN/A } 5941060SN/A 5952702Sktlim@umich.edu /** Records an fp register being set to an integer value. */ 5963735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val, 5973735Sstever@eecs.umich.edu int width) 5982308SN/A { 5993326Sktlim@umich.edu if (recordResult) 6003326Sktlim@umich.edu instResult.integer = val; 6012308SN/A } 6021060SN/A 6032702Sktlim@umich.edu /** Records an fp register being set to an integer value. */ 6043735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val) 6052308SN/A { 6063326Sktlim@umich.edu if (recordResult) 6073326Sktlim@umich.edu instResult.integer = val; 6081060SN/A } 6091060SN/A 6102190SN/A /** Records that one of the source registers is ready. */ 6112292SN/A void markSrcRegReady(); 6122190SN/A 6132331SN/A /** Marks a specific register as ready. */ 6142292SN/A void markSrcRegReady(RegIndex src_idx); 6152190SN/A 6161684SN/A /** Returns if a source register is ready. */ 6171464SN/A bool isReadySrcRegIdx(int idx) const 6181464SN/A { 6191464SN/A return this->_readySrcRegIdx[idx]; 6201464SN/A } 6211464SN/A 6221684SN/A /** Sets this instruction as completed. */ 6232731Sktlim@umich.edu void setCompleted() { status.set(Completed); } 6241464SN/A 6252292SN/A /** Returns whether or not this instruction is completed. */ 6262731Sktlim@umich.edu bool isCompleted() const { return status[Completed]; } 6271464SN/A 6282731Sktlim@umich.edu /** Marks the result as ready. */ 6292731Sktlim@umich.edu void setResultReady() { status.set(ResultReady); } 6302308SN/A 6312731Sktlim@umich.edu /** Returns whether or not the result is ready. */ 6322731Sktlim@umich.edu bool isResultReady() const { return status[ResultReady]; } 6332308SN/A 6341060SN/A /** Sets this instruction as ready to issue. */ 6352731Sktlim@umich.edu void setCanIssue() { status.set(CanIssue); } 6361060SN/A 6371060SN/A /** Returns whether or not this instruction is ready to issue. */ 6382731Sktlim@umich.edu bool readyToIssue() const { return status[CanIssue]; } 6391060SN/A 6404032Sktlim@umich.edu /** Clears this instruction being able to issue. */ 6414032Sktlim@umich.edu void clearCanIssue() { status.reset(CanIssue); } 6424032Sktlim@umich.edu 6431060SN/A /** Sets this instruction as issued from the IQ. */ 6442731Sktlim@umich.edu void setIssued() { status.set(Issued); } 6451060SN/A 6461060SN/A /** Returns whether or not this instruction has issued. */ 6472731Sktlim@umich.edu bool isIssued() const { return status[Issued]; } 6481060SN/A 6494032Sktlim@umich.edu /** Clears this instruction as being issued. */ 6504032Sktlim@umich.edu void clearIssued() { status.reset(Issued); } 6514032Sktlim@umich.edu 6521060SN/A /** Sets this instruction as executed. */ 6532731Sktlim@umich.edu void setExecuted() { status.set(Executed); } 6541060SN/A 6551060SN/A /** Returns whether or not this instruction has executed. */ 6562731Sktlim@umich.edu bool isExecuted() const { return status[Executed]; } 6571060SN/A 6581060SN/A /** Sets this instruction as ready to commit. */ 6592731Sktlim@umich.edu void setCanCommit() { status.set(CanCommit); } 6601060SN/A 6611061SN/A /** Clears this instruction as being ready to commit. */ 6622731Sktlim@umich.edu void clearCanCommit() { status.reset(CanCommit); } 6631061SN/A 6641060SN/A /** Returns whether or not this instruction is ready to commit. */ 6652731Sktlim@umich.edu bool readyToCommit() const { return status[CanCommit]; } 6662731Sktlim@umich.edu 6672731Sktlim@umich.edu void setAtCommit() { status.set(AtCommit); } 6682731Sktlim@umich.edu 6692731Sktlim@umich.edu bool isAtCommit() { return status[AtCommit]; } 6701060SN/A 6712292SN/A /** Sets this instruction as committed. */ 6722731Sktlim@umich.edu void setCommitted() { status.set(Committed); } 6732292SN/A 6742292SN/A /** Returns whether or not this instruction is committed. */ 6752731Sktlim@umich.edu bool isCommitted() const { return status[Committed]; } 6762292SN/A 6771060SN/A /** Sets this instruction as squashed. */ 6782731Sktlim@umich.edu void setSquashed() { status.set(Squashed); } 6791060SN/A 6801060SN/A /** Returns whether or not this instruction is squashed. */ 6812731Sktlim@umich.edu bool isSquashed() const { return status[Squashed]; } 6821060SN/A 6832292SN/A //Instruction Queue Entry 6842292SN/A //----------------------- 6852292SN/A /** Sets this instruction as a entry the IQ. */ 6862731Sktlim@umich.edu void setInIQ() { status.set(IqEntry); } 6872292SN/A 6882292SN/A /** Sets this instruction as a entry the IQ. */ 6892731Sktlim@umich.edu void clearInIQ() { status.reset(IqEntry); } 6902731Sktlim@umich.edu 6912731Sktlim@umich.edu /** Returns whether or not this instruction has issued. */ 6922731Sktlim@umich.edu bool isInIQ() const { return status[IqEntry]; } 6932292SN/A 6941060SN/A /** Sets this instruction as squashed in the IQ. */ 6952731Sktlim@umich.edu void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 6961060SN/A 6971060SN/A /** Returns whether or not this instruction is squashed in the IQ. */ 6982731Sktlim@umich.edu bool isSquashedInIQ() const { return status[SquashedInIQ]; } 6992292SN/A 7002292SN/A 7012292SN/A //Load / Store Queue Functions 7022292SN/A //----------------------- 7032292SN/A /** Sets this instruction as a entry the LSQ. */ 7042731Sktlim@umich.edu void setInLSQ() { status.set(LsqEntry); } 7052292SN/A 7062292SN/A /** Sets this instruction as a entry the LSQ. */ 7072731Sktlim@umich.edu void removeInLSQ() { status.reset(LsqEntry); } 7082731Sktlim@umich.edu 7092731Sktlim@umich.edu /** Returns whether or not this instruction is in the LSQ. */ 7102731Sktlim@umich.edu bool isInLSQ() const { return status[LsqEntry]; } 7112292SN/A 7122292SN/A /** Sets this instruction as squashed in the LSQ. */ 7132731Sktlim@umich.edu void setSquashedInLSQ() { status.set(SquashedInLSQ);} 7142292SN/A 7152292SN/A /** Returns whether or not this instruction is squashed in the LSQ. */ 7162731Sktlim@umich.edu bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 7172292SN/A 7182292SN/A 7192292SN/A //Reorder Buffer Functions 7202292SN/A //----------------------- 7212292SN/A /** Sets this instruction as a entry the ROB. */ 7222731Sktlim@umich.edu void setInROB() { status.set(RobEntry); } 7232292SN/A 7242292SN/A /** Sets this instruction as a entry the ROB. */ 7252731Sktlim@umich.edu void clearInROB() { status.reset(RobEntry); } 7262731Sktlim@umich.edu 7272731Sktlim@umich.edu /** Returns whether or not this instruction is in the ROB. */ 7282731Sktlim@umich.edu bool isInROB() const { return status[RobEntry]; } 7292292SN/A 7302292SN/A /** Sets this instruction as squashed in the ROB. */ 7312731Sktlim@umich.edu void setSquashedInROB() { status.set(SquashedInROB); } 7322292SN/A 7332292SN/A /** Returns whether or not this instruction is squashed in the ROB. */ 7342731Sktlim@umich.edu bool isSquashedInROB() const { return status[SquashedInROB]; } 7352292SN/A 7367720Sgblack@eecs.umich.edu /** Read the PC state of this instruction. */ 7377720Sgblack@eecs.umich.edu const TheISA::PCState pcState() const { return pc; } 7387720Sgblack@eecs.umich.edu 7397720Sgblack@eecs.umich.edu /** Set the PC state of this instruction. */ 7407720Sgblack@eecs.umich.edu const void pcState(const TheISA::PCState &val) { pc = val; } 7417720Sgblack@eecs.umich.edu 7421060SN/A /** Read the PC of this instruction. */ 7437720Sgblack@eecs.umich.edu const Addr instAddr() const { return pc.instAddr(); } 7447720Sgblack@eecs.umich.edu 7457720Sgblack@eecs.umich.edu /** Read the PC of the next instruction. */ 7467720Sgblack@eecs.umich.edu const Addr nextInstAddr() const { return pc.nextInstAddr(); } 7471060SN/A 7484636Sgblack@eecs.umich.edu /**Read the micro PC of this instruction. */ 7497720Sgblack@eecs.umich.edu const Addr microPC() const { return pc.microPC(); } 7504636Sgblack@eecs.umich.edu 7517597Sminkyu.jeong@arm.com bool readPredicate() 7527597Sminkyu.jeong@arm.com { 7537597Sminkyu.jeong@arm.com return predicate; 7547597Sminkyu.jeong@arm.com } 7557597Sminkyu.jeong@arm.com 7567597Sminkyu.jeong@arm.com void setPredicate(bool val) 7577597Sminkyu.jeong@arm.com { 7587597Sminkyu.jeong@arm.com predicate = val; 7597600Sminkyu.jeong@arm.com 7607600Sminkyu.jeong@arm.com if (traceData) { 7617600Sminkyu.jeong@arm.com traceData->setPredicate(val); 7627600Sminkyu.jeong@arm.com } 7637597Sminkyu.jeong@arm.com } 7647597Sminkyu.jeong@arm.com 7652702Sktlim@umich.edu /** Sets the ASID. */ 7662292SN/A void setASID(short addr_space_id) { asid = addr_space_id; } 7672292SN/A 7682702Sktlim@umich.edu /** Sets the thread id. */ 7696221Snate@binkert.org void setTid(ThreadID tid) { threadNumber = tid; } 7702292SN/A 7712731Sktlim@umich.edu /** Sets the pointer to the thread state. */ 7722702Sktlim@umich.edu void setThreadState(ImplState *state) { thread = state; } 7731060SN/A 7742731Sktlim@umich.edu /** Returns the thread context. */ 7752680Sktlim@umich.edu ThreadContext *tcBase() { return thread->getTC(); } 7761464SN/A 7771464SN/A private: 7781684SN/A /** Instruction effective address. 7791684SN/A * @todo: Consider if this is necessary or not. 7801684SN/A */ 7811464SN/A Addr instEffAddr; 7822292SN/A 7831684SN/A /** Whether or not the effective address calculation is completed. 7841684SN/A * @todo: Consider if this is necessary or not. 7851684SN/A */ 7861464SN/A bool eaCalcDone; 7871464SN/A 7884032Sktlim@umich.edu /** Is this instruction's memory access uncacheable. */ 7894032Sktlim@umich.edu bool isUncacheable; 7904032Sktlim@umich.edu 7914032Sktlim@umich.edu /** Has this instruction generated a memory request. */ 7924032Sktlim@umich.edu bool reqMade; 7934032Sktlim@umich.edu 7941464SN/A public: 7951684SN/A /** Sets the effective address. */ 7961464SN/A void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 7971684SN/A 7981684SN/A /** Returns the effective address. */ 7991464SN/A const Addr &getEA() const { return instEffAddr; } 8001684SN/A 8011684SN/A /** Returns whether or not the eff. addr. calculation has been completed. */ 8021464SN/A bool doneEACalc() { return eaCalcDone; } 8031684SN/A 8041684SN/A /** Returns whether or not the eff. addr. source registers are ready. */ 8051464SN/A bool eaSrcsReady(); 8061681SN/A 8072292SN/A /** Whether or not the memory operation is done. */ 8082292SN/A bool memOpDone; 8092292SN/A 8104032Sktlim@umich.edu /** Is this instruction's memory access uncacheable. */ 8114032Sktlim@umich.edu bool uncacheable() { return isUncacheable; } 8124032Sktlim@umich.edu 8134032Sktlim@umich.edu /** Has this instruction generated a memory request. */ 8144032Sktlim@umich.edu bool hasRequest() { return reqMade; } 8154032Sktlim@umich.edu 8161681SN/A public: 8171684SN/A /** Load queue index. */ 8181681SN/A int16_t lqIdx; 8191684SN/A 8201684SN/A /** Store queue index. */ 8211681SN/A int16_t sqIdx; 8222292SN/A 8232292SN/A /** Iterator pointing to this BaseDynInst in the list of all insts. */ 8242292SN/A ListIt instListIt; 8252292SN/A 8262292SN/A /** Returns iterator to this instruction in the list of all insts. */ 8272292SN/A ListIt &getInstListIt() { return instListIt; } 8282292SN/A 8292292SN/A /** Sets iterator for this instruction in the list of all insts. */ 8302292SN/A void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 8313326Sktlim@umich.edu 8323326Sktlim@umich.edu public: 8333326Sktlim@umich.edu /** Returns the number of consecutive store conditional failures. */ 8343326Sktlim@umich.edu unsigned readStCondFailures() 8353326Sktlim@umich.edu { return thread->storeCondFailures; } 8363326Sktlim@umich.edu 8373326Sktlim@umich.edu /** Sets the number of consecutive store conditional failures. */ 8383326Sktlim@umich.edu void setStCondFailures(unsigned sc_failures) 8393326Sktlim@umich.edu { thread->storeCondFailures = sc_failures; } 8401060SN/A}; 8411060SN/A 8421060SN/Atemplate<class Impl> 8437520Sgblack@eecs.umich.eduFault 8448444Sgblack@eecs.umich.eduBaseDynInst<Impl>::readMem(Addr addr, uint8_t *data, 8458444Sgblack@eecs.umich.edu unsigned size, unsigned flags) 8461060SN/A{ 8474032Sktlim@umich.edu reqMade = true; 8487944SGiacomo.Gabrielli@arm.com Request *req = NULL; 8496974Stjones1@inf.ed.ac.uk Request *sreqLow = NULL; 8506974Stjones1@inf.ed.ac.uk Request *sreqHigh = NULL; 8516974Stjones1@inf.ed.ac.uk 8527944SGiacomo.Gabrielli@arm.com if (reqMade && translationStarted) { 8537944SGiacomo.Gabrielli@arm.com req = savedReq; 8547944SGiacomo.Gabrielli@arm.com sreqLow = savedSreqLow; 8557944SGiacomo.Gabrielli@arm.com sreqHigh = savedSreqHigh; 8567944SGiacomo.Gabrielli@arm.com } else { 8577944SGiacomo.Gabrielli@arm.com req = new Request(asid, addr, size, flags, this->pc.instAddr(), 8587944SGiacomo.Gabrielli@arm.com thread->contextId(), threadNumber); 8594032Sktlim@umich.edu 8607944SGiacomo.Gabrielli@arm.com // Only split the request if the ISA supports unaligned accesses. 8617944SGiacomo.Gabrielli@arm.com if (TheISA::HasUnalignedMemAcc) { 8627944SGiacomo.Gabrielli@arm.com splitRequest(req, sreqLow, sreqHigh); 8637944SGiacomo.Gabrielli@arm.com } 8647944SGiacomo.Gabrielli@arm.com initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read); 8651060SN/A } 8661060SN/A 8677944SGiacomo.Gabrielli@arm.com if (translationCompleted) { 8687944SGiacomo.Gabrielli@arm.com if (fault == NoFault) { 8697944SGiacomo.Gabrielli@arm.com effAddr = req->getVaddr(); 8708199SAli.Saidi@ARM.com effSize = size; 8717944SGiacomo.Gabrielli@arm.com effAddrValid = true; 8727944SGiacomo.Gabrielli@arm.com fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx); 8737944SGiacomo.Gabrielli@arm.com } else { 8747944SGiacomo.Gabrielli@arm.com // Commit will have to clean up whatever happened. Set this 8757944SGiacomo.Gabrielli@arm.com // instruction as executed. 8767944SGiacomo.Gabrielli@arm.com this->setExecuted(); 8777944SGiacomo.Gabrielli@arm.com } 8787944SGiacomo.Gabrielli@arm.com 8797944SGiacomo.Gabrielli@arm.com if (fault != NoFault) { 8807944SGiacomo.Gabrielli@arm.com // Return a fixed value to keep simulation deterministic even 8817944SGiacomo.Gabrielli@arm.com // along misspeculated paths. 8827944SGiacomo.Gabrielli@arm.com if (data) 8837944SGiacomo.Gabrielli@arm.com bzero(data, size); 8847944SGiacomo.Gabrielli@arm.com } 8857577SAli.Saidi@ARM.com } 8867577SAli.Saidi@ARM.com 8871060SN/A if (traceData) { 8881060SN/A traceData->setAddr(addr); 8891060SN/A } 8901060SN/A 8911060SN/A return fault; 8921060SN/A} 8931060SN/A 8941060SN/Atemplate<class Impl> 8957520Sgblack@eecs.umich.eduFault 8968444Sgblack@eecs.umich.eduBaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, 8978444Sgblack@eecs.umich.edu Addr addr, unsigned flags, uint64_t *res) 8981060SN/A{ 8991060SN/A if (traceData) { 9001060SN/A traceData->setAddr(addr); 9011060SN/A } 9021060SN/A 9034032Sktlim@umich.edu reqMade = true; 9047944SGiacomo.Gabrielli@arm.com Request *req = NULL; 9056974Stjones1@inf.ed.ac.uk Request *sreqLow = NULL; 9066974Stjones1@inf.ed.ac.uk Request *sreqHigh = NULL; 9076974Stjones1@inf.ed.ac.uk 9087944SGiacomo.Gabrielli@arm.com if (reqMade && translationStarted) { 9097944SGiacomo.Gabrielli@arm.com req = savedReq; 9107944SGiacomo.Gabrielli@arm.com sreqLow = savedSreqLow; 9117944SGiacomo.Gabrielli@arm.com sreqHigh = savedSreqHigh; 9127944SGiacomo.Gabrielli@arm.com } else { 9137944SGiacomo.Gabrielli@arm.com req = new Request(asid, addr, size, flags, this->pc.instAddr(), 9147944SGiacomo.Gabrielli@arm.com thread->contextId(), threadNumber); 9157944SGiacomo.Gabrielli@arm.com 9167944SGiacomo.Gabrielli@arm.com // Only split the request if the ISA supports unaligned accesses. 9177944SGiacomo.Gabrielli@arm.com if (TheISA::HasUnalignedMemAcc) { 9187944SGiacomo.Gabrielli@arm.com splitRequest(req, sreqLow, sreqHigh); 9197944SGiacomo.Gabrielli@arm.com } 9207944SGiacomo.Gabrielli@arm.com initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write); 9216974Stjones1@inf.ed.ac.uk } 9224032Sktlim@umich.edu 9237944SGiacomo.Gabrielli@arm.com if (fault == NoFault && translationCompleted) { 9242678Sktlim@umich.edu effAddr = req->getVaddr(); 9258199SAli.Saidi@ARM.com effSize = size; 9264032Sktlim@umich.edu effAddrValid = true; 9276975Stjones1@inf.ed.ac.uk fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx); 9281060SN/A } 9291060SN/A 9301060SN/A return fault; 9311060SN/A} 9321060SN/A 9336973Stjones1@inf.ed.ac.uktemplate<class Impl> 9346973Stjones1@inf.ed.ac.ukinline void 9356974Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow, 9366974Stjones1@inf.ed.ac.uk RequestPtr &sreqHigh) 9376974Stjones1@inf.ed.ac.uk{ 9386974Stjones1@inf.ed.ac.uk // Check to see if the request crosses the next level block boundary. 9396974Stjones1@inf.ed.ac.uk unsigned block_size = cpu->getDcachePort()->peerBlockSize(); 9406974Stjones1@inf.ed.ac.uk Addr addr = req->getVaddr(); 9416974Stjones1@inf.ed.ac.uk Addr split_addr = roundDown(addr + req->getSize() - 1, block_size); 9426974Stjones1@inf.ed.ac.uk assert(split_addr <= addr || split_addr - addr < block_size); 9436974Stjones1@inf.ed.ac.uk 9446974Stjones1@inf.ed.ac.uk // Spans two blocks. 9456974Stjones1@inf.ed.ac.uk if (split_addr > addr) { 9466974Stjones1@inf.ed.ac.uk req->splitOnVaddr(split_addr, sreqLow, sreqHigh); 9476974Stjones1@inf.ed.ac.uk } 9486974Stjones1@inf.ed.ac.uk} 9496974Stjones1@inf.ed.ac.uk 9506974Stjones1@inf.ed.ac.uktemplate<class Impl> 9516974Stjones1@inf.ed.ac.ukinline void 9526974Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow, 9536974Stjones1@inf.ed.ac.uk RequestPtr sreqHigh, uint64_t *res, 9546973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode) 9556973Stjones1@inf.ed.ac.uk{ 9567944SGiacomo.Gabrielli@arm.com translationStarted = true; 9577944SGiacomo.Gabrielli@arm.com 9586974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) { 9596974Stjones1@inf.ed.ac.uk WholeTranslationState *state = 9606974Stjones1@inf.ed.ac.uk new WholeTranslationState(req, NULL, res, mode); 9616974Stjones1@inf.ed.ac.uk 9626974Stjones1@inf.ed.ac.uk // One translation if the request isn't split. 9636974Stjones1@inf.ed.ac.uk DataTranslation<BaseDynInst<Impl> > *trans = 9646974Stjones1@inf.ed.ac.uk new DataTranslation<BaseDynInst<Impl> >(this, state); 9656974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(req, thread->getTC(), trans, mode); 9667944SGiacomo.Gabrielli@arm.com if (!translationCompleted) { 9677944SGiacomo.Gabrielli@arm.com // Save memory requests. 9687944SGiacomo.Gabrielli@arm.com savedReq = state->mainReq; 9697944SGiacomo.Gabrielli@arm.com savedSreqLow = state->sreqLow; 9707944SGiacomo.Gabrielli@arm.com savedSreqHigh = state->sreqHigh; 9717944SGiacomo.Gabrielli@arm.com } 9726974Stjones1@inf.ed.ac.uk } else { 9736974Stjones1@inf.ed.ac.uk WholeTranslationState *state = 9746974Stjones1@inf.ed.ac.uk new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode); 9756974Stjones1@inf.ed.ac.uk 9766974Stjones1@inf.ed.ac.uk // Two translations when the request is split. 9776974Stjones1@inf.ed.ac.uk DataTranslation<BaseDynInst<Impl> > *stransLow = 9786974Stjones1@inf.ed.ac.uk new DataTranslation<BaseDynInst<Impl> >(this, state, 0); 9796974Stjones1@inf.ed.ac.uk DataTranslation<BaseDynInst<Impl> > *stransHigh = 9806974Stjones1@inf.ed.ac.uk new DataTranslation<BaseDynInst<Impl> >(this, state, 1); 9816974Stjones1@inf.ed.ac.uk 9826974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode); 9836974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode); 9847944SGiacomo.Gabrielli@arm.com if (!translationCompleted) { 9857944SGiacomo.Gabrielli@arm.com // Save memory requests. 9867944SGiacomo.Gabrielli@arm.com savedReq = state->mainReq; 9877944SGiacomo.Gabrielli@arm.com savedSreqLow = state->sreqLow; 9887944SGiacomo.Gabrielli@arm.com savedSreqHigh = state->sreqHigh; 9897944SGiacomo.Gabrielli@arm.com } 9906974Stjones1@inf.ed.ac.uk } 9916973Stjones1@inf.ed.ac.uk} 9926973Stjones1@inf.ed.ac.uk 9936973Stjones1@inf.ed.ac.uktemplate<class Impl> 9946973Stjones1@inf.ed.ac.ukinline void 9956973Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::finishTranslation(WholeTranslationState *state) 9966973Stjones1@inf.ed.ac.uk{ 9976973Stjones1@inf.ed.ac.uk fault = state->getFault(); 9986973Stjones1@inf.ed.ac.uk 9996973Stjones1@inf.ed.ac.uk if (state->isUncacheable()) 10006973Stjones1@inf.ed.ac.uk isUncacheable = true; 10016973Stjones1@inf.ed.ac.uk 10026973Stjones1@inf.ed.ac.uk if (fault == NoFault) { 10036973Stjones1@inf.ed.ac.uk physEffAddr = state->getPaddr(); 10046973Stjones1@inf.ed.ac.uk memReqFlags = state->getFlags(); 10056973Stjones1@inf.ed.ac.uk 10066973Stjones1@inf.ed.ac.uk if (state->mainReq->isCondSwap()) { 10076973Stjones1@inf.ed.ac.uk assert(state->res); 10086973Stjones1@inf.ed.ac.uk state->mainReq->setExtraData(*state->res); 10096973Stjones1@inf.ed.ac.uk } 10106973Stjones1@inf.ed.ac.uk 10116973Stjones1@inf.ed.ac.uk } else { 10126973Stjones1@inf.ed.ac.uk state->deleteReqs(); 10136973Stjones1@inf.ed.ac.uk } 10146973Stjones1@inf.ed.ac.uk delete state; 10157944SGiacomo.Gabrielli@arm.com 10167944SGiacomo.Gabrielli@arm.com translationCompleted = true; 10176973Stjones1@inf.ed.ac.uk} 10186973Stjones1@inf.ed.ac.uk 10191464SN/A#endif // __CPU_BASE_DYN_INST_HH__ 1020