base_dyn_inst.hh revision 6975
11060SN/A/* 22702Sktlim@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 36973Stjones1@inf.ed.ac.uk * Copyright (c) 2009 The University of Edinburgh 41060SN/A * All rights reserved. 51060SN/A * 61060SN/A * Redistribution and use in source and binary forms, with or without 71060SN/A * modification, are permitted provided that the following conditions are 81060SN/A * met: redistributions of source code must retain the above copyright 91060SN/A * notice, this list of conditions and the following disclaimer; 101060SN/A * redistributions in binary form must reproduce the above copyright 111060SN/A * notice, this list of conditions and the following disclaimer in the 121060SN/A * documentation and/or other materials provided with the distribution; 131060SN/A * neither the name of the copyright holders nor the names of its 141060SN/A * contributors may be used to endorse or promote products derived from 151060SN/A * this software without specific prior written permission. 161060SN/A * 171060SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 181060SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 191060SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 201060SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 211060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 221060SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 231060SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 241060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 251060SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 261060SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 271060SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu * 292665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 306973Stjones1@inf.ed.ac.uk * Timothy M. Jones 311060SN/A */ 321060SN/A 331464SN/A#ifndef __CPU_BASE_DYN_INST_HH__ 341464SN/A#define __CPU_BASE_DYN_INST_HH__ 351060SN/A 362731Sktlim@umich.edu#include <bitset> 372292SN/A#include <list> 381464SN/A#include <string> 391060SN/A 402669Sktlim@umich.edu#include "arch/faults.hh" 411060SN/A#include "base/fast_alloc.hh" 421060SN/A#include "base/trace.hh" 431858SN/A#include "config/full_system.hh" 446658Snate@binkert.org#include "config/the_isa.hh" 453770Sgblack@eecs.umich.edu#include "cpu/o3/comm.hh" 461464SN/A#include "cpu/exetrace.hh" 471464SN/A#include "cpu/inst_seq.hh" 482669Sktlim@umich.edu#include "cpu/op_class.hh" 491060SN/A#include "cpu/static_inst.hh" 506973Stjones1@inf.ed.ac.uk#include "cpu/translation.hh" 512669Sktlim@umich.edu#include "mem/packet.hh" 522292SN/A#include "sim/system.hh" 536023Snate@binkert.org#include "sim/tlb.hh" 541060SN/A 551060SN/A/** 561060SN/A * @file 571060SN/A * Defines a dynamic instruction context. 581060SN/A */ 591060SN/A 601061SN/A// Forward declaration. 611061SN/Aclass StaticInstPtr; 621060SN/A 631060SN/Atemplate <class Impl> 641061SN/Aclass BaseDynInst : public FastAlloc, public RefCounted 651060SN/A{ 661060SN/A public: 671060SN/A // Typedef for the CPU. 682733Sktlim@umich.edu typedef typename Impl::CPUType ImplCPU; 692733Sktlim@umich.edu typedef typename ImplCPU::ImplState ImplState; 701060SN/A 712292SN/A // Logical register index type. 722107SN/A typedef TheISA::RegIndex RegIndex; 732690Sktlim@umich.edu // Integer register type. 742107SN/A typedef TheISA::IntReg IntReg; 752690Sktlim@umich.edu // Floating point register type. 762690Sktlim@umich.edu typedef TheISA::FloatReg FloatReg; 771060SN/A 782292SN/A // The DynInstPtr type. 792292SN/A typedef typename Impl::DynInstPtr DynInstPtr; 802292SN/A 812292SN/A // The list of instructions iterator type. 822292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 832292SN/A 841060SN/A enum { 855543Ssaidi@eecs.umich.edu MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 865543Ssaidi@eecs.umich.edu MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs 871060SN/A }; 881060SN/A 892292SN/A /** The StaticInst used by this BaseDynInst. */ 902107SN/A StaticInstPtr staticInst; 911060SN/A 921060SN/A //////////////////////////////////////////// 931060SN/A // 941060SN/A // INSTRUCTION EXECUTION 951060SN/A // 961060SN/A //////////////////////////////////////////// 972292SN/A /** InstRecord that tracks this instructions. */ 981060SN/A Trace::InstRecord *traceData; 991060SN/A 1005358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 1015358Sgblack@eecs.umich.edu { 1025358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 1035358Sgblack@eecs.umich.edu } 1045358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 1055358Sgblack@eecs.umich.edu { 1065358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 1075358Sgblack@eecs.umich.edu } 1085358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 1095358Sgblack@eecs.umich.edu { 1105358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 1115358Sgblack@eecs.umich.edu } 1125358Sgblack@eecs.umich.edu 1132292SN/A /** 1142292SN/A * Does a read to a given address. 1152292SN/A * @param addr The address to read. 1162292SN/A * @param data The read's data is written into this parameter. 1172292SN/A * @param flags The request's flags. 1182292SN/A * @return Returns any fault due to the read. 1192292SN/A */ 1201060SN/A template <class T> 1212132SN/A Fault read(Addr addr, T &data, unsigned flags); 1221060SN/A 1232292SN/A /** 1242292SN/A * Does a write to a given address. 1252292SN/A * @param data The data to be written. 1262292SN/A * @param addr The address to write to. 1272292SN/A * @param flags The request's flags. 1282292SN/A * @param res The result of the write (for load locked/store conditionals). 1292292SN/A * @return Returns any fault due to the write. 1302292SN/A */ 1311060SN/A template <class T> 1326973Stjones1@inf.ed.ac.uk Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 1336973Stjones1@inf.ed.ac.uk 1346974Stjones1@inf.ed.ac.uk /** Splits a request in two if it crosses a dcache block. */ 1356974Stjones1@inf.ed.ac.uk void splitRequest(RequestPtr req, RequestPtr &sreqLow, 1366974Stjones1@inf.ed.ac.uk RequestPtr &sreqHigh); 1376974Stjones1@inf.ed.ac.uk 1386973Stjones1@inf.ed.ac.uk /** Initiate a DTB address translation. */ 1396974Stjones1@inf.ed.ac.uk void initiateTranslation(RequestPtr req, RequestPtr sreqLow, 1406974Stjones1@inf.ed.ac.uk RequestPtr sreqHigh, uint64_t *res, 1416973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode); 1426973Stjones1@inf.ed.ac.uk 1436973Stjones1@inf.ed.ac.uk /** Finish a DTB address translation. */ 1446973Stjones1@inf.ed.ac.uk void finishTranslation(WholeTranslationState *state); 1451060SN/A 1461060SN/A void prefetch(Addr addr, unsigned flags); 1471060SN/A void writeHint(Addr addr, int size, unsigned flags); 1482132SN/A Fault copySrcTranslate(Addr src); 1492132SN/A Fault copy(Addr dest); 1501060SN/A 1511684SN/A /** @todo: Consider making this private. */ 1521060SN/A public: 1531060SN/A /** The sequence number of the instruction. */ 1541060SN/A InstSeqNum seqNum; 1551060SN/A 1562731Sktlim@umich.edu enum Status { 1572731Sktlim@umich.edu IqEntry, /// Instruction is in the IQ 1582731Sktlim@umich.edu RobEntry, /// Instruction is in the ROB 1592731Sktlim@umich.edu LsqEntry, /// Instruction is in the LSQ 1602731Sktlim@umich.edu Completed, /// Instruction has completed 1612731Sktlim@umich.edu ResultReady, /// Instruction has its result 1622731Sktlim@umich.edu CanIssue, /// Instruction can issue and execute 1632731Sktlim@umich.edu Issued, /// Instruction has issued 1642731Sktlim@umich.edu Executed, /// Instruction has executed 1652731Sktlim@umich.edu CanCommit, /// Instruction can commit 1662731Sktlim@umich.edu AtCommit, /// Instruction has reached commit 1672731Sktlim@umich.edu Committed, /// Instruction has committed 1682731Sktlim@umich.edu Squashed, /// Instruction is squashed 1692731Sktlim@umich.edu SquashedInIQ, /// Instruction is squashed in the IQ 1702731Sktlim@umich.edu SquashedInLSQ, /// Instruction is squashed in the LSQ 1712731Sktlim@umich.edu SquashedInROB, /// Instruction is squashed in the ROB 1722731Sktlim@umich.edu RecoverInst, /// Is a recover instruction 1732731Sktlim@umich.edu BlockingInst, /// Is a blocking instruction 1742731Sktlim@umich.edu ThreadsyncWait, /// Is a thread synchronization instruction 1752731Sktlim@umich.edu SerializeBefore, /// Needs to serialize on 1762731Sktlim@umich.edu /// instructions ahead of it 1772731Sktlim@umich.edu SerializeAfter, /// Needs to serialize instructions behind it 1782731Sktlim@umich.edu SerializeHandled, /// Serialization has been handled 1792731Sktlim@umich.edu NumStatus 1802731Sktlim@umich.edu }; 1812292SN/A 1822731Sktlim@umich.edu /** The status of this BaseDynInst. Several bits can be set. */ 1832731Sktlim@umich.edu std::bitset<NumStatus> status; 1841060SN/A 1851060SN/A /** The thread this instruction is from. */ 1866221Snate@binkert.org ThreadID threadNumber; 1871060SN/A 1881060SN/A /** data address space ID, for loads & stores. */ 1891060SN/A short asid; 1901060SN/A 1912292SN/A /** How many source registers are ready. */ 1922292SN/A unsigned readyRegs; 1932292SN/A 1942733Sktlim@umich.edu /** Pointer to the Impl's CPU object. */ 1952733Sktlim@umich.edu ImplCPU *cpu; 1961060SN/A 1972680Sktlim@umich.edu /** Pointer to the thread state. */ 1982292SN/A ImplState *thread; 1991060SN/A 2001060SN/A /** The kind of fault this instruction has generated. */ 2012132SN/A Fault fault; 2021060SN/A 2032702Sktlim@umich.edu /** Pointer to the data for the memory access. */ 2042669Sktlim@umich.edu uint8_t *memData; 2052292SN/A 2061060SN/A /** The effective virtual address (lds & stores only). */ 2071060SN/A Addr effAddr; 2081060SN/A 2094032Sktlim@umich.edu /** Is the effective virtual address valid. */ 2104032Sktlim@umich.edu bool effAddrValid; 2114032Sktlim@umich.edu 2121060SN/A /** The effective physical address. */ 2131060SN/A Addr physEffAddr; 2141060SN/A 2151060SN/A /** Effective virtual address for a copy source. */ 2161060SN/A Addr copySrcEffAddr; 2171060SN/A 2181060SN/A /** Effective physical address for a copy source. */ 2191060SN/A Addr copySrcPhysEffAddr; 2201060SN/A 2211060SN/A /** The memory request flags (from translation). */ 2221060SN/A unsigned memReqFlags; 2231060SN/A 2241464SN/A union Result { 2251464SN/A uint64_t integer; 2262356SN/A// float fp; 2271464SN/A double dbl; 2281464SN/A }; 2291060SN/A 2301464SN/A /** The result of the instruction; assumes for now that there's only one 2311464SN/A * destination register. 2321464SN/A */ 2331464SN/A Result instResult; 2341060SN/A 2353326Sktlim@umich.edu /** Records changes to result? */ 2363326Sktlim@umich.edu bool recordResult; 2373326Sktlim@umich.edu 2381060SN/A /** PC of this instruction. */ 2391060SN/A Addr PC; 2401060SN/A 2414636Sgblack@eecs.umich.edu /** Micro PC of this instruction. */ 2424636Sgblack@eecs.umich.edu Addr microPC; 2434636Sgblack@eecs.umich.edu 2443965Sgblack@eecs.umich.edu protected: 2451060SN/A /** Next non-speculative PC. It is not filled in at fetch, but rather 2461060SN/A * once the target of the branch is truly known (either decode or 2471060SN/A * execute). 2481060SN/A */ 2491060SN/A Addr nextPC; 2501060SN/A 2512935Sksewell@umich.edu /** Next non-speculative NPC. Target PC for Mips or Sparc. */ 2522935Sksewell@umich.edu Addr nextNPC; 2532935Sksewell@umich.edu 2544636Sgblack@eecs.umich.edu /** Next non-speculative micro PC. */ 2554636Sgblack@eecs.umich.edu Addr nextMicroPC; 2564636Sgblack@eecs.umich.edu 2571060SN/A /** Predicted next PC. */ 2581060SN/A Addr predPC; 2591060SN/A 2603794Sgblack@eecs.umich.edu /** Predicted next NPC. */ 2613794Sgblack@eecs.umich.edu Addr predNPC; 2623794Sgblack@eecs.umich.edu 2634636Sgblack@eecs.umich.edu /** Predicted next microPC */ 2644636Sgblack@eecs.umich.edu Addr predMicroPC; 2654636Sgblack@eecs.umich.edu 2663794Sgblack@eecs.umich.edu /** If this is a branch that was predicted taken */ 2673794Sgblack@eecs.umich.edu bool predTaken; 2683794Sgblack@eecs.umich.edu 2693965Sgblack@eecs.umich.edu public: 2703965Sgblack@eecs.umich.edu 2712292SN/A#ifdef DEBUG 2722292SN/A void dumpSNList(); 2732292SN/A#endif 2742292SN/A 2752292SN/A /** Whether or not the source register is ready. 2762292SN/A * @todo: Not sure this should be here vs the derived class. 2771060SN/A */ 2781060SN/A bool _readySrcRegIdx[MaxInstSrcRegs]; 2791060SN/A 2803770Sgblack@eecs.umich.edu protected: 2813770Sgblack@eecs.umich.edu /** Flattened register index of the destination registers of this 2823770Sgblack@eecs.umich.edu * instruction. 2833770Sgblack@eecs.umich.edu */ 2843770Sgblack@eecs.umich.edu TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs]; 2853770Sgblack@eecs.umich.edu 2863770Sgblack@eecs.umich.edu /** Flattened register index of the source registers of this 2873770Sgblack@eecs.umich.edu * instruction. 2883770Sgblack@eecs.umich.edu */ 2893770Sgblack@eecs.umich.edu TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs]; 2903770Sgblack@eecs.umich.edu 2913770Sgblack@eecs.umich.edu /** Physical register index of the destination registers of this 2923770Sgblack@eecs.umich.edu * instruction. 2933770Sgblack@eecs.umich.edu */ 2943770Sgblack@eecs.umich.edu PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs]; 2953770Sgblack@eecs.umich.edu 2963770Sgblack@eecs.umich.edu /** Physical register index of the source registers of this 2973770Sgblack@eecs.umich.edu * instruction. 2983770Sgblack@eecs.umich.edu */ 2993770Sgblack@eecs.umich.edu PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs]; 3003770Sgblack@eecs.umich.edu 3013770Sgblack@eecs.umich.edu /** Physical register index of the previous producers of the 3023770Sgblack@eecs.umich.edu * architected destinations. 3033770Sgblack@eecs.umich.edu */ 3043770Sgblack@eecs.umich.edu PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs]; 3053770Sgblack@eecs.umich.edu 3061060SN/A public: 3073770Sgblack@eecs.umich.edu 3083770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th destination 3093770Sgblack@eecs.umich.edu * register. 3103770Sgblack@eecs.umich.edu */ 3113770Sgblack@eecs.umich.edu PhysRegIndex renamedDestRegIdx(int idx) const 3123770Sgblack@eecs.umich.edu { 3133770Sgblack@eecs.umich.edu return _destRegIdx[idx]; 3143770Sgblack@eecs.umich.edu } 3153770Sgblack@eecs.umich.edu 3163770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th source register. */ 3173770Sgblack@eecs.umich.edu PhysRegIndex renamedSrcRegIdx(int idx) const 3183770Sgblack@eecs.umich.edu { 3193770Sgblack@eecs.umich.edu return _srcRegIdx[idx]; 3203770Sgblack@eecs.umich.edu } 3213770Sgblack@eecs.umich.edu 3223770Sgblack@eecs.umich.edu /** Returns the flattened register index of the i'th destination 3233770Sgblack@eecs.umich.edu * register. 3243770Sgblack@eecs.umich.edu */ 3253770Sgblack@eecs.umich.edu TheISA::RegIndex flattenedDestRegIdx(int idx) const 3263770Sgblack@eecs.umich.edu { 3273770Sgblack@eecs.umich.edu return _flatDestRegIdx[idx]; 3283770Sgblack@eecs.umich.edu } 3293770Sgblack@eecs.umich.edu 3303770Sgblack@eecs.umich.edu /** Returns the flattened register index of the i'th source register */ 3313770Sgblack@eecs.umich.edu TheISA::RegIndex flattenedSrcRegIdx(int idx) const 3323770Sgblack@eecs.umich.edu { 3333770Sgblack@eecs.umich.edu return _flatSrcRegIdx[idx]; 3343770Sgblack@eecs.umich.edu } 3353770Sgblack@eecs.umich.edu 3363770Sgblack@eecs.umich.edu /** Returns the physical register index of the previous physical register 3373770Sgblack@eecs.umich.edu * that remapped to the same logical register index. 3383770Sgblack@eecs.umich.edu */ 3393770Sgblack@eecs.umich.edu PhysRegIndex prevDestRegIdx(int idx) const 3403770Sgblack@eecs.umich.edu { 3413770Sgblack@eecs.umich.edu return _prevDestRegIdx[idx]; 3423770Sgblack@eecs.umich.edu } 3433770Sgblack@eecs.umich.edu 3443770Sgblack@eecs.umich.edu /** Renames a destination register to a physical register. Also records 3453770Sgblack@eecs.umich.edu * the previous physical register that the logical register mapped to. 3463770Sgblack@eecs.umich.edu */ 3473770Sgblack@eecs.umich.edu void renameDestReg(int idx, 3483770Sgblack@eecs.umich.edu PhysRegIndex renamed_dest, 3493770Sgblack@eecs.umich.edu PhysRegIndex previous_rename) 3503770Sgblack@eecs.umich.edu { 3513770Sgblack@eecs.umich.edu _destRegIdx[idx] = renamed_dest; 3523770Sgblack@eecs.umich.edu _prevDestRegIdx[idx] = previous_rename; 3533770Sgblack@eecs.umich.edu } 3543770Sgblack@eecs.umich.edu 3553770Sgblack@eecs.umich.edu /** Renames a source logical register to the physical register which 3563770Sgblack@eecs.umich.edu * has/will produce that logical register's result. 3573770Sgblack@eecs.umich.edu * @todo: add in whether or not the source register is ready. 3583770Sgblack@eecs.umich.edu */ 3593770Sgblack@eecs.umich.edu void renameSrcReg(int idx, PhysRegIndex renamed_src) 3603770Sgblack@eecs.umich.edu { 3613770Sgblack@eecs.umich.edu _srcRegIdx[idx] = renamed_src; 3623770Sgblack@eecs.umich.edu } 3633770Sgblack@eecs.umich.edu 3643770Sgblack@eecs.umich.edu /** Flattens a source architectural register index into a logical index. 3653770Sgblack@eecs.umich.edu */ 3663770Sgblack@eecs.umich.edu void flattenSrcReg(int idx, TheISA::RegIndex flattened_src) 3673770Sgblack@eecs.umich.edu { 3683770Sgblack@eecs.umich.edu _flatSrcRegIdx[idx] = flattened_src; 3693770Sgblack@eecs.umich.edu } 3703770Sgblack@eecs.umich.edu 3713770Sgblack@eecs.umich.edu /** Flattens a destination architectural register index into a logical 3723770Sgblack@eecs.umich.edu * index. 3733770Sgblack@eecs.umich.edu */ 3743770Sgblack@eecs.umich.edu void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 3753770Sgblack@eecs.umich.edu { 3763770Sgblack@eecs.umich.edu _flatDestRegIdx[idx] = flattened_dest; 3773770Sgblack@eecs.umich.edu } 3784636Sgblack@eecs.umich.edu /** BaseDynInst constructor given a binary instruction. 3794636Sgblack@eecs.umich.edu * @param staticInst A StaticInstPtr to the underlying instruction. 3804636Sgblack@eecs.umich.edu * @param PC The PC of the instruction. 3814636Sgblack@eecs.umich.edu * @param pred_PC The predicted next PC. 3824636Sgblack@eecs.umich.edu * @param pred_NPC The predicted next NPC. 3834636Sgblack@eecs.umich.edu * @param seq_num The sequence number of the instruction. 3844636Sgblack@eecs.umich.edu * @param cpu Pointer to the instruction's CPU. 3854636Sgblack@eecs.umich.edu */ 3864636Sgblack@eecs.umich.edu BaseDynInst(StaticInstPtr staticInst, Addr PC, Addr NPC, Addr microPC, 3874636Sgblack@eecs.umich.edu Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC, 3884636Sgblack@eecs.umich.edu InstSeqNum seq_num, ImplCPU *cpu); 3893770Sgblack@eecs.umich.edu 3902292SN/A /** BaseDynInst constructor given a binary instruction. 3912292SN/A * @param inst The binary instruction. 3922292SN/A * @param PC The PC of the instruction. 3932292SN/A * @param pred_PC The predicted next PC. 3943794Sgblack@eecs.umich.edu * @param pred_NPC The predicted next NPC. 3952292SN/A * @param seq_num The sequence number of the instruction. 3962292SN/A * @param cpu Pointer to the instruction's CPU. 3972292SN/A */ 3984636Sgblack@eecs.umich.edu BaseDynInst(TheISA::ExtMachInst inst, Addr PC, Addr NPC, Addr microPC, 3994636Sgblack@eecs.umich.edu Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC, 4003770Sgblack@eecs.umich.edu InstSeqNum seq_num, ImplCPU *cpu); 4011060SN/A 4022292SN/A /** BaseDynInst constructor given a StaticInst pointer. 4032292SN/A * @param _staticInst The StaticInst for this BaseDynInst. 4042292SN/A */ 4052107SN/A BaseDynInst(StaticInstPtr &_staticInst); 4061060SN/A 4071060SN/A /** BaseDynInst destructor. */ 4081060SN/A ~BaseDynInst(); 4091060SN/A 4101464SN/A private: 4111684SN/A /** Function to initialize variables in the constructors. */ 4121464SN/A void initVars(); 4131060SN/A 4141464SN/A public: 4151060SN/A /** Dumps out contents of this BaseDynInst. */ 4161060SN/A void dump(); 4171060SN/A 4181060SN/A /** Dumps out contents of this BaseDynInst into given string. */ 4191060SN/A void dump(std::string &outstring); 4201060SN/A 4213326Sktlim@umich.edu /** Read this CPU's ID. */ 4225712Shsul@eecs.umich.edu int cpuId() { return cpu->cpuId(); } 4233326Sktlim@umich.edu 4245714Shsul@eecs.umich.edu /** Read this context's system-wide ID **/ 4255714Shsul@eecs.umich.edu int contextId() { return thread->contextId(); } 4265714Shsul@eecs.umich.edu 4271060SN/A /** Returns the fault type. */ 4282132SN/A Fault getFault() { return fault; } 4291060SN/A 4301060SN/A /** Checks whether or not this instruction has had its branch target 4311060SN/A * calculated yet. For now it is not utilized and is hacked to be 4321060SN/A * always false. 4332292SN/A * @todo: Actually use this instruction. 4341060SN/A */ 4351060SN/A bool doneTargCalc() { return false; } 4361060SN/A 4371684SN/A /** Returns the next PC. This could be the speculative next PC if it is 4381684SN/A * called prior to the actual branch target being calculated. 4391684SN/A */ 4401060SN/A Addr readNextPC() { return nextPC; } 4411060SN/A 4422935Sksewell@umich.edu /** Returns the next NPC. This could be the speculative next NPC if it is 4432935Sksewell@umich.edu * called prior to the actual branch target being calculated. 4442935Sksewell@umich.edu */ 4453965Sgblack@eecs.umich.edu Addr readNextNPC() 4463965Sgblack@eecs.umich.edu { 4473965Sgblack@eecs.umich.edu#if ISA_HAS_DELAY_SLOT 4483965Sgblack@eecs.umich.edu return nextNPC; 4493965Sgblack@eecs.umich.edu#else 4503965Sgblack@eecs.umich.edu return nextPC + sizeof(TheISA::MachInst); 4513965Sgblack@eecs.umich.edu#endif 4523965Sgblack@eecs.umich.edu } 4532935Sksewell@umich.edu 4544636Sgblack@eecs.umich.edu Addr readNextMicroPC() 4554636Sgblack@eecs.umich.edu { 4564636Sgblack@eecs.umich.edu return nextMicroPC; 4574636Sgblack@eecs.umich.edu } 4584636Sgblack@eecs.umich.edu 4591060SN/A /** Set the predicted target of this current instruction. */ 4604636Sgblack@eecs.umich.edu void setPredTarg(Addr predicted_PC, Addr predicted_NPC, 4614636Sgblack@eecs.umich.edu Addr predicted_MicroPC) 4623794Sgblack@eecs.umich.edu { 4633794Sgblack@eecs.umich.edu predPC = predicted_PC; 4643794Sgblack@eecs.umich.edu predNPC = predicted_NPC; 4654636Sgblack@eecs.umich.edu predMicroPC = predicted_MicroPC; 4663794Sgblack@eecs.umich.edu } 4671060SN/A 4683794Sgblack@eecs.umich.edu /** Returns the predicted PC immediately after the branch. */ 4693794Sgblack@eecs.umich.edu Addr readPredPC() { return predPC; } 4703794Sgblack@eecs.umich.edu 4713794Sgblack@eecs.umich.edu /** Returns the predicted PC two instructions after the branch */ 4723794Sgblack@eecs.umich.edu Addr readPredNPC() { return predNPC; } 4731060SN/A 4744636Sgblack@eecs.umich.edu /** Returns the predicted micro PC after the branch */ 4754636Sgblack@eecs.umich.edu Addr readPredMicroPC() { return predMicroPC; } 4764636Sgblack@eecs.umich.edu 4771060SN/A /** Returns whether the instruction was predicted taken or not. */ 4783794Sgblack@eecs.umich.edu bool readPredTaken() 4793794Sgblack@eecs.umich.edu { 4803794Sgblack@eecs.umich.edu return predTaken; 4813794Sgblack@eecs.umich.edu } 4823794Sgblack@eecs.umich.edu 4833794Sgblack@eecs.umich.edu void setPredTaken(bool predicted_taken) 4843794Sgblack@eecs.umich.edu { 4853794Sgblack@eecs.umich.edu predTaken = predicted_taken; 4863794Sgblack@eecs.umich.edu } 4871060SN/A 4881060SN/A /** Returns whether the instruction mispredicted. */ 4892935Sksewell@umich.edu bool mispredicted() 4903794Sgblack@eecs.umich.edu { 4913965Sgblack@eecs.umich.edu return readPredPC() != readNextPC() || 4924636Sgblack@eecs.umich.edu readPredNPC() != readNextNPC() || 4934636Sgblack@eecs.umich.edu readPredMicroPC() != readNextMicroPC(); 4943794Sgblack@eecs.umich.edu } 4953794Sgblack@eecs.umich.edu 4961060SN/A // 4971060SN/A // Instruction types. Forward checks to StaticInst object. 4981060SN/A // 4995543Ssaidi@eecs.umich.edu bool isNop() const { return staticInst->isNop(); } 5005543Ssaidi@eecs.umich.edu bool isMemRef() const { return staticInst->isMemRef(); } 5015543Ssaidi@eecs.umich.edu bool isLoad() const { return staticInst->isLoad(); } 5025543Ssaidi@eecs.umich.edu bool isStore() const { return staticInst->isStore(); } 5032336SN/A bool isStoreConditional() const 5042336SN/A { return staticInst->isStoreConditional(); } 5051060SN/A bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 5061060SN/A bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 5071060SN/A bool isCopy() const { return staticInst->isCopy(); } 5085543Ssaidi@eecs.umich.edu bool isInteger() const { return staticInst->isInteger(); } 5095543Ssaidi@eecs.umich.edu bool isFloating() const { return staticInst->isFloating(); } 5105543Ssaidi@eecs.umich.edu bool isControl() const { return staticInst->isControl(); } 5115543Ssaidi@eecs.umich.edu bool isCall() const { return staticInst->isCall(); } 5125543Ssaidi@eecs.umich.edu bool isReturn() const { return staticInst->isReturn(); } 5135543Ssaidi@eecs.umich.edu bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 5141060SN/A bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 5155543Ssaidi@eecs.umich.edu bool isCondCtrl() const { return staticInst->isCondCtrl(); } 5165543Ssaidi@eecs.umich.edu bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 5172935Sksewell@umich.edu bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 5181060SN/A bool isThreadSync() const { return staticInst->isThreadSync(); } 5191060SN/A bool isSerializing() const { return staticInst->isSerializing(); } 5202292SN/A bool isSerializeBefore() const 5212731Sktlim@umich.edu { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 5222292SN/A bool isSerializeAfter() const 5232731Sktlim@umich.edu { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 5241060SN/A bool isMemBarrier() const { return staticInst->isMemBarrier(); } 5251060SN/A bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 5261060SN/A bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 5272292SN/A bool isQuiesce() const { return staticInst->isQuiesce(); } 5282336SN/A bool isIprAccess() const { return staticInst->isIprAccess(); } 5292308SN/A bool isUnverifiable() const { return staticInst->isUnverifiable(); } 5304828Sgblack@eecs.umich.edu bool isSyscall() const { return staticInst->isSyscall(); } 5314654Sgblack@eecs.umich.edu bool isMacroop() const { return staticInst->isMacroop(); } 5324654Sgblack@eecs.umich.edu bool isMicroop() const { return staticInst->isMicroop(); } 5334636Sgblack@eecs.umich.edu bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 5344654Sgblack@eecs.umich.edu bool isLastMicroop() const { return staticInst->isLastMicroop(); } 5354654Sgblack@eecs.umich.edu bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 5364636Sgblack@eecs.umich.edu bool isMicroBranch() const { return staticInst->isMicroBranch(); } 5372292SN/A 5382292SN/A /** Temporarily sets this instruction as a serialize before instruction. */ 5392731Sktlim@umich.edu void setSerializeBefore() { status.set(SerializeBefore); } 5402292SN/A 5412292SN/A /** Clears the serializeBefore part of this instruction. */ 5422731Sktlim@umich.edu void clearSerializeBefore() { status.reset(SerializeBefore); } 5432292SN/A 5442292SN/A /** Checks if this serializeBefore is only temporarily set. */ 5452731Sktlim@umich.edu bool isTempSerializeBefore() { return status[SerializeBefore]; } 5462292SN/A 5472292SN/A /** Temporarily sets this instruction as a serialize after instruction. */ 5482731Sktlim@umich.edu void setSerializeAfter() { status.set(SerializeAfter); } 5492292SN/A 5502292SN/A /** Clears the serializeAfter part of this instruction.*/ 5512731Sktlim@umich.edu void clearSerializeAfter() { status.reset(SerializeAfter); } 5522292SN/A 5532292SN/A /** Checks if this serializeAfter is only temporarily set. */ 5542731Sktlim@umich.edu bool isTempSerializeAfter() { return status[SerializeAfter]; } 5552292SN/A 5562731Sktlim@umich.edu /** Sets the serialization part of this instruction as handled. */ 5572731Sktlim@umich.edu void setSerializeHandled() { status.set(SerializeHandled); } 5582292SN/A 5592292SN/A /** Checks if the serialization part of this instruction has been 5602292SN/A * handled. This does not apply to the temporary serializing 5612292SN/A * state; it only applies to this instruction's own permanent 5622292SN/A * serializing state. 5632292SN/A */ 5642731Sktlim@umich.edu bool isSerializeHandled() { return status[SerializeHandled]; } 5651060SN/A 5661464SN/A /** Returns the opclass of this instruction. */ 5671464SN/A OpClass opClass() const { return staticInst->opClass(); } 5681464SN/A 5691464SN/A /** Returns the branch target address. */ 5701464SN/A Addr branchTarget() const { return staticInst->branchTarget(PC); } 5711464SN/A 5722292SN/A /** Returns the number of source registers. */ 5735543Ssaidi@eecs.umich.edu int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 5741684SN/A 5752292SN/A /** Returns the number of destination registers. */ 5761060SN/A int8_t numDestRegs() const { return staticInst->numDestRegs(); } 5771060SN/A 5781060SN/A // the following are used to track physical register usage 5791060SN/A // for machines with separate int & FP reg files 5801060SN/A int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 5811060SN/A int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 5821060SN/A 5831060SN/A /** Returns the logical register index of the i'th destination register. */ 5842292SN/A RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 5851060SN/A 5861060SN/A /** Returns the logical register index of the i'th source register. */ 5872292SN/A RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 5881060SN/A 5891684SN/A /** Returns the result of an integer instruction. */ 5901464SN/A uint64_t readIntResult() { return instResult.integer; } 5911684SN/A 5921684SN/A /** Returns the result of a floating point instruction. */ 5932356SN/A float readFloatResult() { return (float)instResult.dbl; } 5941684SN/A 5951684SN/A /** Returns the result of a floating point (double) instruction. */ 5961464SN/A double readDoubleResult() { return instResult.dbl; } 5971060SN/A 5982702Sktlim@umich.edu /** Records an integer register being set to a value. */ 5993735Sstever@eecs.umich.edu void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 6001060SN/A { 6013326Sktlim@umich.edu if (recordResult) 6023326Sktlim@umich.edu instResult.integer = val; 6031060SN/A } 6041060SN/A 6052702Sktlim@umich.edu /** Records an fp register being set to a value. */ 6063735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 6073735Sstever@eecs.umich.edu int width) 6082690Sktlim@umich.edu { 6093326Sktlim@umich.edu if (recordResult) { 6103326Sktlim@umich.edu if (width == 32) 6113326Sktlim@umich.edu instResult.dbl = (double)val; 6123326Sktlim@umich.edu else if (width == 64) 6133326Sktlim@umich.edu instResult.dbl = val; 6143326Sktlim@umich.edu else 6153326Sktlim@umich.edu panic("Unsupported width!"); 6163326Sktlim@umich.edu } 6172690Sktlim@umich.edu } 6182690Sktlim@umich.edu 6192702Sktlim@umich.edu /** Records an fp register being set to a value. */ 6203735Sstever@eecs.umich.edu void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 6211060SN/A { 6223326Sktlim@umich.edu if (recordResult) 6233326Sktlim@umich.edu instResult.dbl = (double)val; 6242308SN/A } 6251060SN/A 6262702Sktlim@umich.edu /** Records an fp register being set to an integer value. */ 6273735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val, 6283735Sstever@eecs.umich.edu int width) 6292308SN/A { 6303326Sktlim@umich.edu if (recordResult) 6313326Sktlim@umich.edu instResult.integer = val; 6322308SN/A } 6331060SN/A 6342702Sktlim@umich.edu /** Records an fp register being set to an integer value. */ 6353735Sstever@eecs.umich.edu void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val) 6362308SN/A { 6373326Sktlim@umich.edu if (recordResult) 6383326Sktlim@umich.edu instResult.integer = val; 6391060SN/A } 6401060SN/A 6412190SN/A /** Records that one of the source registers is ready. */ 6422292SN/A void markSrcRegReady(); 6432190SN/A 6442331SN/A /** Marks a specific register as ready. */ 6452292SN/A void markSrcRegReady(RegIndex src_idx); 6462190SN/A 6471684SN/A /** Returns if a source register is ready. */ 6481464SN/A bool isReadySrcRegIdx(int idx) const 6491464SN/A { 6501464SN/A return this->_readySrcRegIdx[idx]; 6511464SN/A } 6521464SN/A 6531684SN/A /** Sets this instruction as completed. */ 6542731Sktlim@umich.edu void setCompleted() { status.set(Completed); } 6551464SN/A 6562292SN/A /** Returns whether or not this instruction is completed. */ 6572731Sktlim@umich.edu bool isCompleted() const { return status[Completed]; } 6581464SN/A 6592731Sktlim@umich.edu /** Marks the result as ready. */ 6602731Sktlim@umich.edu void setResultReady() { status.set(ResultReady); } 6612308SN/A 6622731Sktlim@umich.edu /** Returns whether or not the result is ready. */ 6632731Sktlim@umich.edu bool isResultReady() const { return status[ResultReady]; } 6642308SN/A 6651060SN/A /** Sets this instruction as ready to issue. */ 6662731Sktlim@umich.edu void setCanIssue() { status.set(CanIssue); } 6671060SN/A 6681060SN/A /** Returns whether or not this instruction is ready to issue. */ 6692731Sktlim@umich.edu bool readyToIssue() const { return status[CanIssue]; } 6701060SN/A 6714032Sktlim@umich.edu /** Clears this instruction being able to issue. */ 6724032Sktlim@umich.edu void clearCanIssue() { status.reset(CanIssue); } 6734032Sktlim@umich.edu 6741060SN/A /** Sets this instruction as issued from the IQ. */ 6752731Sktlim@umich.edu void setIssued() { status.set(Issued); } 6761060SN/A 6771060SN/A /** Returns whether or not this instruction has issued. */ 6782731Sktlim@umich.edu bool isIssued() const { return status[Issued]; } 6791060SN/A 6804032Sktlim@umich.edu /** Clears this instruction as being issued. */ 6814032Sktlim@umich.edu void clearIssued() { status.reset(Issued); } 6824032Sktlim@umich.edu 6831060SN/A /** Sets this instruction as executed. */ 6842731Sktlim@umich.edu void setExecuted() { status.set(Executed); } 6851060SN/A 6861060SN/A /** Returns whether or not this instruction has executed. */ 6872731Sktlim@umich.edu bool isExecuted() const { return status[Executed]; } 6881060SN/A 6891060SN/A /** Sets this instruction as ready to commit. */ 6902731Sktlim@umich.edu void setCanCommit() { status.set(CanCommit); } 6911060SN/A 6921061SN/A /** Clears this instruction as being ready to commit. */ 6932731Sktlim@umich.edu void clearCanCommit() { status.reset(CanCommit); } 6941061SN/A 6951060SN/A /** Returns whether or not this instruction is ready to commit. */ 6962731Sktlim@umich.edu bool readyToCommit() const { return status[CanCommit]; } 6972731Sktlim@umich.edu 6982731Sktlim@umich.edu void setAtCommit() { status.set(AtCommit); } 6992731Sktlim@umich.edu 7002731Sktlim@umich.edu bool isAtCommit() { return status[AtCommit]; } 7011060SN/A 7022292SN/A /** Sets this instruction as committed. */ 7032731Sktlim@umich.edu void setCommitted() { status.set(Committed); } 7042292SN/A 7052292SN/A /** Returns whether or not this instruction is committed. */ 7062731Sktlim@umich.edu bool isCommitted() const { return status[Committed]; } 7072292SN/A 7081060SN/A /** Sets this instruction as squashed. */ 7092731Sktlim@umich.edu void setSquashed() { status.set(Squashed); } 7101060SN/A 7111060SN/A /** Returns whether or not this instruction is squashed. */ 7122731Sktlim@umich.edu bool isSquashed() const { return status[Squashed]; } 7131060SN/A 7142292SN/A //Instruction Queue Entry 7152292SN/A //----------------------- 7162292SN/A /** Sets this instruction as a entry the IQ. */ 7172731Sktlim@umich.edu void setInIQ() { status.set(IqEntry); } 7182292SN/A 7192292SN/A /** Sets this instruction as a entry the IQ. */ 7202731Sktlim@umich.edu void clearInIQ() { status.reset(IqEntry); } 7212731Sktlim@umich.edu 7222731Sktlim@umich.edu /** Returns whether or not this instruction has issued. */ 7232731Sktlim@umich.edu bool isInIQ() const { return status[IqEntry]; } 7242292SN/A 7251060SN/A /** Sets this instruction as squashed in the IQ. */ 7262731Sktlim@umich.edu void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 7271060SN/A 7281060SN/A /** Returns whether or not this instruction is squashed in the IQ. */ 7292731Sktlim@umich.edu bool isSquashedInIQ() const { return status[SquashedInIQ]; } 7302292SN/A 7312292SN/A 7322292SN/A //Load / Store Queue Functions 7332292SN/A //----------------------- 7342292SN/A /** Sets this instruction as a entry the LSQ. */ 7352731Sktlim@umich.edu void setInLSQ() { status.set(LsqEntry); } 7362292SN/A 7372292SN/A /** Sets this instruction as a entry the LSQ. */ 7382731Sktlim@umich.edu void removeInLSQ() { status.reset(LsqEntry); } 7392731Sktlim@umich.edu 7402731Sktlim@umich.edu /** Returns whether or not this instruction is in the LSQ. */ 7412731Sktlim@umich.edu bool isInLSQ() const { return status[LsqEntry]; } 7422292SN/A 7432292SN/A /** Sets this instruction as squashed in the LSQ. */ 7442731Sktlim@umich.edu void setSquashedInLSQ() { status.set(SquashedInLSQ);} 7452292SN/A 7462292SN/A /** Returns whether or not this instruction is squashed in the LSQ. */ 7472731Sktlim@umich.edu bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 7482292SN/A 7492292SN/A 7502292SN/A //Reorder Buffer Functions 7512292SN/A //----------------------- 7522292SN/A /** Sets this instruction as a entry the ROB. */ 7532731Sktlim@umich.edu void setInROB() { status.set(RobEntry); } 7542292SN/A 7552292SN/A /** Sets this instruction as a entry the ROB. */ 7562731Sktlim@umich.edu void clearInROB() { status.reset(RobEntry); } 7572731Sktlim@umich.edu 7582731Sktlim@umich.edu /** Returns whether or not this instruction is in the ROB. */ 7592731Sktlim@umich.edu bool isInROB() const { return status[RobEntry]; } 7602292SN/A 7612292SN/A /** Sets this instruction as squashed in the ROB. */ 7622731Sktlim@umich.edu void setSquashedInROB() { status.set(SquashedInROB); } 7632292SN/A 7642292SN/A /** Returns whether or not this instruction is squashed in the ROB. */ 7652731Sktlim@umich.edu bool isSquashedInROB() const { return status[SquashedInROB]; } 7662292SN/A 7671060SN/A /** Read the PC of this instruction. */ 7681464SN/A const Addr readPC() const { return PC; } 7691060SN/A 7704636Sgblack@eecs.umich.edu /**Read the micro PC of this instruction. */ 7714636Sgblack@eecs.umich.edu const Addr readMicroPC() const { return microPC; } 7724636Sgblack@eecs.umich.edu 7731060SN/A /** Set the next PC of this instruction (its actual target). */ 7744636Sgblack@eecs.umich.edu void setNextPC(Addr val) 7752308SN/A { 7762308SN/A nextPC = val; 7772308SN/A } 7782190SN/A 7792935Sksewell@umich.edu /** Set the next NPC of this instruction (the target in Mips or Sparc).*/ 7804636Sgblack@eecs.umich.edu void setNextNPC(Addr val) 7812935Sksewell@umich.edu { 7824632Sgblack@eecs.umich.edu#if ISA_HAS_DELAY_SLOT 7832935Sksewell@umich.edu nextNPC = val; 7844632Sgblack@eecs.umich.edu#endif 7852935Sksewell@umich.edu } 7862935Sksewell@umich.edu 7874636Sgblack@eecs.umich.edu void setNextMicroPC(Addr val) 7884636Sgblack@eecs.umich.edu { 7894636Sgblack@eecs.umich.edu nextMicroPC = val; 7904636Sgblack@eecs.umich.edu } 7914636Sgblack@eecs.umich.edu 7922702Sktlim@umich.edu /** Sets the ASID. */ 7932292SN/A void setASID(short addr_space_id) { asid = addr_space_id; } 7942292SN/A 7952702Sktlim@umich.edu /** Sets the thread id. */ 7966221Snate@binkert.org void setTid(ThreadID tid) { threadNumber = tid; } 7972292SN/A 7982731Sktlim@umich.edu /** Sets the pointer to the thread state. */ 7992702Sktlim@umich.edu void setThreadState(ImplState *state) { thread = state; } 8001060SN/A 8012731Sktlim@umich.edu /** Returns the thread context. */ 8022680Sktlim@umich.edu ThreadContext *tcBase() { return thread->getTC(); } 8031464SN/A 8041464SN/A private: 8051684SN/A /** Instruction effective address. 8061684SN/A * @todo: Consider if this is necessary or not. 8071684SN/A */ 8081464SN/A Addr instEffAddr; 8092292SN/A 8101684SN/A /** Whether or not the effective address calculation is completed. 8111684SN/A * @todo: Consider if this is necessary or not. 8121684SN/A */ 8131464SN/A bool eaCalcDone; 8141464SN/A 8154032Sktlim@umich.edu /** Is this instruction's memory access uncacheable. */ 8164032Sktlim@umich.edu bool isUncacheable; 8174032Sktlim@umich.edu 8184032Sktlim@umich.edu /** Has this instruction generated a memory request. */ 8194032Sktlim@umich.edu bool reqMade; 8204032Sktlim@umich.edu 8211464SN/A public: 8221684SN/A /** Sets the effective address. */ 8231464SN/A void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 8241684SN/A 8251684SN/A /** Returns the effective address. */ 8261464SN/A const Addr &getEA() const { return instEffAddr; } 8271684SN/A 8281684SN/A /** Returns whether or not the eff. addr. calculation has been completed. */ 8291464SN/A bool doneEACalc() { return eaCalcDone; } 8301684SN/A 8311684SN/A /** Returns whether or not the eff. addr. source registers are ready. */ 8321464SN/A bool eaSrcsReady(); 8331681SN/A 8342292SN/A /** Whether or not the memory operation is done. */ 8352292SN/A bool memOpDone; 8362292SN/A 8374032Sktlim@umich.edu /** Is this instruction's memory access uncacheable. */ 8384032Sktlim@umich.edu bool uncacheable() { return isUncacheable; } 8394032Sktlim@umich.edu 8404032Sktlim@umich.edu /** Has this instruction generated a memory request. */ 8414032Sktlim@umich.edu bool hasRequest() { return reqMade; } 8424032Sktlim@umich.edu 8431681SN/A public: 8441684SN/A /** Load queue index. */ 8451681SN/A int16_t lqIdx; 8461684SN/A 8471684SN/A /** Store queue index. */ 8481681SN/A int16_t sqIdx; 8492292SN/A 8502292SN/A /** Iterator pointing to this BaseDynInst in the list of all insts. */ 8512292SN/A ListIt instListIt; 8522292SN/A 8532292SN/A /** Returns iterator to this instruction in the list of all insts. */ 8542292SN/A ListIt &getInstListIt() { return instListIt; } 8552292SN/A 8562292SN/A /** Sets iterator for this instruction in the list of all insts. */ 8572292SN/A void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 8583326Sktlim@umich.edu 8593326Sktlim@umich.edu public: 8603326Sktlim@umich.edu /** Returns the number of consecutive store conditional failures. */ 8613326Sktlim@umich.edu unsigned readStCondFailures() 8623326Sktlim@umich.edu { return thread->storeCondFailures; } 8633326Sktlim@umich.edu 8643326Sktlim@umich.edu /** Sets the number of consecutive store conditional failures. */ 8653326Sktlim@umich.edu void setStCondFailures(unsigned sc_failures) 8663326Sktlim@umich.edu { thread->storeCondFailures = sc_failures; } 8671060SN/A}; 8681060SN/A 8691060SN/Atemplate<class Impl> 8701060SN/Atemplate<class T> 8712132SN/Ainline Fault 8721060SN/ABaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) 8731060SN/A{ 8744032Sktlim@umich.edu reqMade = true; 8756429Ssteve.reinhardt@amd.com Request *req = new Request(asid, addr, sizeof(T), flags, this->PC, 8766429Ssteve.reinhardt@amd.com thread->contextId(), threadNumber); 8772292SN/A 8786974Stjones1@inf.ed.ac.uk Request *sreqLow = NULL; 8796974Stjones1@inf.ed.ac.uk Request *sreqHigh = NULL; 8806974Stjones1@inf.ed.ac.uk 8816974Stjones1@inf.ed.ac.uk // Only split the request if the ISA supports unaligned accesses. 8826974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc) { 8836974Stjones1@inf.ed.ac.uk splitRequest(req, sreqLow, sreqHigh); 8846974Stjones1@inf.ed.ac.uk } 8856974Stjones1@inf.ed.ac.uk initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read); 8864032Sktlim@umich.edu 8872678Sktlim@umich.edu if (fault == NoFault) { 8882678Sktlim@umich.edu effAddr = req->getVaddr(); 8894032Sktlim@umich.edu effAddrValid = true; 8906975Stjones1@inf.ed.ac.uk fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx); 8916973Stjones1@inf.ed.ac.uk } else { 8921060SN/A 8931060SN/A // Return a fixed value to keep simulation deterministic even 8941060SN/A // along misspeculated paths. 8951060SN/A data = (T)-1; 8962292SN/A 8972292SN/A // Commit will have to clean up whatever happened. Set this 8982292SN/A // instruction as executed. 8992292SN/A this->setExecuted(); 9001060SN/A } 9011060SN/A 9021060SN/A if (traceData) { 9031060SN/A traceData->setAddr(addr); 9041060SN/A traceData->setData(data); 9051060SN/A } 9061060SN/A 9071060SN/A return fault; 9081060SN/A} 9091060SN/A 9101060SN/Atemplate<class Impl> 9111060SN/Atemplate<class T> 9122132SN/Ainline Fault 9131060SN/ABaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) 9141060SN/A{ 9151060SN/A if (traceData) { 9161060SN/A traceData->setAddr(addr); 9171060SN/A traceData->setData(data); 9181060SN/A } 9191060SN/A 9204032Sktlim@umich.edu reqMade = true; 9216429Ssteve.reinhardt@amd.com Request *req = new Request(asid, addr, sizeof(T), flags, this->PC, 9226429Ssteve.reinhardt@amd.com thread->contextId(), threadNumber); 9231060SN/A 9246974Stjones1@inf.ed.ac.uk Request *sreqLow = NULL; 9256974Stjones1@inf.ed.ac.uk Request *sreqHigh = NULL; 9266974Stjones1@inf.ed.ac.uk 9276974Stjones1@inf.ed.ac.uk // Only split the request if the ISA supports unaligned accesses. 9286974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc) { 9296974Stjones1@inf.ed.ac.uk splitRequest(req, sreqLow, sreqHigh); 9306974Stjones1@inf.ed.ac.uk } 9316974Stjones1@inf.ed.ac.uk initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write); 9324032Sktlim@umich.edu 9332090SN/A if (fault == NoFault) { 9342678Sktlim@umich.edu effAddr = req->getVaddr(); 9354032Sktlim@umich.edu effAddrValid = true; 9366975Stjones1@inf.ed.ac.uk fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx); 9371060SN/A } 9381060SN/A 9391060SN/A return fault; 9401060SN/A} 9411060SN/A 9426973Stjones1@inf.ed.ac.uktemplate<class Impl> 9436973Stjones1@inf.ed.ac.ukinline void 9446974Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow, 9456974Stjones1@inf.ed.ac.uk RequestPtr &sreqHigh) 9466974Stjones1@inf.ed.ac.uk{ 9476974Stjones1@inf.ed.ac.uk // Check to see if the request crosses the next level block boundary. 9486974Stjones1@inf.ed.ac.uk unsigned block_size = cpu->getDcachePort()->peerBlockSize(); 9496974Stjones1@inf.ed.ac.uk Addr addr = req->getVaddr(); 9506974Stjones1@inf.ed.ac.uk Addr split_addr = roundDown(addr + req->getSize() - 1, block_size); 9516974Stjones1@inf.ed.ac.uk assert(split_addr <= addr || split_addr - addr < block_size); 9526974Stjones1@inf.ed.ac.uk 9536974Stjones1@inf.ed.ac.uk // Spans two blocks. 9546974Stjones1@inf.ed.ac.uk if (split_addr > addr) { 9556974Stjones1@inf.ed.ac.uk req->splitOnVaddr(split_addr, sreqLow, sreqHigh); 9566974Stjones1@inf.ed.ac.uk } 9576974Stjones1@inf.ed.ac.uk} 9586974Stjones1@inf.ed.ac.uk 9596974Stjones1@inf.ed.ac.uktemplate<class Impl> 9606974Stjones1@inf.ed.ac.ukinline void 9616974Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow, 9626974Stjones1@inf.ed.ac.uk RequestPtr sreqHigh, uint64_t *res, 9636973Stjones1@inf.ed.ac.uk BaseTLB::Mode mode) 9646973Stjones1@inf.ed.ac.uk{ 9656974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) { 9666974Stjones1@inf.ed.ac.uk WholeTranslationState *state = 9676974Stjones1@inf.ed.ac.uk new WholeTranslationState(req, NULL, res, mode); 9686974Stjones1@inf.ed.ac.uk 9696974Stjones1@inf.ed.ac.uk // One translation if the request isn't split. 9706974Stjones1@inf.ed.ac.uk DataTranslation<BaseDynInst<Impl> > *trans = 9716974Stjones1@inf.ed.ac.uk new DataTranslation<BaseDynInst<Impl> >(this, state); 9726974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(req, thread->getTC(), trans, mode); 9736974Stjones1@inf.ed.ac.uk } else { 9746974Stjones1@inf.ed.ac.uk WholeTranslationState *state = 9756974Stjones1@inf.ed.ac.uk new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode); 9766974Stjones1@inf.ed.ac.uk 9776974Stjones1@inf.ed.ac.uk // Two translations when the request is split. 9786974Stjones1@inf.ed.ac.uk DataTranslation<BaseDynInst<Impl> > *stransLow = 9796974Stjones1@inf.ed.ac.uk new DataTranslation<BaseDynInst<Impl> >(this, state, 0); 9806974Stjones1@inf.ed.ac.uk DataTranslation<BaseDynInst<Impl> > *stransHigh = 9816974Stjones1@inf.ed.ac.uk new DataTranslation<BaseDynInst<Impl> >(this, state, 1); 9826974Stjones1@inf.ed.ac.uk 9836974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode); 9846974Stjones1@inf.ed.ac.uk cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode); 9856974Stjones1@inf.ed.ac.uk } 9866973Stjones1@inf.ed.ac.uk} 9876973Stjones1@inf.ed.ac.uk 9886973Stjones1@inf.ed.ac.uktemplate<class Impl> 9896973Stjones1@inf.ed.ac.ukinline void 9906973Stjones1@inf.ed.ac.ukBaseDynInst<Impl>::finishTranslation(WholeTranslationState *state) 9916973Stjones1@inf.ed.ac.uk{ 9926973Stjones1@inf.ed.ac.uk fault = state->getFault(); 9936973Stjones1@inf.ed.ac.uk 9946973Stjones1@inf.ed.ac.uk if (state->isUncacheable()) 9956973Stjones1@inf.ed.ac.uk isUncacheable = true; 9966973Stjones1@inf.ed.ac.uk 9976973Stjones1@inf.ed.ac.uk if (fault == NoFault) { 9986973Stjones1@inf.ed.ac.uk physEffAddr = state->getPaddr(); 9996973Stjones1@inf.ed.ac.uk memReqFlags = state->getFlags(); 10006973Stjones1@inf.ed.ac.uk 10016973Stjones1@inf.ed.ac.uk if (state->mainReq->isCondSwap()) { 10026973Stjones1@inf.ed.ac.uk assert(state->res); 10036973Stjones1@inf.ed.ac.uk state->mainReq->setExtraData(*state->res); 10046973Stjones1@inf.ed.ac.uk } 10056973Stjones1@inf.ed.ac.uk 10066973Stjones1@inf.ed.ac.uk } else { 10076973Stjones1@inf.ed.ac.uk state->deleteReqs(); 10086973Stjones1@inf.ed.ac.uk } 10096973Stjones1@inf.ed.ac.uk delete state; 10106973Stjones1@inf.ed.ac.uk} 10116973Stjones1@inf.ed.ac.uk 10121464SN/A#endif // __CPU_BASE_DYN_INST_HH__ 1013