base_dyn_inst.hh revision 2669
11060SN/A/* 21762SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 31060SN/A * All rights reserved. 41060SN/A * 51060SN/A * Redistribution and use in source and binary forms, with or without 61060SN/A * modification, are permitted provided that the following conditions are 71060SN/A * met: redistributions of source code must retain the above copyright 81060SN/A * notice, this list of conditions and the following disclaimer; 91060SN/A * redistributions in binary form must reproduce the above copyright 101060SN/A * notice, this list of conditions and the following disclaimer in the 111060SN/A * documentation and/or other materials provided with the distribution; 121060SN/A * neither the name of the copyright holders nor the names of its 131060SN/A * contributors may be used to endorse or promote products derived from 141060SN/A * this software without specific prior written permission. 151060SN/A * 161060SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171060SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181060SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191060SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211060SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221060SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241060SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251060SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261060SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 271060SN/A */ 281060SN/A 291464SN/A#ifndef __CPU_BASE_DYN_INST_HH__ 301464SN/A#define __CPU_BASE_DYN_INST_HH__ 311060SN/A 322292SN/A#include <list> 331464SN/A#include <string> 341060SN/A 352669Sktlim@umich.edu#include "arch/faults.hh" 361060SN/A#include "base/fast_alloc.hh" 371060SN/A#include "base/trace.hh" 381858SN/A#include "config/full_system.hh" 391464SN/A#include "cpu/exetrace.hh" 401464SN/A#include "cpu/inst_seq.hh" 412669Sktlim@umich.edu#include "cpu/op_class.hh" 421060SN/A#include "cpu/static_inst.hh" 432669Sktlim@umich.edu#include "mem/packet.hh" 442292SN/A#include "sim/system.hh" 452292SN/A/* 461717SN/A#include "encumbered/cpu/full/bpred_update.hh" 471717SN/A#include "encumbered/cpu/full/spec_memory.hh" 481717SN/A#include "encumbered/cpu/full/spec_state.hh" 491717SN/A#include "encumbered/mem/functional/main.hh" 502292SN/A*/ 511060SN/A 521060SN/A/** 531060SN/A * @file 541060SN/A * Defines a dynamic instruction context. 551060SN/A */ 561060SN/A 571061SN/A// Forward declaration. 581061SN/Aclass StaticInstPtr; 591060SN/A 601060SN/Atemplate <class Impl> 611061SN/Aclass BaseDynInst : public FastAlloc, public RefCounted 621060SN/A{ 631060SN/A public: 641060SN/A // Typedef for the CPU. 651060SN/A typedef typename Impl::FullCPU FullCPU; 662292SN/A typedef typename FullCPU::ImplState ImplState; 671060SN/A 682292SN/A // Binary machine instruction type. 692107SN/A typedef TheISA::MachInst MachInst; 702292SN/A // Extended machine instruction type 712292SN/A typedef TheISA::ExtMachInst ExtMachInst; 722292SN/A // Logical register index type. 732107SN/A typedef TheISA::RegIndex RegIndex; 742292SN/A // Integer register index type. 752107SN/A typedef TheISA::IntReg IntReg; 761060SN/A 772292SN/A // The DynInstPtr type. 782292SN/A typedef typename Impl::DynInstPtr DynInstPtr; 792292SN/A 802292SN/A // The list of instructions iterator type. 812292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 822292SN/A 831060SN/A enum { 842292SN/A MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 852292SN/A MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs 861060SN/A }; 871060SN/A 882292SN/A /** The StaticInst used by this BaseDynInst. */ 892107SN/A StaticInstPtr staticInst; 901060SN/A 911060SN/A //////////////////////////////////////////// 921060SN/A // 931060SN/A // INSTRUCTION EXECUTION 941060SN/A // 951060SN/A //////////////////////////////////////////// 962292SN/A /** InstRecord that tracks this instructions. */ 971060SN/A Trace::InstRecord *traceData; 981060SN/A 992292SN/A /** 1002292SN/A * Does a read to a given address. 1012292SN/A * @param addr The address to read. 1022292SN/A * @param data The read's data is written into this parameter. 1032292SN/A * @param flags The request's flags. 1042292SN/A * @return Returns any fault due to the read. 1052292SN/A */ 1061060SN/A template <class T> 1072132SN/A Fault read(Addr addr, T &data, unsigned flags); 1081060SN/A 1092292SN/A /** 1102292SN/A * Does a write to a given address. 1112292SN/A * @param data The data to be written. 1122292SN/A * @param addr The address to write to. 1132292SN/A * @param flags The request's flags. 1142292SN/A * @param res The result of the write (for load locked/store conditionals). 1152292SN/A * @return Returns any fault due to the write. 1162292SN/A */ 1171060SN/A template <class T> 1182132SN/A Fault write(T data, Addr addr, unsigned flags, 1191060SN/A uint64_t *res); 1201060SN/A 1211060SN/A void prefetch(Addr addr, unsigned flags); 1221060SN/A void writeHint(Addr addr, int size, unsigned flags); 1232132SN/A Fault copySrcTranslate(Addr src); 1242132SN/A Fault copy(Addr dest); 1251060SN/A 1261684SN/A /** @todo: Consider making this private. */ 1271060SN/A public: 1281060SN/A /** The sequence number of the instruction. */ 1291060SN/A InstSeqNum seqNum; 1301060SN/A 1312292SN/A /** Is the instruction in the IQ */ 1322292SN/A bool iqEntry; 1332292SN/A 1342292SN/A /** Is the instruction in the ROB */ 1352292SN/A bool robEntry; 1362292SN/A 1372292SN/A /** Is the instruction in the LSQ */ 1382292SN/A bool lsqEntry; 1391060SN/A 1401464SN/A /** Is the instruction completed. */ 1411464SN/A bool completed; 1421464SN/A 1432308SN/A /** Is the instruction's result ready. */ 1442308SN/A bool resultReady; 1452308SN/A 1461060SN/A /** Can this instruction issue. */ 1471060SN/A bool canIssue; 1481060SN/A 1491060SN/A /** Has this instruction issued. */ 1501060SN/A bool issued; 1511060SN/A 1521060SN/A /** Has this instruction executed (or made it through execute) yet. */ 1531060SN/A bool executed; 1541060SN/A 1551060SN/A /** Can this instruction commit. */ 1561060SN/A bool canCommit; 1571060SN/A 1582292SN/A /** Is this instruction committed. */ 1592292SN/A bool committed; 1602292SN/A 1611060SN/A /** Is this instruction squashed. */ 1621060SN/A bool squashed; 1631060SN/A 1641060SN/A /** Is this instruction squashed in the instruction queue. */ 1651060SN/A bool squashedInIQ; 1661060SN/A 1672292SN/A /** Is this instruction squashed in the instruction queue. */ 1682292SN/A bool squashedInLSQ; 1692292SN/A 1702292SN/A /** Is this instruction squashed in the instruction queue. */ 1712292SN/A bool squashedInROB; 1722292SN/A 1731060SN/A /** Is this a recover instruction. */ 1741060SN/A bool recoverInst; 1751060SN/A 1761060SN/A /** Is this a thread blocking instruction. */ 1771060SN/A bool blockingInst; /* this inst has called thread_block() */ 1781060SN/A 1791060SN/A /** Is this a thread syncrhonization instruction. */ 1801060SN/A bool threadsyncWait; 1811060SN/A 1821060SN/A /** The thread this instruction is from. */ 1831060SN/A short threadNumber; 1841060SN/A 1851060SN/A /** data address space ID, for loads & stores. */ 1861060SN/A short asid; 1871060SN/A 1882292SN/A /** How many source registers are ready. */ 1892292SN/A unsigned readyRegs; 1902292SN/A 1911060SN/A /** Pointer to the FullCPU object. */ 1921060SN/A FullCPU *cpu; 1931060SN/A 1942308SN/A /** Pointer to the exec context. */ 1952292SN/A ImplState *thread; 1961060SN/A 1971060SN/A /** The kind of fault this instruction has generated. */ 1982132SN/A Fault fault; 1991060SN/A 2002292SN/A /** The memory request. */ 2012669Sktlim@umich.edu// MemReqPtr req; 2022669Sktlim@umich.edu Request *req; 2032669Sktlim@umich.edu// Packet pkt; 2042669Sktlim@umich.edu 2052669Sktlim@umich.edu uint8_t *memData; 2062292SN/A 2071060SN/A /** The effective virtual address (lds & stores only). */ 2081060SN/A Addr effAddr; 2091060SN/A 2101060SN/A /** The effective physical address. */ 2111060SN/A Addr physEffAddr; 2121060SN/A 2131060SN/A /** Effective virtual address for a copy source. */ 2141060SN/A Addr copySrcEffAddr; 2151060SN/A 2161060SN/A /** Effective physical address for a copy source. */ 2171060SN/A Addr copySrcPhysEffAddr; 2181060SN/A 2191060SN/A /** The memory request flags (from translation). */ 2201060SN/A unsigned memReqFlags; 2211060SN/A 2221060SN/A /** The size of the data to be stored. */ 2231060SN/A int storeSize; 2241060SN/A 2251060SN/A /** The data to be stored. */ 2261060SN/A IntReg storeData; 2271060SN/A 2281464SN/A union Result { 2291464SN/A uint64_t integer; 2301464SN/A float fp; 2311464SN/A double dbl; 2321464SN/A }; 2331060SN/A 2341464SN/A /** The result of the instruction; assumes for now that there's only one 2351464SN/A * destination register. 2361464SN/A */ 2371464SN/A Result instResult; 2381060SN/A 2391060SN/A /** PC of this instruction. */ 2401060SN/A Addr PC; 2411060SN/A 2421060SN/A /** Next non-speculative PC. It is not filled in at fetch, but rather 2431060SN/A * once the target of the branch is truly known (either decode or 2441060SN/A * execute). 2451060SN/A */ 2461060SN/A Addr nextPC; 2471060SN/A 2481060SN/A /** Predicted next PC. */ 2491060SN/A Addr predPC; 2501060SN/A 2511060SN/A /** Count of total number of dynamic instructions. */ 2521060SN/A static int instcount; 2531060SN/A 2542292SN/A#ifdef DEBUG 2552292SN/A void dumpSNList(); 2562292SN/A#endif 2572292SN/A 2582292SN/A /** Whether or not the source register is ready. 2592292SN/A * @todo: Not sure this should be here vs the derived class. 2601060SN/A */ 2611060SN/A bool _readySrcRegIdx[MaxInstSrcRegs]; 2621060SN/A 2631060SN/A public: 2642292SN/A /** BaseDynInst constructor given a binary instruction. 2652292SN/A * @param inst The binary instruction. 2662292SN/A * @param PC The PC of the instruction. 2672292SN/A * @param pred_PC The predicted next PC. 2682292SN/A * @param seq_num The sequence number of the instruction. 2692292SN/A * @param cpu Pointer to the instruction's CPU. 2702292SN/A */ 2712292SN/A BaseDynInst(ExtMachInst inst, Addr PC, Addr pred_PC, InstSeqNum seq_num, 2721060SN/A FullCPU *cpu); 2731060SN/A 2742292SN/A /** BaseDynInst constructor given a StaticInst pointer. 2752292SN/A * @param _staticInst The StaticInst for this BaseDynInst. 2762292SN/A */ 2772107SN/A BaseDynInst(StaticInstPtr &_staticInst); 2781060SN/A 2791060SN/A /** BaseDynInst destructor. */ 2801060SN/A ~BaseDynInst(); 2811060SN/A 2821464SN/A private: 2831684SN/A /** Function to initialize variables in the constructors. */ 2841464SN/A void initVars(); 2851060SN/A 2861464SN/A public: 2872292SN/A /** 2882292SN/A * @todo: Make this function work; currently it is a dummy function. 2892292SN/A * @param fault Last fault. 2902292SN/A * @param cmd Last command. 2912292SN/A * @param addr Virtual address of access. 2922292SN/A * @param p Memory accessed. 2932292SN/A * @param nbytes Access size. 2942292SN/A */ 2952669Sktlim@umich.edu// void 2962669Sktlim@umich.edu// trace_mem(Fault fault, 2972669Sktlim@umich.edu// MemCmd cmd, 2982669Sktlim@umich.edu// Addr addr, 2992669Sktlim@umich.edu// void *p, 3002669Sktlim@umich.edu// int nbytes); 3011060SN/A 3021060SN/A /** Dumps out contents of this BaseDynInst. */ 3031060SN/A void dump(); 3041060SN/A 3051060SN/A /** Dumps out contents of this BaseDynInst into given string. */ 3061060SN/A void dump(std::string &outstring); 3071060SN/A 3081060SN/A /** Returns the fault type. */ 3092132SN/A Fault getFault() { return fault; } 3101060SN/A 3111060SN/A /** Checks whether or not this instruction has had its branch target 3121060SN/A * calculated yet. For now it is not utilized and is hacked to be 3131060SN/A * always false. 3142292SN/A * @todo: Actually use this instruction. 3151060SN/A */ 3161060SN/A bool doneTargCalc() { return false; } 3171060SN/A 3181684SN/A /** Returns the next PC. This could be the speculative next PC if it is 3191684SN/A * called prior to the actual branch target being calculated. 3201684SN/A */ 3211060SN/A Addr readNextPC() { return nextPC; } 3221060SN/A 3231060SN/A /** Set the predicted target of this current instruction. */ 3241060SN/A void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; } 3251060SN/A 3261060SN/A /** Returns the predicted target of the branch. */ 3271060SN/A Addr readPredTarg() { return predPC; } 3281060SN/A 3291060SN/A /** Returns whether the instruction was predicted taken or not. */ 3302292SN/A bool predTaken() { return predPC != (PC + sizeof(MachInst)); } 3311060SN/A 3321060SN/A /** Returns whether the instruction mispredicted. */ 3332292SN/A bool mispredicted() { return predPC != nextPC; } 3341060SN/A 3351060SN/A // 3361060SN/A // Instruction types. Forward checks to StaticInst object. 3371060SN/A // 3381060SN/A bool isNop() const { return staticInst->isNop(); } 3391060SN/A bool isMemRef() const { return staticInst->isMemRef(); } 3401060SN/A bool isLoad() const { return staticInst->isLoad(); } 3411060SN/A bool isStore() const { return staticInst->isStore(); } 3422336SN/A bool isStoreConditional() const 3432336SN/A { return staticInst->isStoreConditional(); } 3441060SN/A bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 3451060SN/A bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 3461060SN/A bool isCopy() const { return staticInst->isCopy(); } 3471060SN/A bool isInteger() const { return staticInst->isInteger(); } 3481060SN/A bool isFloating() const { return staticInst->isFloating(); } 3491060SN/A bool isControl() const { return staticInst->isControl(); } 3501060SN/A bool isCall() const { return staticInst->isCall(); } 3511060SN/A bool isReturn() const { return staticInst->isReturn(); } 3521060SN/A bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 3531060SN/A bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 3541060SN/A bool isCondCtrl() const { return staticInst->isCondCtrl(); } 3551060SN/A bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 3561060SN/A bool isThreadSync() const { return staticInst->isThreadSync(); } 3571060SN/A bool isSerializing() const { return staticInst->isSerializing(); } 3582292SN/A bool isSerializeBefore() const 3592292SN/A { return staticInst->isSerializeBefore() || serializeBefore; } 3602292SN/A bool isSerializeAfter() const 3612292SN/A { return staticInst->isSerializeAfter() || serializeAfter; } 3621060SN/A bool isMemBarrier() const { return staticInst->isMemBarrier(); } 3631060SN/A bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 3641060SN/A bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 3652292SN/A bool isQuiesce() const { return staticInst->isQuiesce(); } 3662336SN/A bool isIprAccess() const { return staticInst->isIprAccess(); } 3672308SN/A bool isUnverifiable() const { return staticInst->isUnverifiable(); } 3682292SN/A 3692292SN/A /** Temporarily sets this instruction as a serialize before instruction. */ 3702292SN/A void setSerializeBefore() { serializeBefore = true; } 3712292SN/A 3722292SN/A /** Clears the serializeBefore part of this instruction. */ 3732292SN/A void clearSerializeBefore() { serializeBefore = false; } 3742292SN/A 3752292SN/A /** Checks if this serializeBefore is only temporarily set. */ 3762292SN/A bool isTempSerializeBefore() { return serializeBefore; } 3772292SN/A 3782292SN/A /** Tracks if instruction has been externally set as serializeBefore. */ 3792292SN/A bool serializeBefore; 3802292SN/A 3812292SN/A /** Temporarily sets this instruction as a serialize after instruction. */ 3822292SN/A void setSerializeAfter() { serializeAfter = true; } 3832292SN/A 3842292SN/A /** Clears the serializeAfter part of this instruction.*/ 3852292SN/A void clearSerializeAfter() { serializeAfter = false; } 3862292SN/A 3872292SN/A /** Checks if this serializeAfter is only temporarily set. */ 3882292SN/A bool isTempSerializeAfter() { return serializeAfter; } 3892292SN/A 3902292SN/A /** Tracks if instruction has been externally set as serializeAfter. */ 3912292SN/A bool serializeAfter; 3922292SN/A 3932292SN/A /** Checks if the serialization part of this instruction has been 3942292SN/A * handled. This does not apply to the temporary serializing 3952292SN/A * state; it only applies to this instruction's own permanent 3962292SN/A * serializing state. 3972292SN/A */ 3982292SN/A bool isSerializeHandled() { return serializeHandled; } 3992292SN/A 4002292SN/A /** Sets the serialization part of this instruction as handled. */ 4012292SN/A void setSerializeHandled() { serializeHandled = true; } 4022292SN/A 4032292SN/A /** Whether or not the serialization of this instruction has been handled. */ 4042292SN/A bool serializeHandled; 4051060SN/A 4061464SN/A /** Returns the opclass of this instruction. */ 4071464SN/A OpClass opClass() const { return staticInst->opClass(); } 4081464SN/A 4091464SN/A /** Returns the branch target address. */ 4101464SN/A Addr branchTarget() const { return staticInst->branchTarget(PC); } 4111464SN/A 4122292SN/A /** Returns the number of source registers. */ 4132292SN/A int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 4141684SN/A 4152292SN/A /** Returns the number of destination registers. */ 4161060SN/A int8_t numDestRegs() const { return staticInst->numDestRegs(); } 4171060SN/A 4181060SN/A // the following are used to track physical register usage 4191060SN/A // for machines with separate int & FP reg files 4201060SN/A int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 4211060SN/A int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 4221060SN/A 4231060SN/A /** Returns the logical register index of the i'th destination register. */ 4242292SN/A RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 4251060SN/A 4261060SN/A /** Returns the logical register index of the i'th source register. */ 4272292SN/A RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 4281060SN/A 4291684SN/A /** Returns the result of an integer instruction. */ 4301464SN/A uint64_t readIntResult() { return instResult.integer; } 4311684SN/A 4321684SN/A /** Returns the result of a floating point instruction. */ 4331464SN/A float readFloatResult() { return instResult.fp; } 4341684SN/A 4351684SN/A /** Returns the result of a floating point (double) instruction. */ 4361464SN/A double readDoubleResult() { return instResult.dbl; } 4371060SN/A 4382308SN/A void setIntReg(const StaticInst *si, int idx, uint64_t val) 4391060SN/A { 4402308SN/A instResult.integer = val; 4411060SN/A } 4421060SN/A 4432308SN/A void setFloatRegSingle(const StaticInst *si, int idx, float val) 4441060SN/A { 4452308SN/A instResult.fp = val; 4462308SN/A } 4471060SN/A 4482308SN/A void setFloatRegDouble(const StaticInst *si, int idx, double val) 4492308SN/A { 4502308SN/A instResult.dbl = val; 4512308SN/A } 4521060SN/A 4532308SN/A void setFloatRegInt(const StaticInst *si, int idx, uint64_t val) 4542308SN/A { 4552308SN/A instResult.integer = val; 4561060SN/A } 4571060SN/A 4582190SN/A /** Records that one of the source registers is ready. */ 4592292SN/A void markSrcRegReady(); 4602190SN/A 4612331SN/A /** Marks a specific register as ready. */ 4622292SN/A void markSrcRegReady(RegIndex src_idx); 4632190SN/A 4641684SN/A /** Returns if a source register is ready. */ 4651464SN/A bool isReadySrcRegIdx(int idx) const 4661464SN/A { 4671464SN/A return this->_readySrcRegIdx[idx]; 4681464SN/A } 4691464SN/A 4701684SN/A /** Sets this instruction as completed. */ 4711464SN/A void setCompleted() { completed = true; } 4721464SN/A 4732292SN/A /** Returns whether or not this instruction is completed. */ 4741464SN/A bool isCompleted() const { return completed; } 4751464SN/A 4762308SN/A void setResultReady() { resultReady = true; } 4772308SN/A 4782308SN/A bool isResultReady() const { return resultReady; } 4792308SN/A 4801060SN/A /** Sets this instruction as ready to issue. */ 4811060SN/A void setCanIssue() { canIssue = true; } 4821060SN/A 4831060SN/A /** Returns whether or not this instruction is ready to issue. */ 4841060SN/A bool readyToIssue() const { return canIssue; } 4851060SN/A 4861060SN/A /** Sets this instruction as issued from the IQ. */ 4871060SN/A void setIssued() { issued = true; } 4881060SN/A 4891060SN/A /** Returns whether or not this instruction has issued. */ 4901464SN/A bool isIssued() const { return issued; } 4911060SN/A 4921060SN/A /** Sets this instruction as executed. */ 4931060SN/A void setExecuted() { executed = true; } 4941060SN/A 4951060SN/A /** Returns whether or not this instruction has executed. */ 4961464SN/A bool isExecuted() const { return executed; } 4971060SN/A 4981060SN/A /** Sets this instruction as ready to commit. */ 4991060SN/A void setCanCommit() { canCommit = true; } 5001060SN/A 5011061SN/A /** Clears this instruction as being ready to commit. */ 5021061SN/A void clearCanCommit() { canCommit = false; } 5031061SN/A 5041060SN/A /** Returns whether or not this instruction is ready to commit. */ 5051060SN/A bool readyToCommit() const { return canCommit; } 5061060SN/A 5072292SN/A /** Sets this instruction as committed. */ 5082292SN/A void setCommitted() { committed = true; } 5092292SN/A 5102292SN/A /** Returns whether or not this instruction is committed. */ 5112292SN/A bool isCommitted() const { return committed; } 5122292SN/A 5131060SN/A /** Sets this instruction as squashed. */ 5141060SN/A void setSquashed() { squashed = true; } 5151060SN/A 5161060SN/A /** Returns whether or not this instruction is squashed. */ 5171060SN/A bool isSquashed() const { return squashed; } 5181060SN/A 5192292SN/A //Instruction Queue Entry 5202292SN/A //----------------------- 5212292SN/A /** Sets this instruction as a entry the IQ. */ 5222292SN/A void setInIQ() { iqEntry = true; } 5232292SN/A 5242292SN/A /** Sets this instruction as a entry the IQ. */ 5252292SN/A void removeInIQ() { iqEntry = false; } 5262292SN/A 5271060SN/A /** Sets this instruction as squashed in the IQ. */ 5282292SN/A void setSquashedInIQ() { squashedInIQ = true; squashed = true;} 5291060SN/A 5301060SN/A /** Returns whether or not this instruction is squashed in the IQ. */ 5311464SN/A bool isSquashedInIQ() const { return squashedInIQ; } 5321060SN/A 5332292SN/A /** Returns whether or not this instruction has issued. */ 5342292SN/A bool isInIQ() const { return iqEntry; } 5352292SN/A 5362292SN/A 5372292SN/A //Load / Store Queue Functions 5382292SN/A //----------------------- 5392292SN/A /** Sets this instruction as a entry the LSQ. */ 5402292SN/A void setInLSQ() { lsqEntry = true; } 5412292SN/A 5422292SN/A /** Sets this instruction as a entry the LSQ. */ 5432292SN/A void removeInLSQ() { lsqEntry = false; } 5442292SN/A 5452292SN/A /** Sets this instruction as squashed in the LSQ. */ 5462292SN/A void setSquashedInLSQ() { squashedInLSQ = true;} 5472292SN/A 5482292SN/A /** Returns whether or not this instruction is squashed in the LSQ. */ 5492292SN/A bool isSquashedInLSQ() const { return squashedInLSQ; } 5502292SN/A 5512292SN/A /** Returns whether or not this instruction is in the LSQ. */ 5522292SN/A bool isInLSQ() const { return lsqEntry; } 5532292SN/A 5542292SN/A 5552292SN/A //Reorder Buffer Functions 5562292SN/A //----------------------- 5572292SN/A /** Sets this instruction as a entry the ROB. */ 5582292SN/A void setInROB() { robEntry = true; } 5592292SN/A 5602292SN/A /** Sets this instruction as a entry the ROB. */ 5612292SN/A void removeInROB() { robEntry = false; } 5622292SN/A 5632292SN/A /** Sets this instruction as squashed in the ROB. */ 5642292SN/A void setSquashedInROB() { squashedInROB = true; } 5652292SN/A 5662292SN/A /** Returns whether or not this instruction is squashed in the ROB. */ 5672292SN/A bool isSquashedInROB() const { return squashedInROB; } 5682292SN/A 5692292SN/A /** Returns whether or not this instruction is in the ROB. */ 5702292SN/A bool isInROB() const { return robEntry; } 5712292SN/A 5721060SN/A /** Read the PC of this instruction. */ 5731464SN/A const Addr readPC() const { return PC; } 5741060SN/A 5751060SN/A /** Set the next PC of this instruction (its actual target). */ 5762308SN/A void setNextPC(uint64_t val) 5772308SN/A { 5782308SN/A nextPC = val; 5792308SN/A// instResult.integer = val; 5802308SN/A } 5812190SN/A 5822292SN/A void setASID(short addr_space_id) { asid = addr_space_id; } 5832292SN/A 5842292SN/A void setThread(unsigned tid) { threadNumber = tid; } 5852292SN/A 5862292SN/A void setState(ImplState *state) { thread = state; } 5871060SN/A 5881684SN/A /** Returns the exec context. 5891684SN/A * @todo: Remove this once the ExecContext is no longer used. 5901684SN/A */ 5912292SN/A ExecContext *xcBase() { return thread->getXCProxy(); } 5921464SN/A 5931464SN/A private: 5941684SN/A /** Instruction effective address. 5951684SN/A * @todo: Consider if this is necessary or not. 5961684SN/A */ 5971464SN/A Addr instEffAddr; 5982292SN/A 5991684SN/A /** Whether or not the effective address calculation is completed. 6001684SN/A * @todo: Consider if this is necessary or not. 6011684SN/A */ 6021464SN/A bool eaCalcDone; 6031464SN/A 6041464SN/A public: 6051684SN/A /** Sets the effective address. */ 6061464SN/A void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 6071684SN/A 6081684SN/A /** Returns the effective address. */ 6092669Sktlim@umich.edu const Addr &getEA() const { return instEffAddr; } 6101684SN/A 6111684SN/A /** Returns whether or not the eff. addr. calculation has been completed. */ 6121464SN/A bool doneEACalc() { return eaCalcDone; } 6131684SN/A 6141684SN/A /** Returns whether or not the eff. addr. source registers are ready. */ 6151464SN/A bool eaSrcsReady(); 6161681SN/A 6172292SN/A /** Whether or not the memory operation is done. */ 6182292SN/A bool memOpDone; 6192292SN/A 6201681SN/A public: 6211684SN/A /** Load queue index. */ 6221681SN/A int16_t lqIdx; 6231684SN/A 6241684SN/A /** Store queue index. */ 6251681SN/A int16_t sqIdx; 6262292SN/A 6272292SN/A bool reachedCommit; 6282292SN/A 6292292SN/A /** Iterator pointing to this BaseDynInst in the list of all insts. */ 6302292SN/A ListIt instListIt; 6312292SN/A 6322292SN/A /** Returns iterator to this instruction in the list of all insts. */ 6332292SN/A ListIt &getInstListIt() { return instListIt; } 6342292SN/A 6352292SN/A /** Sets iterator for this instruction in the list of all insts. */ 6362292SN/A void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 6371060SN/A}; 6381060SN/A 6391060SN/Atemplate<class Impl> 6401060SN/Atemplate<class T> 6412132SN/Ainline Fault 6421060SN/ABaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) 6431060SN/A{ 6442292SN/A if (executed) { 6452669Sktlim@umich.edu panic("Not supposed to re-execute with split mem ops!"); 6462292SN/A fault = cpu->read(req, data, lqIdx); 6472292SN/A return fault; 6482292SN/A } 6492292SN/A 6502669Sktlim@umich.edu req = new Request(); 6512669Sktlim@umich.edu req->setVirt(asid, addr, sizeof(T), flags, this->PC); 6522669Sktlim@umich.edu req->setThreadContext(thread->cpuId, threadNumber); 6532292SN/A 6542669Sktlim@umich.edu if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() > 6552292SN/A TheISA::VMPageSize) { 6562292SN/A return TheISA::genAlignmentFault(); 6572292SN/A } 6581060SN/A 6591060SN/A fault = cpu->translateDataReadReq(req); 6601060SN/A 6612669Sktlim@umich.edu effAddr = req->getVaddr(); 6622669Sktlim@umich.edu physEffAddr = req->getPaddr(); 6632669Sktlim@umich.edu memReqFlags = req->getFlags(); 6641060SN/A 6652292SN/A if (fault == NoFault) { 6662292SN/A#if FULL_SYSTEM 6672292SN/A if (cpu->system->memctrl->badaddr(physEffAddr)) { 6682292SN/A fault = TheISA::genMachineCheckFault(); 6692292SN/A data = (T)-1; 6702292SN/A this->setExecuted(); 6712292SN/A } else { 6722292SN/A fault = cpu->read(req, data, lqIdx); 6732292SN/A } 6742292SN/A#else 6752292SN/A fault = cpu->read(req, data, lqIdx); 6761060SN/A#endif 6771684SN/A } else { 6781060SN/A // Return a fixed value to keep simulation deterministic even 6791060SN/A // along misspeculated paths. 6801060SN/A data = (T)-1; 6812292SN/A 6822292SN/A // Commit will have to clean up whatever happened. Set this 6832292SN/A // instruction as executed. 6842292SN/A this->setExecuted(); 6851060SN/A } 6861060SN/A 6871060SN/A if (traceData) { 6881060SN/A traceData->setAddr(addr); 6891060SN/A traceData->setData(data); 6901060SN/A } 6911060SN/A 6921060SN/A return fault; 6931060SN/A} 6941060SN/A 6951060SN/Atemplate<class Impl> 6961060SN/Atemplate<class T> 6972132SN/Ainline Fault 6981060SN/ABaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) 6991060SN/A{ 7001060SN/A if (traceData) { 7011060SN/A traceData->setAddr(addr); 7021060SN/A traceData->setData(data); 7031060SN/A } 7041060SN/A 7052669Sktlim@umich.edu req = new Request(); 7062669Sktlim@umich.edu req->setVirt(asid, addr, sizeof(T), flags, this->PC); 7072669Sktlim@umich.edu req->setThreadContext(thread->cpuId, threadNumber); 7081060SN/A 7092669Sktlim@umich.edu if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() > 7102292SN/A TheISA::VMPageSize) { 7112292SN/A return TheISA::genAlignmentFault(); 7122292SN/A } 7131060SN/A 7141060SN/A fault = cpu->translateDataWriteReq(req); 7151060SN/A 7162669Sktlim@umich.edu effAddr = req->getVaddr(); 7172669Sktlim@umich.edu physEffAddr = req->getPaddr(); 7182669Sktlim@umich.edu memReqFlags = req->getFlags(); 7191060SN/A 7202292SN/A if (fault == NoFault) { 7212292SN/A#if FULL_SYSTEM 7222292SN/A if (cpu->system->memctrl->badaddr(physEffAddr)) { 7232292SN/A fault = TheISA::genMachineCheckFault(); 7242292SN/A } else { 7252292SN/A fault = cpu->write(req, data, sqIdx); 7262292SN/A } 7272292SN/A#else 7282292SN/A fault = cpu->write(req, data, sqIdx); 7291060SN/A#endif 7301060SN/A } 7311060SN/A 7321060SN/A if (res) { 7331060SN/A // always return some result to keep misspeculated paths 7341060SN/A // (which will ignore faults) deterministic 7352669Sktlim@umich.edu *res = (fault == NoFault) ? req->getScResult() : 0; 7361060SN/A } 7371060SN/A 7381060SN/A return fault; 7391060SN/A} 7401060SN/A 7411464SN/A#endif // __CPU_BASE_DYN_INST_HH__ 742