base_dyn_inst.hh revision 2107
110263Satgutier@umich.edu/* 210941Sdavid.guillen@arm.com * Copyright (c) 2004-2005 The Regents of The University of Michigan 310263Satgutier@umich.edu * All rights reserved. 410263Satgutier@umich.edu * 510263Satgutier@umich.edu * Redistribution and use in source and binary forms, with or without 610263Satgutier@umich.edu * modification, are permitted provided that the following conditions are 710263Satgutier@umich.edu * met: redistributions of source code must retain the above copyright 810263Satgutier@umich.edu * notice, this list of conditions and the following disclaimer; 910263Satgutier@umich.edu * redistributions in binary form must reproduce the above copyright 1010263Satgutier@umich.edu * notice, this list of conditions and the following disclaimer in the 1110263Satgutier@umich.edu * documentation and/or other materials provided with the distribution; 1210263Satgutier@umich.edu * neither the name of the copyright holders nor the names of its 1310263Satgutier@umich.edu * contributors may be used to endorse or promote products derived from 1410263Satgutier@umich.edu * this software without specific prior written permission. 1510263Satgutier@umich.edu * 1610263Satgutier@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710263Satgutier@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810263Satgutier@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910263Satgutier@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010263Satgutier@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110263Satgutier@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210263Satgutier@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310263Satgutier@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410263Satgutier@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510263Satgutier@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610263Satgutier@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710263Satgutier@umich.edu */ 2810263Satgutier@umich.edu 2910263Satgutier@umich.edu#ifndef __CPU_BASE_DYN_INST_HH__ 3010263Satgutier@umich.edu#define __CPU_BASE_DYN_INST_HH__ 3110263Satgutier@umich.edu 3210263Satgutier@umich.edu#include <string> 3310263Satgutier@umich.edu#include <vector> 3410263Satgutier@umich.edu 3510263Satgutier@umich.edu#include "base/fast_alloc.hh" 3610263Satgutier@umich.edu#include "base/trace.hh" 3710263Satgutier@umich.edu#include "config/full_system.hh" 3810263Satgutier@umich.edu#include "cpu/exetrace.hh" 3910263Satgutier@umich.edu#include "cpu/inst_seq.hh" 4010263Satgutier@umich.edu#include "cpu/o3/comm.hh" 4110263Satgutier@umich.edu#include "cpu/static_inst.hh" 4210263Satgutier@umich.edu#include "encumbered/cpu/full/bpred_update.hh" 4310263Satgutier@umich.edu#include "encumbered/cpu/full/op_class.hh" 4410263Satgutier@umich.edu#include "encumbered/cpu/full/spec_memory.hh" 4510263Satgutier@umich.edu#include "encumbered/cpu/full/spec_state.hh" 4610263Satgutier@umich.edu#include "encumbered/mem/functional/main.hh" 4710263Satgutier@umich.edu 4810263Satgutier@umich.edu/** 4910263Satgutier@umich.edu * @file 5010263Satgutier@umich.edu * Defines a dynamic instruction context. 5110263Satgutier@umich.edu */ 5210263Satgutier@umich.edu 5310263Satgutier@umich.edu// Forward declaration. 5410263Satgutier@umich.educlass StaticInstPtr; 5511486Snikos.nikoleris@arm.com 5611486Snikos.nikoleris@arm.comtemplate <class Impl> 5710263Satgutier@umich.educlass BaseDynInst : public FastAlloc, public RefCounted 5810263Satgutier@umich.edu{ 5910263Satgutier@umich.edu public: 6010263Satgutier@umich.edu // Typedef for the CPU. 6110263Satgutier@umich.edu typedef typename Impl::FullCPU FullCPU; 6210263Satgutier@umich.edu 6310263Satgutier@umich.edu /// Binary machine instruction type. 6410263Satgutier@umich.edu typedef TheISA::MachInst MachInst; 6510263Satgutier@umich.edu /// Memory address type. 6610263Satgutier@umich.edu typedef TheISA::Addr Addr; 6710263Satgutier@umich.edu /// Logical register index type. 6810263Satgutier@umich.edu typedef TheISA::RegIndex RegIndex; 6910263Satgutier@umich.edu /// Integer register index type. 7010263Satgutier@umich.edu typedef TheISA::IntReg IntReg; 7110263Satgutier@umich.edu 7210263Satgutier@umich.edu enum { 7310263Satgutier@umich.edu MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 7410263Satgutier@umich.edu MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs 7510263Satgutier@umich.edu }; 7610263Satgutier@umich.edu 7710263Satgutier@umich.edu /** The static inst used by this dyn inst. */ 7810263Satgutier@umich.edu StaticInstPtr staticInst; 7910263Satgutier@umich.edu 8010263Satgutier@umich.edu //////////////////////////////////////////// 8110263Satgutier@umich.edu // 8210263Satgutier@umich.edu // INSTRUCTION EXECUTION 8310263Satgutier@umich.edu // 8410263Satgutier@umich.edu //////////////////////////////////////////// 8510263Satgutier@umich.edu Trace::InstRecord *traceData; 8610263Satgutier@umich.edu 8710263Satgutier@umich.edu template <class T> 8810263Satgutier@umich.edu Fault * read(Addr addr, T &data, unsigned flags); 8910263Satgutier@umich.edu 9010941Sdavid.guillen@arm.com template <class T> 9110941Sdavid.guillen@arm.com Fault * write(T data, Addr addr, unsigned flags, 9210263Satgutier@umich.edu uint64_t *res); 9310263Satgutier@umich.edu 9410263Satgutier@umich.edu void prefetch(Addr addr, unsigned flags); 9510263Satgutier@umich.edu void writeHint(Addr addr, int size, unsigned flags); 9610263Satgutier@umich.edu Fault * copySrcTranslate(Addr src); 9710263Satgutier@umich.edu Fault * copy(Addr dest); 9810263Satgutier@umich.edu 9910263Satgutier@umich.edu /** @todo: Consider making this private. */ 10010263Satgutier@umich.edu public: 10110263Satgutier@umich.edu /** Is this instruction valid. */ 10210263Satgutier@umich.edu bool valid; 10310263Satgutier@umich.edu 10410263Satgutier@umich.edu /** The sequence number of the instruction. */ 10510263Satgutier@umich.edu InstSeqNum seqNum; 10610263Satgutier@umich.edu 10710263Satgutier@umich.edu /** How many source registers are ready. */ 10810263Satgutier@umich.edu unsigned readyRegs; 10910263Satgutier@umich.edu 11010263Satgutier@umich.edu /** Is the instruction completed. */ 11110263Satgutier@umich.edu bool completed; 11210263Satgutier@umich.edu 11310263Satgutier@umich.edu /** Can this instruction issue. */ 11410263Satgutier@umich.edu bool canIssue; 11510263Satgutier@umich.edu 11610263Satgutier@umich.edu /** Has this instruction issued. */ 11710263Satgutier@umich.edu bool issued; 11810263Satgutier@umich.edu 11910263Satgutier@umich.edu /** Has this instruction executed (or made it through execute) yet. */ 12010263Satgutier@umich.edu bool executed; 12110263Satgutier@umich.edu 12210263Satgutier@umich.edu /** Can this instruction commit. */ 12310263Satgutier@umich.edu bool canCommit; 12410263Satgutier@umich.edu 12510263Satgutier@umich.edu /** Is this instruction squashed. */ 12610263Satgutier@umich.edu bool squashed; 12710263Satgutier@umich.edu 12810263Satgutier@umich.edu /** Is this instruction squashed in the instruction queue. */ 12910263Satgutier@umich.edu bool squashedInIQ; 13010263Satgutier@umich.edu 13110263Satgutier@umich.edu /** Is this a recover instruction. */ 13210263Satgutier@umich.edu bool recoverInst; 13310263Satgutier@umich.edu 13410263Satgutier@umich.edu /** Is this a thread blocking instruction. */ 13510263Satgutier@umich.edu bool blockingInst; /* this inst has called thread_block() */ 13610263Satgutier@umich.edu 13710263Satgutier@umich.edu /** Is this a thread syncrhonization instruction. */ 13810263Satgutier@umich.edu bool threadsyncWait; 13910263Satgutier@umich.edu 14010263Satgutier@umich.edu /** The thread this instruction is from. */ 14110263Satgutier@umich.edu short threadNumber; 14210263Satgutier@umich.edu 14310263Satgutier@umich.edu /** data address space ID, for loads & stores. */ 14410263Satgutier@umich.edu short asid; 14510263Satgutier@umich.edu 14610263Satgutier@umich.edu /** Pointer to the FullCPU object. */ 14710263Satgutier@umich.edu FullCPU *cpu; 14810263Satgutier@umich.edu 14910263Satgutier@umich.edu /** Pointer to the exec context. Will not exist in the final version. */ 15010263Satgutier@umich.edu ExecContext *xc; 15110941Sdavid.guillen@arm.com 15210941Sdavid.guillen@arm.com /** The kind of fault this instruction has generated. */ 15310941Sdavid.guillen@arm.com Fault * fault; 15410941Sdavid.guillen@arm.com 15511169Sandreas.hansson@arm.com /** The effective virtual address (lds & stores only). */ 15610941Sdavid.guillen@arm.com Addr effAddr; 15710941Sdavid.guillen@arm.com 15810941Sdavid.guillen@arm.com /** The effective physical address. */ 15910941Sdavid.guillen@arm.com Addr physEffAddr; 16010941Sdavid.guillen@arm.com 16110941Sdavid.guillen@arm.com /** Effective virtual address for a copy source. */ 16210941Sdavid.guillen@arm.com Addr copySrcEffAddr; 16310941Sdavid.guillen@arm.com 16410941Sdavid.guillen@arm.com /** Effective physical address for a copy source. */ 16511169Sandreas.hansson@arm.com Addr copySrcPhysEffAddr; 16610941Sdavid.guillen@arm.com 16710941Sdavid.guillen@arm.com /** The memory request flags (from translation). */ 16810941Sdavid.guillen@arm.com unsigned memReqFlags; 16910941Sdavid.guillen@arm.com 17010941Sdavid.guillen@arm.com /** The size of the data to be stored. */ 17110941Sdavid.guillen@arm.com int storeSize; 17210941Sdavid.guillen@arm.com 17310941Sdavid.guillen@arm.com /** The data to be stored. */ 17410941Sdavid.guillen@arm.com IntReg storeData; 17510941Sdavid.guillen@arm.com 17611169Sandreas.hansson@arm.com union Result { 17710941Sdavid.guillen@arm.com uint64_t integer; 17810941Sdavid.guillen@arm.com float fp; 17910263Satgutier@umich.edu double dbl; 18010263Satgutier@umich.edu }; 18110263Satgutier@umich.edu 18211169Sandreas.hansson@arm.com /** The result of the instruction; assumes for now that there's only one 18310263Satgutier@umich.edu * destination register. 18410263Satgutier@umich.edu */ 18510263Satgutier@umich.edu Result instResult; 18610263Satgutier@umich.edu 18710263Satgutier@umich.edu /** PC of this instruction. */ 18810263Satgutier@umich.edu Addr PC; 18910263Satgutier@umich.edu 19010263Satgutier@umich.edu /** Next non-speculative PC. It is not filled in at fetch, but rather 19110263Satgutier@umich.edu * once the target of the branch is truly known (either decode or 19210263Satgutier@umich.edu * execute). 19310263Satgutier@umich.edu */ 19410263Satgutier@umich.edu Addr nextPC; 19510263Satgutier@umich.edu 19611484Snikos.nikoleris@arm.com /** Predicted next PC. */ 19710263Satgutier@umich.edu Addr predPC; 19810263Satgutier@umich.edu 19910263Satgutier@umich.edu /** Count of total number of dynamic instructions. */ 20010263Satgutier@umich.edu static int instcount; 20110263Satgutier@umich.edu 20210263Satgutier@umich.edu /** Whether or not the source register is ready. Not sure this should be 20310263Satgutier@umich.edu * here vs. the derived class. 20410263Satgutier@umich.edu */ 20510815Sdavid.guillen@arm.com bool _readySrcRegIdx[MaxInstSrcRegs]; 20611169Sandreas.hansson@arm.com 20710263Satgutier@umich.edu public: 20810263Satgutier@umich.edu /** BaseDynInst constructor given a binary instruction. */ 20910263Satgutier@umich.edu BaseDynInst(MachInst inst, Addr PC, Addr Pred_PC, InstSeqNum seq_num, 21010263Satgutier@umich.edu FullCPU *cpu); 21110263Satgutier@umich.edu 21210263Satgutier@umich.edu /** BaseDynInst constructor given a static inst pointer. */ 21310263Satgutier@umich.edu BaseDynInst(StaticInstPtr &_staticInst); 21410263Satgutier@umich.edu 21510941Sdavid.guillen@arm.com /** BaseDynInst destructor. */ 21610263Satgutier@umich.edu ~BaseDynInst(); 21711484Snikos.nikoleris@arm.com 21810263Satgutier@umich.edu private: 21910263Satgutier@umich.edu /** Function to initialize variables in the constructors. */ 22010263Satgutier@umich.edu void initVars(); 22110941Sdavid.guillen@arm.com 22210263Satgutier@umich.edu public: 22310263Satgutier@umich.edu void 22411484Snikos.nikoleris@arm.com trace_mem(Fault * fault, // last fault 22511722Ssophiane.senni@gmail.com MemCmd cmd, // last command 22611722Ssophiane.senni@gmail.com Addr addr, // virtual address of access 22711722Ssophiane.senni@gmail.com void *p, // memory accessed 22811722Ssophiane.senni@gmail.com int nbytes); // access size 22911722Ssophiane.senni@gmail.com 23011722Ssophiane.senni@gmail.com /** Dumps out contents of this BaseDynInst. */ 23111722Ssophiane.senni@gmail.com void dump(); 23211722Ssophiane.senni@gmail.com 23311722Ssophiane.senni@gmail.com /** Dumps out contents of this BaseDynInst into given string. */ 23410263Satgutier@umich.edu void dump(std::string &outstring); 23510263Satgutier@umich.edu 23611722Ssophiane.senni@gmail.com /** Returns the fault type. */ 23711722Ssophiane.senni@gmail.com Fault * getFault() { return fault; } 23811722Ssophiane.senni@gmail.com 23910263Satgutier@umich.edu /** Checks whether or not this instruction has had its branch target 24010263Satgutier@umich.edu * calculated yet. For now it is not utilized and is hacked to be 24110263Satgutier@umich.edu * always false. 24210263Satgutier@umich.edu */ 24310263Satgutier@umich.edu bool doneTargCalc() { return false; } 24410263Satgutier@umich.edu 24510263Satgutier@umich.edu /** Returns the next PC. This could be the speculative next PC if it is 24610263Satgutier@umich.edu * called prior to the actual branch target being calculated. 24710263Satgutier@umich.edu */ 24810263Satgutier@umich.edu Addr readNextPC() { return nextPC; } 24910263Satgutier@umich.edu 25010263Satgutier@umich.edu /** Set the predicted target of this current instruction. */ 25110263Satgutier@umich.edu void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; } 25211169Sandreas.hansson@arm.com 25310263Satgutier@umich.edu /** Returns the predicted target of the branch. */ 25410263Satgutier@umich.edu Addr readPredTarg() { return predPC; } 25510263Satgutier@umich.edu 25610263Satgutier@umich.edu /** Returns whether the instruction was predicted taken or not. */ 25710263Satgutier@umich.edu bool predTaken() { 25810263Satgutier@umich.edu return( predPC != (PC + sizeof(MachInst) ) ); 25910263Satgutier@umich.edu } 26010263Satgutier@umich.edu 26111169Sandreas.hansson@arm.com /** Returns whether the instruction mispredicted. */ 26210263Satgutier@umich.edu bool mispredicted() { return (predPC != nextPC); } 26311484Snikos.nikoleris@arm.com 26410263Satgutier@umich.edu // 26510263Satgutier@umich.edu // Instruction types. Forward checks to StaticInst object. 26610263Satgutier@umich.edu // 26710941Sdavid.guillen@arm.com bool isNop() const { return staticInst->isNop(); } 26810263Satgutier@umich.edu bool isMemRef() const { return staticInst->isMemRef(); } 26910941Sdavid.guillen@arm.com bool isLoad() const { return staticInst->isLoad(); } 27010263Satgutier@umich.edu bool isStore() const { return staticInst->isStore(); } 27110263Satgutier@umich.edu bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 27210263Satgutier@umich.edu bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 27310263Satgutier@umich.edu bool isCopy() const { return staticInst->isCopy(); } 27410263Satgutier@umich.edu bool isInteger() const { return staticInst->isInteger(); } 27510263Satgutier@umich.edu bool isFloating() const { return staticInst->isFloating(); } 27610263Satgutier@umich.edu bool isControl() const { return staticInst->isControl(); } 27710263Satgutier@umich.edu bool isCall() const { return staticInst->isCall(); } 27810263Satgutier@umich.edu bool isReturn() const { return staticInst->isReturn(); } 27910263Satgutier@umich.edu bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 28010263Satgutier@umich.edu bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 28111169Sandreas.hansson@arm.com bool isCondCtrl() const { return staticInst->isCondCtrl(); } 28210263Satgutier@umich.edu bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 28310263Satgutier@umich.edu bool isThreadSync() const { return staticInst->isThreadSync(); } 28410263Satgutier@umich.edu bool isSerializing() const { return staticInst->isSerializing(); } 28510263Satgutier@umich.edu bool isMemBarrier() const { return staticInst->isMemBarrier(); } 28610274Smitch.hayenga@arm.com bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 28710263Satgutier@umich.edu bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 28810263Satgutier@umich.edu 28910263Satgutier@umich.edu /** Returns the opclass of this instruction. */ 29010263Satgutier@umich.edu OpClass opClass() const { return staticInst->opClass(); } 29110263Satgutier@umich.edu 29210263Satgutier@umich.edu /** Returns the branch target address. */ 29310263Satgutier@umich.edu Addr branchTarget() const { return staticInst->branchTarget(PC); } 29410263Satgutier@umich.edu 29510263Satgutier@umich.edu /** Number of source registers. */ 29610263Satgutier@umich.edu int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 29710263Satgutier@umich.edu 29810263Satgutier@umich.edu /** Number of destination registers. */ 29910263Satgutier@umich.edu int8_t numDestRegs() const { return staticInst->numDestRegs(); } 30010263Satgutier@umich.edu 30110263Satgutier@umich.edu // the following are used to track physical register usage 30210263Satgutier@umich.edu // for machines with separate int & FP reg files 30310263Satgutier@umich.edu int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 30410263Satgutier@umich.edu int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 30510263Satgutier@umich.edu 30610263Satgutier@umich.edu /** Returns the logical register index of the i'th destination register. */ 30710263Satgutier@umich.edu RegIndex destRegIdx(int i) const 30810263Satgutier@umich.edu { 30910263Satgutier@umich.edu return staticInst->destRegIdx(i); 31010263Satgutier@umich.edu } 31110263Satgutier@umich.edu 31210263Satgutier@umich.edu /** Returns the logical register index of the i'th source register. */ 31310263Satgutier@umich.edu RegIndex srcRegIdx(int i) const 31410274Smitch.hayenga@arm.com { 31510263Satgutier@umich.edu return staticInst->srcRegIdx(i); 31610263Satgutier@umich.edu } 31710263Satgutier@umich.edu 31810263Satgutier@umich.edu /** Returns the result of an integer instruction. */ 31910263Satgutier@umich.edu uint64_t readIntResult() { return instResult.integer; } 32010263Satgutier@umich.edu 32110263Satgutier@umich.edu /** Returns the result of a floating point instruction. */ 32210263Satgutier@umich.edu float readFloatResult() { return instResult.fp; } 32310263Satgutier@umich.edu 32410263Satgutier@umich.edu /** Returns the result of a floating point (double) instruction. */ 32510263Satgutier@umich.edu double readDoubleResult() { return instResult.dbl; } 32610263Satgutier@umich.edu 32710263Satgutier@umich.edu //Push to .cc file. 32810263Satgutier@umich.edu /** Records that one of the source registers is ready. */ 32910263Satgutier@umich.edu void markSrcRegReady() 33010263Satgutier@umich.edu { 33110941Sdavid.guillen@arm.com ++readyRegs; 33210941Sdavid.guillen@arm.com if(readyRegs == numSrcRegs()) { 33310941Sdavid.guillen@arm.com canIssue = true; 33411169Sandreas.hansson@arm.com } 33510941Sdavid.guillen@arm.com } 33610941Sdavid.guillen@arm.com 33710941Sdavid.guillen@arm.com /** Marks a specific register as ready. 33810941Sdavid.guillen@arm.com * @todo: Move this to .cc file. 33910941Sdavid.guillen@arm.com */ 34010941Sdavid.guillen@arm.com void markSrcRegReady(RegIndex src_idx) 34110941Sdavid.guillen@arm.com { 34210941Sdavid.guillen@arm.com ++readyRegs; 34310941Sdavid.guillen@arm.com 34411169Sandreas.hansson@arm.com _readySrcRegIdx[src_idx] = 1; 34510941Sdavid.guillen@arm.com 34610941Sdavid.guillen@arm.com if(readyRegs == numSrcRegs()) { 34710941Sdavid.guillen@arm.com canIssue = true; 34810941Sdavid.guillen@arm.com } 34910941Sdavid.guillen@arm.com } 35010263Satgutier@umich.edu 35110263Satgutier@umich.edu /** Returns if a source register is ready. */ 35210263Satgutier@umich.edu bool isReadySrcRegIdx(int idx) const 35310263Satgutier@umich.edu { 35411169Sandreas.hansson@arm.com return this->_readySrcRegIdx[idx]; 35510263Satgutier@umich.edu } 35610263Satgutier@umich.edu 35710263Satgutier@umich.edu /** Sets this instruction as completed. */ 35810263Satgutier@umich.edu void setCompleted() { completed = true; } 35910263Satgutier@umich.edu 36010263Satgutier@umich.edu /** Returns whethe or not this instruction is completed. */ 36110263Satgutier@umich.edu bool isCompleted() const { return completed; } 36210263Satgutier@umich.edu 36310263Satgutier@umich.edu /** Sets this instruction as ready to issue. */ 36411169Sandreas.hansson@arm.com void setCanIssue() { canIssue = true; } 36510263Satgutier@umich.edu 36610263Satgutier@umich.edu /** Returns whether or not this instruction is ready to issue. */ 36710263Satgutier@umich.edu bool readyToIssue() const { return canIssue; } 36810263Satgutier@umich.edu 36910263Satgutier@umich.edu /** Sets this instruction as issued from the IQ. */ 37010263Satgutier@umich.edu void setIssued() { issued = true; } 37110263Satgutier@umich.edu 37210263Satgutier@umich.edu /** Returns whether or not this instruction has issued. */ 37310263Satgutier@umich.edu bool isIssued() const { return issued; } 37410263Satgutier@umich.edu 37510263Satgutier@umich.edu /** Sets this instruction as executed. */ 37610263Satgutier@umich.edu void setExecuted() { executed = true; } 37710263Satgutier@umich.edu 37810263Satgutier@umich.edu /** Returns whether or not this instruction has executed. */ 37910263Satgutier@umich.edu bool isExecuted() const { return executed; } 38010263Satgutier@umich.edu 38110263Satgutier@umich.edu /** Sets this instruction as ready to commit. */ 38210263Satgutier@umich.edu void setCanCommit() { canCommit = true; } 38310263Satgutier@umich.edu 38410263Satgutier@umich.edu /** Clears this instruction as being ready to commit. */ 38511169Sandreas.hansson@arm.com void clearCanCommit() { canCommit = false; } 38610263Satgutier@umich.edu 38710263Satgutier@umich.edu /** Returns whether or not this instruction is ready to commit. */ 38810263Satgutier@umich.edu bool readyToCommit() const { return canCommit; } 38910263Satgutier@umich.edu 39010263Satgutier@umich.edu /** Sets this instruction as squashed. */ 39110263Satgutier@umich.edu void setSquashed() { squashed = true; } 39210263Satgutier@umich.edu 39311169Sandreas.hansson@arm.com /** Returns whether or not this instruction is squashed. */ 39410263Satgutier@umich.edu bool isSquashed() const { return squashed; } 39510263Satgutier@umich.edu 39610263Satgutier@umich.edu /** Sets this instruction as squashed in the IQ. */ 39710263Satgutier@umich.edu void setSquashedInIQ() { squashedInIQ = true; } 39811169Sandreas.hansson@arm.com 39910263Satgutier@umich.edu /** Returns whether or not this instruction is squashed in the IQ. */ 40010263Satgutier@umich.edu bool isSquashedInIQ() const { return squashedInIQ; } 40110263Satgutier@umich.edu 40210263Satgutier@umich.edu /** Read the PC of this instruction. */ 40311169Sandreas.hansson@arm.com const Addr readPC() const { return PC; } 40410263Satgutier@umich.edu 40510263Satgutier@umich.edu /** Set the next PC of this instruction (its actual target). */ 40610263Satgutier@umich.edu void setNextPC(uint64_t val) { nextPC = val; } 40710263Satgutier@umich.edu 40810263Satgutier@umich.edu /** Returns the exec context. 40910263Satgutier@umich.edu * @todo: Remove this once the ExecContext is no longer used. 41010263Satgutier@umich.edu */ 41110263Satgutier@umich.edu ExecContext *xcBase() { return xc; } 41210263Satgutier@umich.edu 41310263Satgutier@umich.edu private: 41410263Satgutier@umich.edu /** Instruction effective address. 41510263Satgutier@umich.edu * @todo: Consider if this is necessary or not. 41610263Satgutier@umich.edu */ 41711168Sandreas.hansson@arm.com Addr instEffAddr; 41810263Satgutier@umich.edu /** Whether or not the effective address calculation is completed. 41910263Satgutier@umich.edu * @todo: Consider if this is necessary or not. 42010263Satgutier@umich.edu */ 42110263Satgutier@umich.edu bool eaCalcDone; 42210263Satgutier@umich.edu 42310263Satgutier@umich.edu public: 42410263Satgutier@umich.edu /** Sets the effective address. */ 42510263Satgutier@umich.edu void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 426 427 /** Returns the effective address. */ 428 const Addr &getEA() const { return instEffAddr; } 429 430 /** Returns whether or not the eff. addr. calculation has been completed. */ 431 bool doneEACalc() { return eaCalcDone; } 432 433 /** Returns whether or not the eff. addr. source registers are ready. */ 434 bool eaSrcsReady(); 435 436 public: 437 /** Load queue index. */ 438 int16_t lqIdx; 439 440 /** Store queue index. */ 441 int16_t sqIdx; 442}; 443 444template<class Impl> 445template<class T> 446inline Fault * 447BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) 448{ 449 MemReqPtr req = new MemReq(addr, xc, sizeof(T), flags); 450 req->asid = asid; 451 452 fault = cpu->translateDataReadReq(req); 453 454 // Record key MemReq parameters so we can generate another one 455 // just like it for the timing access without calling translate() 456 // again (which might mess up the TLB). 457 // Do I ever really need this? -KTL 3/05 458 effAddr = req->vaddr; 459 physEffAddr = req->paddr; 460 memReqFlags = req->flags; 461 462 /** 463 * @todo 464 * Replace the disjoint functional memory with a unified one and remove 465 * this hack. 466 */ 467#if !FULL_SYSTEM 468 req->paddr = req->vaddr; 469#endif 470 471 if (fault == NoFault) { 472 fault = cpu->read(req, data, lqIdx); 473 } else { 474 // Return a fixed value to keep simulation deterministic even 475 // along misspeculated paths. 476 data = (T)-1; 477 } 478 479 if (traceData) { 480 traceData->setAddr(addr); 481 traceData->setData(data); 482 } 483 484 return fault; 485} 486 487template<class Impl> 488template<class T> 489inline Fault * 490BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) 491{ 492 if (traceData) { 493 traceData->setAddr(addr); 494 traceData->setData(data); 495 } 496 497 MemReqPtr req = new MemReq(addr, xc, sizeof(T), flags); 498 499 req->asid = asid; 500 501 fault = cpu->translateDataWriteReq(req); 502 503 // Record key MemReq parameters so we can generate another one 504 // just like it for the timing access without calling translate() 505 // again (which might mess up the TLB). 506 effAddr = req->vaddr; 507 physEffAddr = req->paddr; 508 memReqFlags = req->flags; 509 510 /** 511 * @todo 512 * Replace the disjoint functional memory with a unified one and remove 513 * this hack. 514 */ 515#if !FULL_SYSTEM 516 req->paddr = req->vaddr; 517#endif 518 519 if (fault == NoFault) { 520 fault = cpu->write(req, data, sqIdx); 521 } 522 523 if (res) { 524 // always return some result to keep misspeculated paths 525 // (which will ignore faults) deterministic 526 *res = (fault == NoFault) ? req->result : 0; 527 } 528 529 return fault; 530} 531 532#endif // __CPU_BASE_DYN_INST_HH__ 533