base_dyn_inst.hh revision 1762 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __CPU_BASE_DYN_INST_HH__
30#define __CPU_BASE_DYN_INST_HH__
31
32#include <string>
33#include <vector>
34
35#include "base/fast_alloc.hh"
36#include "base/trace.hh"
37#include "cpu/exetrace.hh"
38#include "cpu/inst_seq.hh"
39#include "cpu/o3/comm.hh"
40#include "cpu/static_inst.hh"
41#include "encumbered/cpu/full/bpred_update.hh"
42#include "encumbered/cpu/full/op_class.hh"
43#include "encumbered/cpu/full/spec_memory.hh"
44#include "encumbered/cpu/full/spec_state.hh"
45#include "encumbered/mem/functional/main.hh"
46
47/**
48 * @file
49 * Defines a dynamic instruction context.
50 */
51
52// Forward declaration.
53template <class ISA>
54class StaticInstPtr;
55
56template <class Impl>
57class BaseDynInst : public FastAlloc, public RefCounted
58{
59  public:
60    // Typedef for the CPU.
61    typedef typename Impl::FullCPU FullCPU;
62
63    //Typedef to get the ISA.
64    typedef typename Impl::ISA ISA;
65
66    /// Binary machine instruction type.
67    typedef typename ISA::MachInst MachInst;
68    /// Memory address type.
69    typedef typename ISA::Addr	   Addr;
70    /// Logical register index type.
71    typedef typename ISA::RegIndex RegIndex;
72    /// Integer register index type.
73    typedef typename ISA::IntReg   IntReg;
74
75    enum {
76        MaxInstSrcRegs = ISA::MaxInstSrcRegs,	//< Max source regs
77        MaxInstDestRegs = ISA::MaxInstDestRegs,	//< Max dest regs
78    };
79
80    /** The static inst used by this dyn inst. */
81    StaticInstPtr<ISA> staticInst;
82
83    ////////////////////////////////////////////
84    //
85    // INSTRUCTION EXECUTION
86    //
87    ////////////////////////////////////////////
88    Trace::InstRecord *traceData;
89
90    template <class T>
91    Fault read(Addr addr, T &data, unsigned flags);
92
93    template <class T>
94    Fault write(T data, Addr addr, unsigned flags,
95                        uint64_t *res);
96
97    void prefetch(Addr addr, unsigned flags);
98    void writeHint(Addr addr, int size, unsigned flags);
99    Fault copySrcTranslate(Addr src);
100    Fault copy(Addr dest);
101
102    /** @todo: Consider making this private. */
103  public:
104    /** Is this instruction valid. */
105    bool valid;
106
107    /** The sequence number of the instruction. */
108    InstSeqNum seqNum;
109
110    /** How many source registers are ready. */
111    unsigned readyRegs;
112
113    /** Is the instruction completed. */
114    bool completed;
115
116    /** Can this instruction issue. */
117    bool canIssue;
118
119    /** Has this instruction issued. */
120    bool issued;
121
122    /** Has this instruction executed (or made it through execute) yet. */
123    bool executed;
124
125    /** Can this instruction commit. */
126    bool canCommit;
127
128    /** Is this instruction squashed. */
129    bool squashed;
130
131    /** Is this instruction squashed in the instruction queue. */
132    bool squashedInIQ;
133
134    /** Is this a recover instruction. */
135    bool recoverInst;
136
137    /** Is this a thread blocking instruction. */
138    bool blockingInst;	/* this inst has called thread_block() */
139
140    /** Is this a thread syncrhonization instruction. */
141    bool threadsyncWait;
142
143    /** The thread this instruction is from. */
144    short threadNumber;
145
146    /** data address space ID, for loads & stores. */
147    short asid;
148
149    /** Pointer to the FullCPU object. */
150    FullCPU *cpu;
151
152    /** Pointer to the exec context.  Will not exist in the final version. */
153    ExecContext *xc;
154
155    /** The kind of fault this instruction has generated. */
156    Fault fault;
157
158    /** The effective virtual address (lds & stores only). */
159    Addr effAddr;
160
161    /** The effective physical address. */
162    Addr physEffAddr;
163
164    /** Effective virtual address for a copy source. */
165    Addr copySrcEffAddr;
166
167    /** Effective physical address for a copy source. */
168    Addr copySrcPhysEffAddr;
169
170    /** The memory request flags (from translation). */
171    unsigned memReqFlags;
172
173    /** The size of the data to be stored. */
174    int storeSize;
175
176    /** The data to be stored. */
177    IntReg storeData;
178
179    union Result {
180        uint64_t integer;
181        float fp;
182        double dbl;
183    };
184
185    /** The result of the instruction; assumes for now that there's only one
186     *  destination register.
187     */
188    Result instResult;
189
190    /** PC of this instruction. */
191    Addr PC;
192
193    /** Next non-speculative PC.  It is not filled in at fetch, but rather
194     *  once the target of the branch is truly known (either decode or
195     *  execute).
196     */
197    Addr nextPC;
198
199    /** Predicted next PC. */
200    Addr predPC;
201
202    /** Count of total number of dynamic instructions. */
203    static int instcount;
204
205    /** Whether or not the source register is ready.  Not sure this should be
206     *  here vs. the derived class.
207     */
208    bool _readySrcRegIdx[MaxInstSrcRegs];
209
210  public:
211    /** BaseDynInst constructor given a binary instruction. */
212    BaseDynInst(MachInst inst, Addr PC, Addr Pred_PC, InstSeqNum seq_num,
213                FullCPU *cpu);
214
215    /** BaseDynInst constructor given a static inst pointer. */
216    BaseDynInst(StaticInstPtr<ISA> &_staticInst);
217
218    /** BaseDynInst destructor. */
219    ~BaseDynInst();
220
221  private:
222    /** Function to initialize variables in the constructors. */
223    void initVars();
224
225  public:
226    void
227    trace_mem(Fault fault,      // last fault
228              MemCmd cmd,       // last command
229              Addr addr,        // virtual address of access
230              void *p,          // memory accessed
231              int nbytes);      // access size
232
233    /** Dumps out contents of this BaseDynInst. */
234    void dump();
235
236    /** Dumps out contents of this BaseDynInst into given string. */
237    void dump(std::string &outstring);
238
239    /** Returns the fault type. */
240    Fault getFault() { return fault; }
241
242    /** Checks whether or not this instruction has had its branch target
243     *  calculated yet.  For now it is not utilized and is hacked to be
244     *  always false.
245     */
246    bool doneTargCalc() { return false; }
247
248    /** Returns the next PC.  This could be the speculative next PC if it is
249     *  called prior to the actual branch target being calculated.
250     */
251    Addr readNextPC() { return nextPC; }
252
253    /** Set the predicted target of this current instruction. */
254    void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; }
255
256    /** Returns the predicted target of the branch. */
257    Addr readPredTarg() { return predPC; }
258
259    /** Returns whether the instruction was predicted taken or not. */
260    bool predTaken() {
261        return( predPC != (PC + sizeof(MachInst) ) );
262    }
263
264    /** Returns whether the instruction mispredicted. */
265    bool mispredicted() { return (predPC != nextPC); }
266
267    //
268    //  Instruction types.  Forward checks to StaticInst object.
269    //
270    bool isNop()	  const { return staticInst->isNop(); }
271    bool isMemRef()    	  const { return staticInst->isMemRef(); }
272    bool isLoad()	  const { return staticInst->isLoad(); }
273    bool isStore()	  const { return staticInst->isStore(); }
274    bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
275    bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
276    bool isCopy()         const { return staticInst->isCopy(); }
277    bool isInteger()	  const { return staticInst->isInteger(); }
278    bool isFloating()	  const { return staticInst->isFloating(); }
279    bool isControl()	  const { return staticInst->isControl(); }
280    bool isCall()	  const { return staticInst->isCall(); }
281    bool isReturn()	  const { return staticInst->isReturn(); }
282    bool isDirectCtrl()	  const { return staticInst->isDirectCtrl(); }
283    bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
284    bool isCondCtrl()	  const { return staticInst->isCondCtrl(); }
285    bool isUncondCtrl()	  const { return staticInst->isUncondCtrl(); }
286    bool isThreadSync()   const { return staticInst->isThreadSync(); }
287    bool isSerializing()  const { return staticInst->isSerializing(); }
288    bool isMemBarrier()   const { return staticInst->isMemBarrier(); }
289    bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
290    bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
291
292    /** Returns the opclass of this instruction. */
293    OpClass opClass() const { return staticInst->opClass(); }
294
295    /** Returns the branch target address. */
296    Addr branchTarget() const { return staticInst->branchTarget(PC); }
297
298    /** Number of source registers. */
299    int8_t numSrcRegs()	 const { return staticInst->numSrcRegs(); }
300
301    /** Number of destination registers. */
302    int8_t numDestRegs() const { return staticInst->numDestRegs(); }
303
304    // the following are used to track physical register usage
305    // for machines with separate int & FP reg files
306    int8_t numFPDestRegs()  const { return staticInst->numFPDestRegs(); }
307    int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
308
309    /** Returns the logical register index of the i'th destination register. */
310    RegIndex destRegIdx(int i) const
311    {
312        return staticInst->destRegIdx(i);
313    }
314
315    /** Returns the logical register index of the i'th source register. */
316    RegIndex srcRegIdx(int i) const
317    {
318        return staticInst->srcRegIdx(i);
319    }
320
321    /** Returns the result of an integer instruction. */
322    uint64_t readIntResult() { return instResult.integer; }
323
324    /** Returns the result of a floating point instruction. */
325    float readFloatResult() { return instResult.fp; }
326
327    /** Returns the result of a floating point (double) instruction. */
328    double readDoubleResult() { return instResult.dbl; }
329
330    //Push to .cc file.
331    /** Records that one of the source registers is ready. */
332    void markSrcRegReady()
333    {
334        ++readyRegs;
335        if(readyRegs == numSrcRegs()) {
336            canIssue = true;
337        }
338    }
339
340    /** Marks a specific register as ready.
341     *  @todo: Move this to .cc file.
342     */
343    void markSrcRegReady(RegIndex src_idx)
344    {
345        ++readyRegs;
346
347        _readySrcRegIdx[src_idx] = 1;
348
349        if(readyRegs == numSrcRegs()) {
350            canIssue = true;
351        }
352    }
353
354    /** Returns if a source register is ready. */
355    bool isReadySrcRegIdx(int idx) const
356    {
357        return this->_readySrcRegIdx[idx];
358    }
359
360    /** Sets this instruction as completed. */
361    void setCompleted() { completed = true; }
362
363    /** Returns whethe or not this instruction is completed. */
364    bool isCompleted() const { return completed; }
365
366    /** Sets this instruction as ready to issue. */
367    void setCanIssue() { canIssue = true; }
368
369    /** Returns whether or not this instruction is ready to issue. */
370    bool readyToIssue() const { return canIssue; }
371
372    /** Sets this instruction as issued from the IQ. */
373    void setIssued() { issued = true; }
374
375    /** Returns whether or not this instruction has issued. */
376    bool isIssued() const { return issued; }
377
378    /** Sets this instruction as executed. */
379    void setExecuted() { executed = true; }
380
381    /** Returns whether or not this instruction has executed. */
382    bool isExecuted() const { return executed; }
383
384    /** Sets this instruction as ready to commit. */
385    void setCanCommit() { canCommit = true; }
386
387    /** Clears this instruction as being ready to commit. */
388    void clearCanCommit() { canCommit = false; }
389
390    /** Returns whether or not this instruction is ready to commit. */
391    bool readyToCommit() const { return canCommit; }
392
393    /** Sets this instruction as squashed. */
394    void setSquashed() { squashed = true; }
395
396    /** Returns whether or not this instruction is squashed. */
397    bool isSquashed() const { return squashed; }
398
399    /** Sets this instruction as squashed in the IQ. */
400    void setSquashedInIQ() { squashedInIQ = true; }
401
402    /** Returns whether or not this instruction is squashed in the IQ. */
403    bool isSquashedInIQ() const { return squashedInIQ; }
404
405    /** Read the PC of this instruction. */
406    const Addr readPC() const { return PC; }
407
408    /** Set the next PC of this instruction (its actual target). */
409    void setNextPC(uint64_t val) { nextPC = val; }
410
411    /** Returns the exec context.
412     *  @todo: Remove this once the ExecContext is no longer used.
413     */
414    ExecContext *xcBase() { return xc; }
415
416  private:
417    /** Instruction effective address.
418     *  @todo: Consider if this is necessary or not.
419     */
420    Addr instEffAddr;
421    /** Whether or not the effective address calculation is completed.
422     *  @todo: Consider if this is necessary or not.
423     */
424    bool eaCalcDone;
425
426  public:
427    /** Sets the effective address. */
428    void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
429
430    /** Returns the effective address. */
431    const Addr &getEA() const { return instEffAddr; }
432
433    /** Returns whether or not the eff. addr. calculation has been completed. */
434    bool doneEACalc() { return eaCalcDone; }
435
436    /** Returns whether or not the eff. addr. source registers are ready. */
437    bool eaSrcsReady();
438
439  public:
440    /** Load queue index. */
441    int16_t lqIdx;
442
443    /** Store queue index. */
444    int16_t sqIdx;
445};
446
447template<class Impl>
448template<class T>
449inline Fault
450BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
451{
452    MemReqPtr req = new MemReq(addr, xc, sizeof(T), flags);
453    req->asid = asid;
454
455    fault = cpu->translateDataReadReq(req);
456
457    // Record key MemReq parameters so we can generate another one
458    // just like it for the timing access without calling translate()
459    // again (which might mess up the TLB).
460    // Do I ever really need this? -KTL 3/05
461    effAddr = req->vaddr;
462    physEffAddr = req->paddr;
463    memReqFlags = req->flags;
464
465    /**
466     * @todo
467     * Replace the disjoint functional memory with a unified one and remove
468     * this hack.
469     */
470#ifndef FULL_SYSTEM
471    req->paddr = req->vaddr;
472#endif
473
474    if (fault == No_Fault) {
475        fault = cpu->read(req, data, lqIdx);
476    } else {
477        // Return a fixed value to keep simulation deterministic even
478        // along misspeculated paths.
479        data = (T)-1;
480    }
481
482    if (traceData) {
483        traceData->setAddr(addr);
484        traceData->setData(data);
485    }
486
487    return fault;
488}
489
490template<class Impl>
491template<class T>
492inline Fault
493BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
494{
495    if (traceData) {
496        traceData->setAddr(addr);
497        traceData->setData(data);
498    }
499
500    MemReqPtr req = new MemReq(addr, xc, sizeof(T), flags);
501
502    req->asid = asid;
503
504    fault = cpu->translateDataWriteReq(req);
505
506    // Record key MemReq parameters so we can generate another one
507    // just like it for the timing access without calling translate()
508    // again (which might mess up the TLB).
509    effAddr = req->vaddr;
510    physEffAddr = req->paddr;
511    memReqFlags = req->flags;
512
513    /**
514     * @todo
515     * Replace the disjoint functional memory with a unified one and remove
516     * this hack.
517     */
518#ifndef FULL_SYSTEM
519    req->paddr = req->vaddr;
520#endif
521
522    if (fault == No_Fault) {
523        fault = cpu->write(req, data, sqIdx);
524    }
525
526    if (res) {
527        // always return some result to keep misspeculated paths
528        // (which will ignore faults) deterministic
529        *res = (fault == No_Fault) ? req->result : 0;
530    }
531
532    return fault;
533}
534
535#endif // __CPU_BASE_DYN_INST_HH__
536