base_dyn_inst.hh revision 1464 
1/*
2 * Copyright (c) 2001-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __CPU_BASE_DYN_INST_HH__
30#define __CPU_BASE_DYN_INST_HH__
31
32#include <string>
33#include <vector>
34
35#include "base/fast_alloc.hh"
36#include "base/trace.hh"
37
38#include "cpu/beta_cpu/comm.hh"
39#include "cpu/exetrace.hh"
40#include "cpu/full_cpu/bpred_update.hh"
41#include "cpu/full_cpu/op_class.hh"
42#include "cpu/full_cpu/spec_memory.hh"
43#include "cpu/full_cpu/spec_state.hh"
44#include "cpu/inst_seq.hh"
45#include "cpu/static_inst.hh"
46#include "mem/functional_mem/main_memory.hh"
47
48/**
49 * @file
50 * Defines a dynamic instruction context.
51 */
52
53// Forward declaration.
54template <class ISA>
55class StaticInstPtr;
56
57template <class Impl>
58class BaseDynInst : public FastAlloc, public RefCounted
59{
60  public:
61    // Typedef for the CPU.
62    typedef typename Impl::FullCPU FullCPU;
63
64    //Typedef to get the ISA.
65    typedef typename Impl::ISA ISA;
66
67    /// Binary machine instruction type.
68    typedef typename ISA::MachInst MachInst;
69    /// Memory address type.
70    typedef typename ISA::Addr	   Addr;
71    /// Logical register index type.
72    typedef typename ISA::RegIndex RegIndex;
73    /// Integer register index type.
74    typedef typename ISA::IntReg   IntReg;
75
76    enum {
77        MaxInstSrcRegs = ISA::MaxInstSrcRegs,	//< Max source regs
78        MaxInstDestRegs = ISA::MaxInstDestRegs,	//< Max dest regs
79    };
80
81    StaticInstPtr<ISA> staticInst;
82
83    ////////////////////////////////////////////
84    //
85    // INSTRUCTION EXECUTION
86    //
87    ////////////////////////////////////////////
88    Trace::InstRecord *traceData;
89
90    template <class T>
91    Fault read(Addr addr, T &data, unsigned flags);
92
93    template <class T>
94    Fault write(T data, Addr addr, unsigned flags,
95                        uint64_t *res);
96
97    void prefetch(Addr addr, unsigned flags);
98    void writeHint(Addr addr, int size, unsigned flags);
99    Fault copySrcTranslate(Addr src);
100    Fault copy(Addr dest);
101
102    // Probably should be private...
103  public:
104    /** Is this instruction valid. */
105    bool valid;
106
107    /** The sequence number of the instruction. */
108    InstSeqNum seqNum;
109
110    /** How many source registers are ready. */
111    unsigned readyRegs;
112
113    /** Is the instruction completed. */
114    bool completed;
115
116    /** Can this instruction issue. */
117    bool canIssue;
118
119    /** Has this instruction issued. */
120    bool issued;
121
122    /** Has this instruction executed (or made it through execute) yet. */
123    bool executed;
124
125    /** Can this instruction commit. */
126    bool canCommit;
127
128    /** Is this instruction squashed. */
129    bool squashed;
130
131    /** Is this instruction squashed in the instruction queue. */
132    bool squashedInIQ;
133
134    /** Is this a recover instruction. */
135    bool recoverInst;
136
137    /** Is this a thread blocking instruction. */
138    bool blockingInst;	/* this inst has called thread_block() */
139
140    /** Is this a thread syncrhonization instruction. */
141    bool threadsyncWait;
142
143    /** The thread this instruction is from. */
144    short threadNumber;
145
146    /** data address space ID, for loads & stores. */
147    short asid;
148
149    /** Pointer to the FullCPU object. */
150    FullCPU *cpu;
151
152    /** Pointer to the exec context.  Will not exist in the final version. */
153    ExecContext *xc;
154
155    /** The kind of fault this instruction has generated. */
156    Fault fault;
157
158    /** The effective virtual address (lds & stores only). */
159    Addr effAddr;
160
161    /** The effective physical address. */
162    Addr physEffAddr;
163
164    /** Effective virtual address for a copy source. */
165    Addr copySrcEffAddr;
166
167    /** Effective physical address for a copy source. */
168    Addr copySrcPhysEffAddr;
169
170    /** The memory request flags (from translation). */
171    unsigned memReqFlags;
172
173    /** The size of the data to be stored. */
174    int storeSize;
175
176    /** The data to be stored. */
177    IntReg storeData;
178
179    union Result {
180        uint64_t integer;
181        float fp;
182        double dbl;
183    };
184
185    /** The result of the instruction; assumes for now that there's only one
186     *  destination register.
187     */
188    Result instResult;
189
190    /** PC of this instruction. */
191    Addr PC;
192
193    /** Next non-speculative PC.  It is not filled in at fetch, but rather
194     *  once the target of the branch is truly known (either decode or
195     *  execute).
196     */
197    Addr nextPC;
198
199    /** Predicted next PC. */
200    Addr predPC;
201
202    /** Count of total number of dynamic instructions. */
203    static int instcount;
204
205    /** Whether or not the source register is ready.  Not sure this should be
206     *  here vs. the derived class.
207     */
208    bool _readySrcRegIdx[MaxInstSrcRegs];
209
210  public:
211    /** BaseDynInst constructor given a binary instruction. */
212    BaseDynInst(MachInst inst, Addr PC, Addr Pred_PC, InstSeqNum seq_num,
213                FullCPU *cpu);
214
215    /** BaseDynInst constructor given a static inst pointer. */
216    BaseDynInst(StaticInstPtr<ISA> &_staticInst);
217
218    /** BaseDynInst destructor. */
219    ~BaseDynInst();
220
221  private:
222    void initVars();
223
224  public:
225    void
226    trace_mem(Fault fault,      // last fault
227              MemCmd cmd,       // last command
228              Addr addr,        // virtual address of access
229              void *p,          // memory accessed
230              int nbytes);      // access size
231
232    /** Dumps out contents of this BaseDynInst. */
233    void dump();
234
235    /** Dumps out contents of this BaseDynInst into given string. */
236    void dump(std::string &outstring);
237
238    /** Returns the fault type. */
239    Fault getFault() { return fault; }
240
241    /** Checks whether or not this instruction has had its branch target
242     *  calculated yet.  For now it is not utilized and is hacked to be
243     *  always false.
244     */
245    bool doneTargCalc() { return false; }
246
247    /** Returns the calculated target of the branch. */
248//    Addr readCalcTarg() { return nextPC; }
249
250    Addr readNextPC() { return nextPC; }
251
252    /** Set the predicted target of this current instruction. */
253    void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; }
254
255    /** Returns the predicted target of the branch. */
256    Addr readPredTarg() { return predPC; }
257
258    /** Returns whether the instruction was predicted taken or not. */
259    bool predTaken() {
260        return( predPC != (PC + sizeof(MachInst) ) );
261    }
262
263    /** Returns whether the instruction mispredicted. */
264    bool mispredicted() { return (predPC != nextPC); }
265
266    //
267    //  Instruction types.  Forward checks to StaticInst object.
268    //
269    bool isNop()	  const { return staticInst->isNop(); }
270    bool isMemRef()    	  const { return staticInst->isMemRef(); }
271    bool isLoad()	  const { return staticInst->isLoad(); }
272    bool isStore()	  const { return staticInst->isStore(); }
273    bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
274    bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
275    bool isCopy()         const { return staticInst->isCopy(); }
276    bool isInteger()	  const { return staticInst->isInteger(); }
277    bool isFloating()	  const { return staticInst->isFloating(); }
278    bool isControl()	  const { return staticInst->isControl(); }
279    bool isCall()	  const { return staticInst->isCall(); }
280    bool isReturn()	  const { return staticInst->isReturn(); }
281    bool isDirectCtrl()	  const { return staticInst->isDirectCtrl(); }
282    bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
283    bool isCondCtrl()	  const { return staticInst->isCondCtrl(); }
284    bool isUncondCtrl()	  const { return staticInst->isUncondCtrl(); }
285    bool isThreadSync()   const { return staticInst->isThreadSync(); }
286    bool isSerializing()  const { return staticInst->isSerializing(); }
287    bool isMemBarrier()   const { return staticInst->isMemBarrier(); }
288    bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
289    bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
290
291    /** Returns the opclass of this instruction. */
292    OpClass opClass() const { return staticInst->opClass(); }
293
294    /** Returns the branch target address. */
295    Addr branchTarget() const { return staticInst->branchTarget(PC); }
296
297    int8_t numSrcRegs()	 const { return staticInst->numSrcRegs(); }
298    int8_t numDestRegs() const { return staticInst->numDestRegs(); }
299
300    // the following are used to track physical register usage
301    // for machines with separate int & FP reg files
302    int8_t numFPDestRegs()  const { return staticInst->numFPDestRegs(); }
303    int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
304
305    /** Returns the logical register index of the i'th destination register. */
306    RegIndex destRegIdx(int i) const
307    {
308        return staticInst->destRegIdx(i);
309    }
310
311    /** Returns the logical register index of the i'th source register. */
312    RegIndex srcRegIdx(int i) const
313    {
314        return staticInst->srcRegIdx(i);
315    }
316
317    uint64_t readIntResult() { return instResult.integer; }
318    float readFloatResult() { return instResult.fp; }
319    double readDoubleResult() { return instResult.dbl; }
320
321    //Push to .cc file.
322    /** Records that one of the source registers is ready. */
323    void markSrcRegReady()
324    {
325        ++readyRegs;
326        if(readyRegs == numSrcRegs()) {
327            canIssue = true;
328        }
329    }
330
331    void markSrcRegReady(RegIndex src_idx)
332    {
333        ++readyRegs;
334
335        _readySrcRegIdx[src_idx] = 1;
336
337        if(readyRegs == numSrcRegs()) {
338            canIssue = true;
339        }
340    }
341
342    bool isReadySrcRegIdx(int idx) const
343    {
344        return this->_readySrcRegIdx[idx];
345    }
346
347    void setCompleted() { completed = true; }
348
349    bool isCompleted() const { return completed; }
350
351    /** Sets this instruction as ready to issue. */
352    void setCanIssue() { canIssue = true; }
353
354    /** Returns whether or not this instruction is ready to issue. */
355    bool readyToIssue() const { return canIssue; }
356
357    /** Sets this instruction as issued from the IQ. */
358    void setIssued() { issued = true; }
359
360    /** Returns whether or not this instruction has issued. */
361    bool isIssued() const { return issued; }
362
363    /** Sets this instruction as executed. */
364    void setExecuted() { executed = true; }
365
366    /** Returns whether or not this instruction has executed. */
367    bool isExecuted() const { return executed; }
368
369    /** Sets this instruction as ready to commit. */
370    void setCanCommit() { canCommit = true; }
371
372    /** Clears this instruction as being ready to commit. */
373    void clearCanCommit() { canCommit = false; }
374
375    /** Returns whether or not this instruction is ready to commit. */
376    bool readyToCommit() const { return canCommit; }
377
378    /** Sets this instruction as squashed. */
379    void setSquashed() { squashed = true; }
380
381    /** Returns whether or not this instruction is squashed. */
382    bool isSquashed() const { return squashed; }
383
384    /** Sets this instruction as squashed in the IQ. */
385    void setSquashedInIQ() { squashedInIQ = true; }
386
387    /** Returns whether or not this instruction is squashed in the IQ. */
388    bool isSquashedInIQ() const { return squashedInIQ; }
389
390    /** Read the PC of this instruction. */
391    const Addr readPC() const { return PC; }
392
393    /** Set the next PC of this instruction (its actual target). */
394    void setNextPC(uint64_t val) { nextPC = val; }
395
396    ExecContext *xcBase() { return xc; }
397
398  private:
399    Addr instEffAddr;
400    bool eaCalcDone;
401
402  public:
403    void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
404    const Addr &getEA() const { return instEffAddr; }
405    bool doneEACalc() { return eaCalcDone; }
406    bool eaSrcsReady();
407};
408
409template<class Impl>
410template<class T>
411inline Fault
412BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
413{
414    MemReqPtr req = new MemReq(addr, xc, sizeof(T), flags);
415    req->asid = asid;
416
417    fault = cpu->translateDataReadReq(req);
418
419    // Record key MemReq parameters so we can generate another one
420    // just like it for the timing access without calling translate()
421    // again (which might mess up the TLB).
422    effAddr = req->vaddr;
423    physEffAddr = req->paddr;
424    memReqFlags = req->flags;
425
426    /**
427     * @todo
428     * Replace the disjoint functional memory with a unified one and remove
429     * this hack.
430     */
431#ifndef FULL_SYSTEM
432    req->paddr = req->vaddr;
433#endif
434
435    if (fault == No_Fault) {
436        fault = cpu->read(req, data);
437    }
438    else {
439        // Return a fixed value to keep simulation deterministic even
440        // along misspeculated paths.
441        data = (T)-1;
442    }
443
444    if (traceData) {
445        traceData->setAddr(addr);
446        traceData->setData(data);
447    }
448
449    return fault;
450}
451
452template<class Impl>
453template<class T>
454inline Fault
455BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
456{
457    if (traceData) {
458        traceData->setAddr(addr);
459        traceData->setData(data);
460    }
461
462    storeSize = sizeof(T);
463    storeData = data;
464
465    MemReqPtr req = new MemReq(addr, xc, sizeof(T), flags);
466
467    req->asid = asid;
468
469    fault = cpu->translateDataWriteReq(req);
470
471    // Record key MemReq parameters so we can generate another one
472    // just like it for the timing access without calling translate()
473    // again (which might mess up the TLB).
474    effAddr = req->vaddr;
475    physEffAddr = req->paddr;
476    memReqFlags = req->flags;
477
478    /**
479     * @todo
480     * Replace the disjoint functional memory with a unified one and remove
481     * this hack.
482     */
483#ifndef FULL_SYSTEM
484    req->paddr = req->vaddr;
485#endif
486
487    if (fault == No_Fault) {
488        fault = cpu->write(req, data);
489    }
490
491    if (res) {
492        // always return some result to keep misspeculated paths
493        // (which will ignore faults) deterministic
494        *res = (fault == No_Fault) ? req->result : 0;
495    }
496
497    return fault;
498}
499
500#endif // __CPU_BASE_DYN_INST_HH__
501