base_dyn_inst.hh revision 13652
11689SN/A/* 210331Smitch.hayenga@arm.com * Copyright (c) 2011, 2013, 2016-2018 ARM Limited 39916Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48707Sandreas.hansson@arm.com * All rights reserved. 58707Sandreas.hansson@arm.com * 68707Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 78707Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 88707Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 98707Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 108707Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 118707Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 128707Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 138707Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 148707Sandreas.hansson@arm.com * 152325SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 167897Shestness@cs.utexas.edu * Copyright (c) 2009 The University of Edinburgh 171689SN/A * All rights reserved. 181689SN/A * 191689SN/A * Redistribution and use in source and binary forms, with or without 201689SN/A * modification, are permitted provided that the following conditions are 211689SN/A * met: redistributions of source code must retain the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer; 231689SN/A * redistributions in binary form must reproduce the above copyright 241689SN/A * notice, this list of conditions and the following disclaimer in the 251689SN/A * documentation and/or other materials provided with the distribution; 261689SN/A * neither the name of the copyright holders nor the names of its 271689SN/A * contributors may be used to endorse or promote products derived from 281689SN/A * this software without specific prior written permission. 291689SN/A * 301689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 311689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 321689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 331689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 341689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 351689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 361689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 371689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 381689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 391689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 401689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 412665Ssaidi@eecs.umich.edu * 422665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 432756Sksewell@umich.edu * Timothy M. Jones 447897Shestness@cs.utexas.edu */ 451689SN/A 461689SN/A#ifndef __CPU_BASE_DYN_INST_HH__ 478779Sgblack@eecs.umich.edu#define __CPU_BASE_DYN_INST_HH__ 486658Snate@binkert.org 498887Sgeoffrey.blake@arm.com#include <array> 508887Sgeoffrey.blake@arm.com#include <bitset> 518229Snate@binkert.org#include <deque> 528229Snate@binkert.org#include <list> 538229Snate@binkert.org#include <string> 544762Snate@binkert.org 558779Sgblack@eecs.umich.edu#include "arch/generic/tlb.hh" 564762Snate@binkert.org#include "arch/utility.hh" 574762Snate@binkert.org#include "base/trace.hh" 588232Snate@binkert.org#include "config/the_isa.hh" 599152Satgutier@umich.edu#include "cpu/checker/cpu.hh" 608232Snate@binkert.org#include "cpu/exec_context.hh" 618232Snate@binkert.org#include "cpu/exetrace.hh" 624762Snate@binkert.org#include "cpu/inst_res.hh" 634762Snate@binkert.org#include "cpu/inst_seq.hh" 648793Sgblack@eecs.umich.edu#include "cpu/o3/comm.hh" 658779Sgblack@eecs.umich.edu#include "cpu/op_class.hh" 664762Snate@binkert.org#include "cpu/static_inst.hh" 678460SAli.Saidi@ARM.com#include "cpu/translation.hh" 684762Snate@binkert.org#include "mem/packet.hh" 695702Ssaidi@eecs.umich.edu#include "mem/request.hh" 705702Ssaidi@eecs.umich.edu#include "sim/byteswap.hh" 718232Snate@binkert.org#include "sim/system.hh" 725702Ssaidi@eecs.umich.edu 735702Ssaidi@eecs.umich.edu/** 748737Skoansin.tan@gmail.com * @file 755529Snate@binkert.org * Defines a dynamic instruction context. 762669Sktlim@umich.edu */ 776221Snate@binkert.org 781060SN/Atemplate <class Impl> 795529Snate@binkert.orgclass BaseDynInst : public ExecContext, public RefCounted 805712Shsul@eecs.umich.edu{ 811060SN/A public: 821060SN/A // Typedef for the CPU. 831060SN/A typedef typename Impl::CPUType ImplCPU; 842292SN/A typedef typename ImplCPU::ImplState ImplState; 852733Sktlim@umich.edu using VecRegContainer = TheISA::VecRegContainer; 862292SN/A 872292SN/A using LSQRequestPtr = typename Impl::CPUPol::LSQ::LSQRequest*; 882292SN/A using LQIterator = typename Impl::CPUPol::LSQUnit::LQIterator; 892292SN/A using SQIterator = typename Impl::CPUPol::LSQUnit::SQIterator; 908707Sandreas.hansson@arm.com 918707Sandreas.hansson@arm.com // The DynInstPtr type. 928975Sandreas.hansson@arm.com typedef typename Impl::DynInstPtr DynInstPtr; 938707Sandreas.hansson@arm.com typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr; 948707Sandreas.hansson@arm.com 9510821Sandreas.hansson@arm.com // The list of instructions iterator type. 9610821Sandreas.hansson@arm.com typedef typename std::list<DynInstPtr>::iterator ListIt; 9710821Sandreas.hansson@arm.com 988948Sandreas.hansson@arm.com enum { 998707Sandreas.hansson@arm.com MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 1008707Sandreas.hansson@arm.com MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs 1018707Sandreas.hansson@arm.com }; 1028707Sandreas.hansson@arm.com 1038707Sandreas.hansson@arm.com protected: 1048707Sandreas.hansson@arm.com enum Status { 10510713Sandreas.hansson@arm.com IqEntry, /// Instruction is in the IQ 1068707Sandreas.hansson@arm.com RobEntry, /// Instruction is in the ROB 10710713Sandreas.hansson@arm.com LsqEntry, /// Instruction is in the LSQ 1088707Sandreas.hansson@arm.com Completed, /// Instruction has completed 1098707Sandreas.hansson@arm.com ResultReady, /// Instruction has its result 1108707Sandreas.hansson@arm.com CanIssue, /// Instruction can issue and execute 1118707Sandreas.hansson@arm.com Issued, /// Instruction has issued 1128975Sandreas.hansson@arm.com Executed, /// Instruction has executed 1138707Sandreas.hansson@arm.com CanCommit, /// Instruction can commit 1148975Sandreas.hansson@arm.com AtCommit, /// Instruction has reached commit 1158707Sandreas.hansson@arm.com Committed, /// Instruction has committed 1168707Sandreas.hansson@arm.com Squashed, /// Instruction is squashed 1178707Sandreas.hansson@arm.com SquashedInIQ, /// Instruction is squashed in the IQ 1188975Sandreas.hansson@arm.com SquashedInLSQ, /// Instruction is squashed in the LSQ 1198975Sandreas.hansson@arm.com SquashedInROB, /// Instruction is squashed in the ROB 1208948Sandreas.hansson@arm.com RecoverInst, /// Is a recover instruction 12111148Smitch.hayenga@arm.com BlockingInst, /// Is a blocking instruction 12211148Smitch.hayenga@arm.com ThreadsyncWait, /// Is a thread synchronization instruction 12311151Smitch.hayenga@arm.com SerializeBefore, /// Needs to serialize on 12411148Smitch.hayenga@arm.com /// instructions ahead of it 12510529Smorr@cs.wisc.edu SerializeAfter, /// Needs to serialize instructions behind it 1268975Sandreas.hansson@arm.com SerializeHandled, /// Serialization has been handled 1278948Sandreas.hansson@arm.com NumStatus 1288948Sandreas.hansson@arm.com }; 1298948Sandreas.hansson@arm.com 1308707Sandreas.hansson@arm.com enum Flags { 13110713Sandreas.hansson@arm.com NotAnInst, 1328707Sandreas.hansson@arm.com TranslationStarted, 13310713Sandreas.hansson@arm.com TranslationCompleted, 1348707Sandreas.hansson@arm.com PossibleLoadViolation, 1358707Sandreas.hansson@arm.com HitExternalSnoop, 1361060SN/A EffAddrValid, 1371755SN/A RecordResult, 1385606Snate@binkert.org Predicate, 1391060SN/A PredTaken, 1401060SN/A IsStrictlyOrdered, 1411060SN/A ReqMade, 1421060SN/A MemOpDone, 1431060SN/A MaxFlags 1441755SN/A }; 1451060SN/A 1461060SN/A public: 1471060SN/A /** The sequence number of the instruction. */ 1481060SN/A InstSeqNum seqNum; 1491060SN/A 1501060SN/A /** The StaticInst used by this BaseDynInst. */ 1515336Shines@cs.fsu.edu const StaticInstPtr staticInst; 1521060SN/A 1534873Sstever@eecs.umich.edu /** Pointer to the Impl's CPU object. */ 1541060SN/A ImplCPU *cpu; 1551060SN/A 1561060SN/A BaseCPU *getCpuPtr() { return cpu; } 1575595Sgblack@eecs.umich.edu 1582733Sktlim@umich.edu /** Pointer to the thread state. */ 1593781Sgblack@eecs.umich.edu ImplState *thread; 1603781Sgblack@eecs.umich.edu 1611060SN/A /** The kind of fault this instruction has generated. */ 1625737Scws3k@cs.virginia.edu Fault fault; 1635737Scws3k@cs.virginia.edu 1645737Scws3k@cs.virginia.edu /** InstRecord that tracks this instructions. */ 1652292SN/A Trace::InstRecord *traceData; 1665595Sgblack@eecs.umich.edu 1675595Sgblack@eecs.umich.edu protected: 1685595Sgblack@eecs.umich.edu /** The result of the instruction; assumes an instruction can have many 1695595Sgblack@eecs.umich.edu * destination registers. 1705595Sgblack@eecs.umich.edu */ 1711060SN/A std::queue<InstResult> instResult; 1729915Ssteve.reinhardt@amd.com 1739920Syasuko.eckert@amd.com /** PC state for this instruction. */ 17410935Snilay@cs.wisc.edu TheISA::PCState pc; 1751060SN/A 1769919Ssteve.reinhardt@amd.com /* An amalgamation of a lot of boolean values into one */ 1771060SN/A std::bitset<MaxFlags> instFlags; 1789954SFaissal.Sleiman@arm.com 1791060SN/A /** The status of this BaseDynInst. Several bits can be set. */ 1809916Ssteve.reinhardt@amd.com std::bitset<NumStatus> status; 1819916Ssteve.reinhardt@amd.com 1829916Ssteve.reinhardt@amd.com /** Whether or not the source register is ready. 1831060SN/A * @todo: Not sure this should be here vs the derived class. 1849384SAndreas.Sandberg@arm.com */ 1859384SAndreas.Sandberg@arm.com std::bitset<MaxInstSrcRegs> _readySrcRegIdx; 1868707Sandreas.hansson@arm.com 1878707Sandreas.hansson@arm.com public: 1888707Sandreas.hansson@arm.com /** The thread this instruction is from. */ 1892873Sktlim@umich.edu ThreadID threadNumber; 1902873Sktlim@umich.edu 1912873Sktlim@umich.edu /** Iterator pointing to this BaseDynInst in the list of all insts. */ 1922873Sktlim@umich.edu ListIt instListIt; 1932873Sktlim@umich.edu 1945804Snate@binkert.org ////////////////////// Branch Data /////////////// 1952873Sktlim@umich.edu /** Predicted PC state after this instruction. */ 1962873Sktlim@umich.edu TheISA::PCState predPC; 1971060SN/A 1981060SN/A /** The Macroop if one exists */ 1992292SN/A const StaticInstPtr macroop; 2009180Sandreas.hansson@arm.com 2011060SN/A /** How many source registers are ready. */ 2029433SAndreas.Sandberg@ARM.com uint8_t readyRegs; 2033221Sktlim@umich.edu 2043221Sktlim@umich.edu public: 2059152Satgutier@umich.edu /////////////////////// Load Store Data ////////////////////// 2063221Sktlim@umich.edu /** The effective virtual address (lds & stores only). */ 2071681SN/A Addr effAddr; 2082794Sktlim@umich.edu 2092316SN/A /** The effective physical address. */ 2108733Sgeoffrey.blake@arm.com Addr physEffAddr; 2118707Sandreas.hansson@arm.com 2122316SN/A /** The memory request flags (from translation). */ 2134598Sbinkertn@umich.edu unsigned memReqFlags; 2144598Sbinkertn@umich.edu 2154598Sbinkertn@umich.edu /** data address space ID, for loads & stores. */ 2162316SN/A short asid; 2178793Sgblack@eecs.umich.edu 2188793Sgblack@eecs.umich.edu /** The size of the request */ 2198793Sgblack@eecs.umich.edu uint8_t effSize; 2208793Sgblack@eecs.umich.edu 2211681SN/A /** Pointer to the data for the memory access. */ 2222325SN/A uint8_t *memData; 2232325SN/A 2242325SN/A /** Load queue index. */ 2251060SN/A int16_t lqIdx; 2262292SN/A LQIterator lqIt; 2272292SN/A 2282292SN/A /** Store queue index. */ 2292292SN/A int16_t sqIdx; 2302292SN/A SQIterator sqIt; 2312292SN/A 2321060SN/A 2331060SN/A /////////////////////// TLB Miss ////////////////////// 2341060SN/A /** 2351060SN/A * Saved memory request (needed when the DTB address translation is 2361060SN/A * delayed due to a hw page table walk). 2371060SN/A */ 2381060SN/A LSQRequestPtr savedReq; 2391060SN/A 2401060SN/A /////////////////////// Checker ////////////////////// 2411060SN/A // Need a copy of main request pointer to verify on writes. 2421060SN/A RequestPtr reqToVerify; 2432292SN/A 2441060SN/A protected: 2451060SN/A /** Flattened register index of the destination registers of this 2461060SN/A * instruction. 2471060SN/A */ 2481060SN/A std::array<RegId, TheISA::MaxInstDestRegs> _flatDestRegIdx; 2491060SN/A 2501060SN/A /** Physical register index of the destination registers of this 2511060SN/A * instruction. 2522292SN/A */ 2532292SN/A std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _destRegIdx; 2542292SN/A 2552292SN/A /** Physical register index of the source registers of this 2568793Sgblack@eecs.umich.edu * instruction. 2578793Sgblack@eecs.umich.edu */ 2588793Sgblack@eecs.umich.edu std::array<PhysRegIdPtr, TheISA::MaxInstSrcRegs> _srcRegIdx; 2598793Sgblack@eecs.umich.edu 2608793Sgblack@eecs.umich.edu /** Physical register index of the previous producers of the 2612831Sksewell@umich.edu * architected destinations. 2628793Sgblack@eecs.umich.edu */ 2638793Sgblack@eecs.umich.edu std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _prevDestRegIdx; 2648793Sgblack@eecs.umich.edu 2658793Sgblack@eecs.umich.edu 2668793Sgblack@eecs.umich.edu public: 2672831Sksewell@umich.edu /** Records changes to result? */ 2682292SN/A void recordResult(bool f) { instFlags[RecordResult] = f; } 2692316SN/A 2702292SN/A /** Is the effective virtual address valid. */ 2712292SN/A bool effAddrValid() const { return instFlags[EffAddrValid]; } 2729920Syasuko.eckert@amd.com void effAddrValid(bool b) { instFlags[EffAddrValid] = b; } 2732292SN/A 2742292SN/A /** Whether or not the memory operation is done. */ 2752292SN/A bool memOpDone() const { return instFlags[MemOpDone]; } 2762292SN/A void memOpDone(bool f) { instFlags[MemOpDone] = f; } 2771060SN/A 2786221Snate@binkert.org bool notAnInst() const { return instFlags[NotAnInst]; } 2799384SAndreas.Sandberg@arm.com void setNotAnInst() { instFlags[NotAnInst] = true; } 2809384SAndreas.Sandberg@arm.com 2819919Ssteve.reinhardt@amd.com 2829919Ssteve.reinhardt@amd.com //////////////////////////////////////////// 2839919Ssteve.reinhardt@amd.com // 2849919Ssteve.reinhardt@amd.com // INSTRUCTION EXECUTION 2859919Ssteve.reinhardt@amd.com // 2869919Ssteve.reinhardt@amd.com //////////////////////////////////////////// 2872292SN/A 2889919Ssteve.reinhardt@amd.com void demapPage(Addr vaddr, uint64_t asn) 2899919Ssteve.reinhardt@amd.com { 2902292SN/A cpu->demapPage(vaddr, asn); 2919919Ssteve.reinhardt@amd.com } 2929919Ssteve.reinhardt@amd.com void demapInstPage(Addr vaddr, uint64_t asn) 2932292SN/A { 2942292SN/A cpu->demapPage(vaddr, asn); 2959919Ssteve.reinhardt@amd.com } 2969919Ssteve.reinhardt@amd.com void demapDataPage(Addr vaddr, uint64_t asn) 2979919Ssteve.reinhardt@amd.com { 2989919Ssteve.reinhardt@amd.com cpu->demapPage(vaddr, asn); 2999919Ssteve.reinhardt@amd.com } 3009919Ssteve.reinhardt@amd.com 3019919Ssteve.reinhardt@amd.com Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags); 3029919Ssteve.reinhardt@amd.com 3039919Ssteve.reinhardt@amd.com Fault writeMem(uint8_t *data, unsigned size, Addr addr, 3049919Ssteve.reinhardt@amd.com Request::Flags flags, uint64_t *res); 3059919Ssteve.reinhardt@amd.com 3069919Ssteve.reinhardt@amd.com Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags, 3079919Ssteve.reinhardt@amd.com AtomicOpFunctor *amo_op); 3089919Ssteve.reinhardt@amd.com 3099919Ssteve.reinhardt@amd.com /** True if the DTB address translation has started. */ 3109919Ssteve.reinhardt@amd.com bool translationStarted() const { return instFlags[TranslationStarted]; } 3119920Syasuko.eckert@amd.com void translationStarted(bool f) { instFlags[TranslationStarted] = f; } 3129920Syasuko.eckert@amd.com 3139920Syasuko.eckert@amd.com /** True if the DTB address translation has completed. */ 3149920Syasuko.eckert@amd.com bool translationCompleted() const { return instFlags[TranslationCompleted]; } 3159920Syasuko.eckert@amd.com void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; } 3169920Syasuko.eckert@amd.com 3179919Ssteve.reinhardt@amd.com /** True if this address was found to match a previous load and they issued 3189919Ssteve.reinhardt@amd.com * out of order. If that happend, then it's only a problem if an incoming 3192292SN/A * snoop invalidate modifies the line, in which case we need to squash. 3202292SN/A * If nothing modified the line the order doesn't matter. 3211060SN/A */ 3222292SN/A bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; } 3231060SN/A void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; } 3241060SN/A 3252292SN/A /** True if the address hit a external snoop while sitting in the LSQ. 3269158Sandreas.hansson@arm.com * If this is true and a older instruction sees it, this instruction must 3276221Snate@binkert.org * reexecute 3283093Sksewell@umich.edu */ 3296221Snate@binkert.org bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; } 3306221Snate@binkert.org void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; } 3316221Snate@binkert.org 3323093Sksewell@umich.edu /** 3335595Sgblack@eecs.umich.edu * Returns true if the DTB address translation is being delayed due to a hw 3345595Sgblack@eecs.umich.edu * page table walk. 3355595Sgblack@eecs.umich.edu */ 3365595Sgblack@eecs.umich.edu bool isTranslationDelayed() const 3375595Sgblack@eecs.umich.edu { 3386221Snate@binkert.org return (translationStarted() && !translationCompleted()); 3398793Sgblack@eecs.umich.edu } 3408793Sgblack@eecs.umich.edu 3418793Sgblack@eecs.umich.edu public: 3428793Sgblack@eecs.umich.edu#ifdef DEBUG 3438793Sgblack@eecs.umich.edu void dumpSNList(); 3448793Sgblack@eecs.umich.edu#endif 3458793Sgblack@eecs.umich.edu 3468793Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th destination 3478793Sgblack@eecs.umich.edu * register. 3488793Sgblack@eecs.umich.edu */ 3498793Sgblack@eecs.umich.edu PhysRegIdPtr renamedDestRegIdx(int idx) const 3505595Sgblack@eecs.umich.edu { 3518793Sgblack@eecs.umich.edu return _destRegIdx[idx]; 3528793Sgblack@eecs.umich.edu } 3538793Sgblack@eecs.umich.edu 3548793Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th source register. */ 3558793Sgblack@eecs.umich.edu PhysRegIdPtr renamedSrcRegIdx(int idx) const 3568793Sgblack@eecs.umich.edu { 3575595Sgblack@eecs.umich.edu assert(TheISA::MaxInstSrcRegs > idx); 3588793Sgblack@eecs.umich.edu return _srcRegIdx[idx]; 3598793Sgblack@eecs.umich.edu } 3608793Sgblack@eecs.umich.edu 3618793Sgblack@eecs.umich.edu /** Returns the flattened register index of the i'th destination 3628793Sgblack@eecs.umich.edu * register. 3635595Sgblack@eecs.umich.edu */ 3645595Sgblack@eecs.umich.edu const RegId& flattenedDestRegIdx(int idx) const 3655595Sgblack@eecs.umich.edu { 3665595Sgblack@eecs.umich.edu return _flatDestRegIdx[idx]; 3675595Sgblack@eecs.umich.edu } 3685595Sgblack@eecs.umich.edu 3695595Sgblack@eecs.umich.edu /** Returns the physical register index of the previous physical register 3705595Sgblack@eecs.umich.edu * that remapped to the same logical register index. 3715595Sgblack@eecs.umich.edu */ 3725595Sgblack@eecs.umich.edu PhysRegIdPtr prevDestRegIdx(int idx) const 3735595Sgblack@eecs.umich.edu { 3745595Sgblack@eecs.umich.edu return _prevDestRegIdx[idx]; 3755595Sgblack@eecs.umich.edu } 3765595Sgblack@eecs.umich.edu 3775595Sgblack@eecs.umich.edu /** Renames a destination register to a physical register. Also records 3785595Sgblack@eecs.umich.edu * the previous physical register that the logical register mapped to. 3795595Sgblack@eecs.umich.edu */ 3805595Sgblack@eecs.umich.edu void renameDestReg(int idx, 3816221Snate@binkert.org PhysRegIdPtr renamed_dest, 3825595Sgblack@eecs.umich.edu PhysRegIdPtr previous_rename) 3838793Sgblack@eecs.umich.edu { 3848793Sgblack@eecs.umich.edu _destRegIdx[idx] = renamed_dest; 3858793Sgblack@eecs.umich.edu _prevDestRegIdx[idx] = previous_rename; 3868793Sgblack@eecs.umich.edu } 3875595Sgblack@eecs.umich.edu 3886221Snate@binkert.org /** Renames a source logical register to the physical register which 3895595Sgblack@eecs.umich.edu * has/will produce that logical register's result. 3905595Sgblack@eecs.umich.edu * @todo: add in whether or not the source register is ready. 3915595Sgblack@eecs.umich.edu */ 3925595Sgblack@eecs.umich.edu void renameSrcReg(int idx, PhysRegIdPtr renamed_src) 3935595Sgblack@eecs.umich.edu { 3948876Sandreas.hansson@arm.com _srcRegIdx[idx] = renamed_src; 39511150Smitch.hayenga@arm.com } 3968876Sandreas.hansson@arm.com 3978876Sandreas.hansson@arm.com /** Flattens a destination architectural register index into a logical 3988876Sandreas.hansson@arm.com * index. 3998876Sandreas.hansson@arm.com */ 4006221Snate@binkert.org void flattenDestReg(int idx, const RegId& flattened_dest) 4016221Snate@binkert.org { 4021060SN/A _flatDestRegIdx[idx] = flattened_dest; 4031060SN/A } 4041060SN/A /** BaseDynInst constructor given a binary instruction. 4051755SN/A * @param staticInst A StaticInstPtr to the underlying instruction. 4061060SN/A * @param pc The PC state for the instruction. 4071060SN/A * @param predPC The predicted next PC state for the instruction. 4081060SN/A * @param seq_num The sequence number of the instruction. 4091060SN/A * @param cpu Pointer to the instruction's CPU. 4101060SN/A */ 41110023Smatt.horsnell@ARM.com BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop, 41210023Smatt.horsnell@ARM.com TheISA::PCState pc, TheISA::PCState predPC, 41310464SAndreas.Sandberg@ARM.com InstSeqNum seq_num, ImplCPU *cpu); 41410464SAndreas.Sandberg@ARM.com 41510023Smatt.horsnell@ARM.com /** BaseDynInst constructor given a StaticInst pointer. 41610023Smatt.horsnell@ARM.com * @param _staticInst The StaticInst for this BaseDynInst. 41710464SAndreas.Sandberg@ARM.com */ 41810023Smatt.horsnell@ARM.com BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop); 41911246Sradhika.jagtap@ARM.com 42010023Smatt.horsnell@ARM.com /** BaseDynInst destructor. */ 42110023Smatt.horsnell@ARM.com ~BaseDynInst(); 42210023Smatt.horsnell@ARM.com 42310023Smatt.horsnell@ARM.com private: 42410023Smatt.horsnell@ARM.com /** Function to initialize variables in the constructors. */ 42510023Smatt.horsnell@ARM.com void initVars(); 4265595Sgblack@eecs.umich.edu 4271062SN/A public: 4282733Sktlim@umich.edu /** Dumps out contents of this BaseDynInst. */ 4292292SN/A void dump(); 4302733Sktlim@umich.edu 4312292SN/A /** Dumps out contents of this BaseDynInst into given string. */ 4322292SN/A void dump(std::string &outstring); 4332292SN/A 4342292SN/A /** Read this CPU's ID. */ 4352292SN/A int cpuId() const { return cpu->cpuId(); } 4362292SN/A 4372292SN/A /** Read this CPU's Socket ID. */ 4382292SN/A uint32_t socketId() const { return cpu->socketId(); } 4392292SN/A 4402292SN/A /** Read this CPU's data requestor ID */ 4412292SN/A MasterID masterId() const { return cpu->dataMasterId(); } 4422292SN/A 4438627SAli.Saidi@ARM.com /** Read this context's system-wide ID **/ 4448627SAli.Saidi@ARM.com ContextID contextId() const { return thread->contextId(); } 4458627SAli.Saidi@ARM.com 4468627SAli.Saidi@ARM.com /** Returns the fault type. */ 4478627SAli.Saidi@ARM.com Fault getFault() const { return fault; } 4488627SAli.Saidi@ARM.com /** TODO: This I added for the LSQRequest side to be able to modify the 4492292SN/A * fault. There should be a better mechanism in place. */ 4502292SN/A Fault& getFault() { return fault; } 4512292SN/A 4522292SN/A /** Checks whether or not this instruction has had its branch target 4532292SN/A * calculated yet. For now it is not utilized and is hacked to be 4542292SN/A * always false. 4552292SN/A * @todo: Actually use this instruction. 45610225Snilay@cs.wisc.edu */ 45710225Snilay@cs.wisc.edu bool doneTargCalc() { return false; } 4582292SN/A 4598834Satgutier@umich.edu /** Set the predicted target of this current instruction. */ 4608834Satgutier@umich.edu void setPredTarg(const TheISA::PCState &_predPC) 4618834Satgutier@umich.edu { 46210225Snilay@cs.wisc.edu predPC = _predPC; 46310225Snilay@cs.wisc.edu } 4642292SN/A 4652292SN/A const TheISA::PCState &readPredTarg() { return predPC; } 4662292SN/A 4672292SN/A /** Returns the predicted PC immediately after the branch. */ 4682292SN/A Addr predInstAddr() { return predPC.instAddr(); } 4694392Sktlim@umich.edu 4702292SN/A /** Returns the predicted PC two instructions after the branch */ 4712292SN/A Addr predNextInstAddr() { return predPC.nextInstAddr(); } 4722292SN/A 4732292SN/A /** Returns the predicted micro PC after the branch */ 4742292SN/A Addr predMicroPC() { return predPC.microPC(); } 47510225Snilay@cs.wisc.edu 4762292SN/A /** Returns whether the instruction was predicted taken or not. */ 4772292SN/A bool readPredTaken() 4782292SN/A { 4792292SN/A return instFlags[PredTaken]; 4802292SN/A } 4814392Sktlim@umich.edu 4822292SN/A void setPredTaken(bool predicted_taken) 4832292SN/A { 4842292SN/A instFlags[PredTaken] = predicted_taken; 4852292SN/A } 4862292SN/A 48710225Snilay@cs.wisc.edu /** Returns whether the instruction mispredicted. */ 4882292SN/A bool mispredicted() 4895595Sgblack@eecs.umich.edu { 4905595Sgblack@eecs.umich.edu TheISA::PCState tempPC = pc; 4915595Sgblack@eecs.umich.edu TheISA::advancePC(tempPC, staticInst); 4925595Sgblack@eecs.umich.edu return !(tempPC == predPC); 4935595Sgblack@eecs.umich.edu } 4947897Shestness@cs.utexas.edu 4957897Shestness@cs.utexas.edu // 4967897Shestness@cs.utexas.edu // Instruction types. Forward checks to StaticInst object. 4977897Shestness@cs.utexas.edu // 4987897Shestness@cs.utexas.edu bool isNop() const { return staticInst->isNop(); } 4997897Shestness@cs.utexas.edu bool isMemRef() const { return staticInst->isMemRef(); } 5007897Shestness@cs.utexas.edu bool isLoad() const { return staticInst->isLoad(); } 5017897Shestness@cs.utexas.edu bool isStore() const { return staticInst->isStore(); } 5027897Shestness@cs.utexas.edu bool isAtomic() const { return staticInst->isAtomic(); } 5037897Shestness@cs.utexas.edu bool isStoreConditional() const 5047897Shestness@cs.utexas.edu { return staticInst->isStoreConditional(); } 5057897Shestness@cs.utexas.edu bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 5067897Shestness@cs.utexas.edu bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 5077897Shestness@cs.utexas.edu bool isInteger() const { return staticInst->isInteger(); } 5087897Shestness@cs.utexas.edu bool isFloating() const { return staticInst->isFloating(); } 5097897Shestness@cs.utexas.edu bool isVector() const { return staticInst->isVector(); } 5107897Shestness@cs.utexas.edu bool isControl() const { return staticInst->isControl(); } 5117897Shestness@cs.utexas.edu bool isCall() const { return staticInst->isCall(); } 5127897Shestness@cs.utexas.edu bool isReturn() const { return staticInst->isReturn(); } 5137897Shestness@cs.utexas.edu bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 5147897Shestness@cs.utexas.edu bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 5157897Shestness@cs.utexas.edu bool isCondCtrl() const { return staticInst->isCondCtrl(); } 5169920Syasuko.eckert@amd.com bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 5179920Syasuko.eckert@amd.com bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 5189920Syasuko.eckert@amd.com bool isThreadSync() const { return staticInst->isThreadSync(); } 5199920Syasuko.eckert@amd.com bool isSerializing() const { return staticInst->isSerializing(); } 5209920Syasuko.eckert@amd.com bool isSerializeBefore() const 5219920Syasuko.eckert@amd.com { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 5229920Syasuko.eckert@amd.com bool isSerializeAfter() const 5239920Syasuko.eckert@amd.com { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 5249920Syasuko.eckert@amd.com bool isSquashAfter() const { return staticInst->isSquashAfter(); } 5259920Syasuko.eckert@amd.com bool isMemBarrier() const { return staticInst->isMemBarrier(); } 5267897Shestness@cs.utexas.edu bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 5277897Shestness@cs.utexas.edu bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 5287897Shestness@cs.utexas.edu bool isQuiesce() const { return staticInst->isQuiesce(); } 5297897Shestness@cs.utexas.edu bool isIprAccess() const { return staticInst->isIprAccess(); } 5307897Shestness@cs.utexas.edu bool isUnverifiable() const { return staticInst->isUnverifiable(); } 5317897Shestness@cs.utexas.edu bool isSyscall() const { return staticInst->isSyscall(); } 5327897Shestness@cs.utexas.edu bool isMacroop() const { return staticInst->isMacroop(); } 5337897Shestness@cs.utexas.edu bool isMicroop() const { return staticInst->isMicroop(); } 5347897Shestness@cs.utexas.edu bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 5351062SN/A bool isLastMicroop() const { return staticInst->isLastMicroop(); } 5361062SN/A bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 5371062SN/A bool isMicroBranch() const { return staticInst->isMicroBranch(); } 5381062SN/A 5391755SN/A /** Temporarily sets this instruction as a serialize before instruction. */ 5401060SN/A void setSerializeBefore() { status.set(SerializeBefore); } 5412733Sktlim@umich.edu 5429444SAndreas.Sandberg@ARM.com /** Clears the serializeBefore part of this instruction. */ 54310913Sandreas.sandberg@arm.com void clearSerializeBefore() { status.reset(SerializeBefore); } 5441060SN/A 5452292SN/A /** Checks if this serializeBefore is only temporarily set. */ 54610464SAndreas.Sandberg@ARM.com bool isTempSerializeBefore() { return status[SerializeBefore]; } 5472292SN/A 5482325SN/A /** Temporarily sets this instruction as a serialize after instruction. */ 5492292SN/A void setSerializeAfter() { status.set(SerializeAfter); } 5502292SN/A 5511060SN/A /** Clears the serializeAfter part of this instruction.*/ 5521060SN/A void clearSerializeAfter() { status.reset(SerializeAfter); } 5531060SN/A 5541060SN/A /** Checks if this serializeAfter is only temporarily set. */ 5551060SN/A bool isTempSerializeAfter() { return status[SerializeAfter]; } 5561060SN/A 5571060SN/A /** Sets the serialization part of this instruction as handled. */ 5581060SN/A void setSerializeHandled() { status.set(SerializeHandled); } 5591060SN/A 5601060SN/A /** Checks if the serialization part of this instruction has been 5612292SN/A * handled. This does not apply to the temporary serializing 5621060SN/A * state; it only applies to this instruction's own permanent 5631060SN/A * serializing state. 5641060SN/A */ 5651060SN/A bool isSerializeHandled() { return status[SerializeHandled]; } 5661060SN/A 5671060SN/A /** Returns the opclass of this instruction. */ 5681060SN/A OpClass opClass() const { return staticInst->opClass(); } 5692325SN/A 5702292SN/A /** Returns the branch target address. */ 5712292SN/A TheISA::PCState branchTarget() const 5722292SN/A { return staticInst->branchTarget(pc); } 5732292SN/A 5742292SN/A /** Returns the number of source registers. */ 5752325SN/A int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 5769444SAndreas.Sandberg@ARM.com 5773226Sktlim@umich.edu /** Returns the number of destination registers. */ 5782325SN/A int8_t numDestRegs() const { return staticInst->numDestRegs(); } 5799179Sandreas.hansson@arm.com 5803221Sktlim@umich.edu // the following are used to track physical register usage 5813226Sktlim@umich.edu // for machines with separate int & FP reg files 5829179Sandreas.hansson@arm.com int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 5832325SN/A int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 5842325SN/A int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); } 5859180Sandreas.hansson@arm.com int8_t numVecDestRegs() const { return staticInst->numVecDestRegs(); } 5863226Sktlim@umich.edu int8_t numVecElemDestRegs() const 5872325SN/A { 5882292SN/A return staticInst->numVecElemDestRegs(); 5892292SN/A } 5908793Sgblack@eecs.umich.edu int8_t 5918793Sgblack@eecs.umich.edu numVecPredDestRegs() const 5929444SAndreas.Sandberg@ARM.com { 5939444SAndreas.Sandberg@ARM.com return staticInst->numVecPredDestRegs(); 5941060SN/A } 5951060SN/A 5961060SN/A /** Returns the logical register index of the i'th destination register. */ 5971060SN/A const RegId& destRegIdx(int i) const { return staticInst->destRegIdx(i); } 5981755SN/A 5991060SN/A /** Returns the logical register index of the i'th source register. */ 6005714Shsul@eecs.umich.edu const RegId& srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 6011060SN/A 6028921Sandreas.hansson@arm.com /** Return the size of the instResult queue. */ 6039382SAli.Saidi@ARM.com uint8_t resultSize() { return instResult.size(); } 6048921Sandreas.hansson@arm.com 6059382SAli.Saidi@ARM.com /** Pops a result off the instResult queue. 6068921Sandreas.hansson@arm.com * If the result stack is empty, return the default value. 6078921Sandreas.hansson@arm.com * */ 6088921Sandreas.hansson@arm.com InstResult popResult(InstResult dflt = InstResult()) 6092292SN/A { 6109433SAndreas.Sandberg@ARM.com if (!instResult.empty()) { 6118793Sgblack@eecs.umich.edu InstResult t = instResult.front(); 6128793Sgblack@eecs.umich.edu instResult.pop(); 6138793Sgblack@eecs.umich.edu return t; 6148793Sgblack@eecs.umich.edu } 6156034Ssteve.reinhardt@amd.com return dflt; 6162292SN/A } 6179382SAli.Saidi@ARM.com 6186221Snate@binkert.org /** Pushes a result onto the instResult queue. */ 6199382SAli.Saidi@ARM.com /** @{ */ 6202292SN/A /** Scalar result. */ 6219427SAndreas.Sandberg@ARM.com template<typename T> 6229427SAndreas.Sandberg@ARM.com void setScalarResult(T&& t) 6232292SN/A { 6249427SAndreas.Sandberg@ARM.com if (instFlags[RecordResult]) { 6259427SAndreas.Sandberg@ARM.com instResult.push(InstResult(std::forward<T>(t), 6269427SAndreas.Sandberg@ARM.com InstResult::ResultType::Scalar)); 6279427SAndreas.Sandberg@ARM.com } 6289992Snilay@cs.wisc.edu } 6299461Snilay@cs.wisc.edu 6309461Snilay@cs.wisc.edu /** Full vector result. */ 6319461Snilay@cs.wisc.edu template<typename T> 6329427SAndreas.Sandberg@ARM.com void setVecResult(T&& t) 6339444SAndreas.Sandberg@ARM.com { 6349427SAndreas.Sandberg@ARM.com if (instFlags[RecordResult]) { 6359427SAndreas.Sandberg@ARM.com instResult.push(InstResult(std::forward<T>(t), 6369427SAndreas.Sandberg@ARM.com InstResult::ResultType::VecReg)); 6372292SN/A } 6382292SN/A } 6392292SN/A 6402292SN/A /** Vector element result. */ 6416221Snate@binkert.org template<typename T> 6422875Sksewell@umich.edu void setVecElemResult(T&& t) 6436221Snate@binkert.org { 6445314Sstever@gmail.com if (instFlags[RecordResult]) { 6452875Sksewell@umich.edu instResult.push(InstResult(std::forward<T>(t), 6463226Sktlim@umich.edu InstResult::ResultType::VecElem)); 6479444SAndreas.Sandberg@ARM.com } 6483226Sktlim@umich.edu } 6492875Sksewell@umich.edu 6502875Sksewell@umich.edu /** Predicate result. */ 6512875Sksewell@umich.edu template<typename T> 6522875Sksewell@umich.edu void setVecPredResult(T&& t) 6532875Sksewell@umich.edu { 6542875Sksewell@umich.edu if (instFlags[RecordResult]) { 6552875Sksewell@umich.edu instResult.push(InstResult(std::forward<T>(t), 6562875Sksewell@umich.edu InstResult::ResultType::VecPredReg)); 6572875Sksewell@umich.edu } 6582875Sksewell@umich.edu } 6596221Snate@binkert.org /** @} */ 6602875Sksewell@umich.edu 6612875Sksewell@umich.edu /** Records an integer register being set to a value. */ 6626221Snate@binkert.org void setIntRegOperand(const StaticInst *si, int idx, RegVal val) 6635314Sstever@gmail.com { 6642875Sksewell@umich.edu setScalarResult(val); 6653226Sktlim@umich.edu } 6669444SAndreas.Sandberg@ARM.com 6673226Sktlim@umich.edu /** Records a CC register being set to a value. */ 6682875Sksewell@umich.edu void setCCRegOperand(const StaticInst *si, int idx, RegVal val) 6692875Sksewell@umich.edu { 6702875Sksewell@umich.edu setScalarResult(val); 6712875Sksewell@umich.edu } 6722875Sksewell@umich.edu 67310331Smitch.hayenga@arm.com /** Record a vector register being set to a value */ 67410331Smitch.hayenga@arm.com void setVecRegOperand(const StaticInst *si, int idx, 67510331Smitch.hayenga@arm.com const VecRegContainer& val) 6762875Sksewell@umich.edu { 6772875Sksewell@umich.edu setVecResult(val); 6782875Sksewell@umich.edu } 6796221Snate@binkert.org 6808834Satgutier@umich.edu /** Records an fp register being set to an integer value. */ 6816221Snate@binkert.org void 6826221Snate@binkert.org setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) 6836221Snate@binkert.org { 6846221Snate@binkert.org setScalarResult(val); 6856221Snate@binkert.org } 6866221Snate@binkert.org 6876221Snate@binkert.org /** Record a vector register being set to a value */ 6886221Snate@binkert.org void setVecElemOperand(const StaticInst *si, int idx, const VecElem val) 6896221Snate@binkert.org { 6906221Snate@binkert.org setVecElemResult(val); 6916221Snate@binkert.org } 6928834Satgutier@umich.edu 6938834Satgutier@umich.edu /** Record a vector register being set to a value */ 6948834Satgutier@umich.edu void setVecPredRegOperand(const StaticInst *si, int idx, 6958834Satgutier@umich.edu const VecPredRegContainer& val) 6968834Satgutier@umich.edu { 6978834Satgutier@umich.edu setVecPredResult(val); 6988834Satgutier@umich.edu } 6998834Satgutier@umich.edu 7008834Satgutier@umich.edu /** Records that one of the source registers is ready. */ 7018834Satgutier@umich.edu void markSrcRegReady(); 7028834Satgutier@umich.edu 7038834Satgutier@umich.edu /** Marks a specific register as ready. */ 7048834Satgutier@umich.edu void markSrcRegReady(RegIndex src_idx); 7052875Sksewell@umich.edu 70610407Smitch.hayenga@arm.com /** Returns if a source register is ready. */ 7072875Sksewell@umich.edu bool isReadySrcRegIdx(int idx) const 7089444SAndreas.Sandberg@ARM.com { 7099444SAndreas.Sandberg@ARM.com return this->_readySrcRegIdx[idx]; 7102875Sksewell@umich.edu } 71110407Smitch.hayenga@arm.com 7122875Sksewell@umich.edu /** Sets this instruction as completed. */ 7139444SAndreas.Sandberg@ARM.com void setCompleted() { status.set(Completed); } 7149444SAndreas.Sandberg@ARM.com 7159444SAndreas.Sandberg@ARM.com /** Returns whether or not this instruction is completed. */ 71610913Sandreas.sandberg@arm.com bool isCompleted() const { return status[Completed]; } 7179444SAndreas.Sandberg@ARM.com 7189444SAndreas.Sandberg@ARM.com /** Marks the result as ready. */ 7199158Sandreas.hansson@arm.com void setResultReady() { status.set(ResultReady); } 7209158Sandreas.hansson@arm.com 7219158Sandreas.hansson@arm.com /** Returns whether or not the result is ready. */ 72210407Smitch.hayenga@arm.com bool isResultReady() const { return status[ResultReady]; } 7232875Sksewell@umich.edu 7242875Sksewell@umich.edu /** Sets this instruction as ready to issue. */ 7252875Sksewell@umich.edu void setCanIssue() { status.set(CanIssue); } 7262875Sksewell@umich.edu 7272875Sksewell@umich.edu /** Returns whether or not this instruction is ready to issue. */ 7282875Sksewell@umich.edu bool readyToIssue() const { return status[CanIssue]; } 7299180Sandreas.hansson@arm.com 7309180Sandreas.hansson@arm.com /** Clears this instruction being able to issue. */ 7319179Sandreas.hansson@arm.com void clearCanIssue() { status.reset(CanIssue); } 7329179Sandreas.hansson@arm.com 7339179Sandreas.hansson@arm.com /** Sets this instruction as issued from the IQ. */ 7348627SAli.Saidi@ARM.com void setIssued() { status.set(Issued); } 7357823Ssteve.reinhardt@amd.com 7362875Sksewell@umich.edu /** Returns whether or not this instruction has issued. */ 7372875Sksewell@umich.edu bool isIssued() const { return status[Issued]; } 7382875Sksewell@umich.edu 7392875Sksewell@umich.edu /** Clears this instruction as being issued. */ 7402875Sksewell@umich.edu void clearIssued() { status.reset(Issued); } 7412875Sksewell@umich.edu 74210407Smitch.hayenga@arm.com /** Sets this instruction as executed. */ 7436221Snate@binkert.org void setExecuted() { status.set(Executed); } 7442875Sksewell@umich.edu 7452875Sksewell@umich.edu /** Returns whether or not this instruction has executed. */ 7469444SAndreas.Sandberg@ARM.com bool isExecuted() const { return status[Executed]; } 74710408Smitch.hayenga@arm.com 74810408Smitch.hayenga@arm.com /** Sets this instruction as ready to commit. */ 74910407Smitch.hayenga@arm.com void setCanCommit() { status.set(CanCommit); } 7503221Sktlim@umich.edu 75110683Salexandru.dutu@amd.com /** Clears this instruction as being ready to commit. */ 7522910Sksewell@umich.edu void clearCanCommit() { status.reset(CanCommit); } 75310683Salexandru.dutu@amd.com 75410683Salexandru.dutu@amd.com /** Returns whether or not this instruction is ready to commit. */ 75510683Salexandru.dutu@amd.com bool readyToCommit() const { return status[CanCommit]; } 7568627SAli.Saidi@ARM.com 7578627SAli.Saidi@ARM.com void setAtCommit() { status.set(AtCommit); } 7582875Sksewell@umich.edu 7592875Sksewell@umich.edu bool isAtCommit() { return status[AtCommit]; } 7602875Sksewell@umich.edu 7612875Sksewell@umich.edu /** Sets this instruction as committed. */ 7626221Snate@binkert.org void setCommitted() { status.set(Committed); } 7632875Sksewell@umich.edu 7642910Sksewell@umich.edu /** Returns whether or not this instruction is committed. */ 7652910Sksewell@umich.edu bool isCommitted() const { return status[Committed]; } 7669444SAndreas.Sandberg@ARM.com 76710408Smitch.hayenga@arm.com /** Sets this instruction as squashed. */ 76810408Smitch.hayenga@arm.com void setSquashed() { status.set(Squashed); } 76910408Smitch.hayenga@arm.com 7702875Sksewell@umich.edu /** Returns whether or not this instruction is squashed. */ 7712875Sksewell@umich.edu bool isSquashed() const { return status[Squashed]; } 7722875Sksewell@umich.edu 7732875Sksewell@umich.edu //Instruction Queue Entry 7746221Snate@binkert.org //----------------------- 7752292SN/A /** Sets this instruction as a entry the IQ. */ 7762847Sksewell@umich.edu void setInIQ() { status.set(IqEntry); } 7772292SN/A 7782683Sktlim@umich.edu /** Sets this instruction as a entry the IQ. */ 7798793Sgblack@eecs.umich.edu void clearInIQ() { status.reset(IqEntry); } 7808793Sgblack@eecs.umich.edu 7818793Sgblack@eecs.umich.edu /** Returns whether or not this instruction has issued. */ 7828793Sgblack@eecs.umich.edu bool isInIQ() const { return status[IqEntry]; } 7838793Sgblack@eecs.umich.edu 7842292SN/A /** Sets this instruction as squashed in the IQ. */ 7852292SN/A void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 7862292SN/A 7872292SN/A /** Returns whether or not this instruction is squashed in the IQ. */ 7882292SN/A bool isSquashedInIQ() const { return status[SquashedInIQ]; } 7892292SN/A 7902292SN/A 7912292SN/A //Load / Store Queue Functions 7922292SN/A //----------------------- 7932292SN/A /** Sets this instruction as a entry the LSQ. */ 79411225Snathananel.premillieu@arm.com void setInLSQ() { status.set(LsqEntry); } 79511225Snathananel.premillieu@arm.com 7962292SN/A /** Sets this instruction as a entry the LSQ. */ 7972292SN/A void removeInLSQ() { status.reset(LsqEntry); } 7982292SN/A 7992292SN/A /** Returns whether or not this instruction is in the LSQ. */ 8002292SN/A bool isInLSQ() const { return status[LsqEntry]; } 8012292SN/A 8029920Syasuko.eckert@amd.com /** Sets this instruction as squashed in the LSQ. */ 80311225Snathananel.premillieu@arm.com void setSquashedInLSQ() { status.set(SquashedInLSQ);} 80411225Snathananel.premillieu@arm.com 8059920Syasuko.eckert@amd.com /** Returns whether or not this instruction is squashed in the LSQ. */ 8069920Syasuko.eckert@amd.com bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 8079920Syasuko.eckert@amd.com 8089920Syasuko.eckert@amd.com 8099920Syasuko.eckert@amd.com //Reorder Buffer Functions 8109920Syasuko.eckert@amd.com //----------------------- 8119920Syasuko.eckert@amd.com /** Sets this instruction as a entry the ROB. */ 8122292SN/A void setInROB() { status.set(RobEntry); } 8132847Sksewell@umich.edu 8142292SN/A /** Sets this instruction as a entry the ROB. */ 8152847Sksewell@umich.edu void clearInROB() { status.reset(RobEntry); } 8167720Sgblack@eecs.umich.edu 8172292SN/A /** Returns whether or not this instruction is in the ROB. */ 8182680Sktlim@umich.edu bool isInROB() const { return status[RobEntry]; } 8192292SN/A 82010407Smitch.hayenga@arm.com /** Sets this instruction as squashed in the ROB. */ 8212292SN/A void setSquashedInROB() { status.set(SquashedInROB); } 8222292SN/A 8232292SN/A /** Returns whether or not this instruction is squashed in the ROB. */ 8242292SN/A bool isSquashedInROB() const { return status[SquashedInROB]; } 8252292SN/A 8262292SN/A /** Read the PC state of this instruction. */ 8272292SN/A TheISA::PCState pcState() const { return pc; } 8282292SN/A 8296221Snate@binkert.org /** Set the PC state of this instruction. */ 8302292SN/A void pcState(const TheISA::PCState &val) { pc = val; } 8312877Sksewell@umich.edu 8322847Sksewell@umich.edu /** Read the PC of this instruction. */ 8332847Sksewell@umich.edu Addr instAddr() const { return pc.instAddr(); } 8342847Sksewell@umich.edu 8355364Sksewell@umich.edu /** Read the PC of the next instruction. */ 8365364Sksewell@umich.edu Addr nextInstAddr() const { return pc.nextInstAddr(); } 8375364Sksewell@umich.edu 8385364Sksewell@umich.edu /**Read the micro PC of this instruction. */ 8395364Sksewell@umich.edu Addr microPC() const { return pc.microPC(); } 8405364Sksewell@umich.edu 8412847Sksewell@umich.edu bool readPredicate() const 8422847Sksewell@umich.edu { 8432292SN/A return instFlags[Predicate]; 8442292SN/A } 8452292SN/A 8462292SN/A void setPredicate(bool val) 8472292SN/A { 8482292SN/A instFlags[Predicate] = val; 8492847Sksewell@umich.edu 85010487Snilay@cs.wisc.edu if (traceData) { 85110487Snilay@cs.wisc.edu traceData->setPredicate(val); 8522292SN/A } 8532292SN/A } 8542292SN/A 8552292SN/A /** Sets the ASID. */ 8562292SN/A void setASID(short addr_space_id) { asid = addr_space_id; } 8579920Syasuko.eckert@amd.com short getASID() { return asid; } 85810487Snilay@cs.wisc.edu 85910487Snilay@cs.wisc.edu /** Sets the thread id. */ 8609920Syasuko.eckert@amd.com void setTid(ThreadID tid) { threadNumber = tid; } 8619920Syasuko.eckert@amd.com 8629920Syasuko.eckert@amd.com /** Sets the pointer to the thread state. */ 8639920Syasuko.eckert@amd.com void setThreadState(ImplState *state) { thread = state; } 8649920Syasuko.eckert@amd.com 8652847Sksewell@umich.edu /** Returns the thread context. */ 8668138SAli.Saidi@ARM.com ThreadContext *tcBase() { return thread->getTC(); } 8678138SAli.Saidi@ARM.com 8688138SAli.Saidi@ARM.com public: 8692292SN/A /** Returns whether or not the eff. addr. source registers are ready. */ 8702935Sksewell@umich.edu bool eaSrcsReady() const; 8712875Sksewell@umich.edu 8725363Sksewell@umich.edu /** Is this instruction's memory access strictly ordered? */ 8732935Sksewell@umich.edu bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; } 8742292SN/A void strictlyOrdered(bool so) { instFlags[IsStrictlyOrdered] = so; } 8755362Sksewell@umich.edu 8765362Sksewell@umich.edu /** Has this instruction generated a memory request. */ 8772292SN/A bool hasRequest() const { return instFlags[ReqMade]; } 8782292SN/A /** Assert this instruction has generated a memory request. */ 8792847Sksewell@umich.edu void setRequest() { instFlags[ReqMade] = true; } 8803229Sktlim@umich.edu 8813229Sktlim@umich.edu /** Returns iterator to this instruction in the list of all insts. */ 8823229Sktlim@umich.edu ListIt &getInstListIt() { return instListIt; } 8833229Sktlim@umich.edu 8843229Sktlim@umich.edu /** Sets iterator for this instruction in the list of all insts. */ 8853229Sktlim@umich.edu void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 8862292SN/A 8872292SN/A public: 8882292SN/A /** Returns the number of consecutive store conditional failures. */ 8892292SN/A unsigned int readStCondFailures() const 8903229Sktlim@umich.edu { return thread->storeCondFailures; } 8912292SN/A 8922292SN/A /** Sets the number of consecutive store conditional failures. */ 8934192Sktlim@umich.edu void setStCondFailures(unsigned int sc_failures) 8945595Sgblack@eecs.umich.edu { thread->storeCondFailures = sc_failures; } 8956221Snate@binkert.org 8965702Ssaidi@eecs.umich.edu public: 8975702Ssaidi@eecs.umich.edu // monitor/mwait funtions 8985702Ssaidi@eecs.umich.edu void armMonitor(Addr address) { cpu->armMonitor(threadNumber, address); } 8995702Ssaidi@eecs.umich.edu bool mwait(PacketPtr pkt) { return cpu->mwait(threadNumber, pkt); } 9005702Ssaidi@eecs.umich.edu void mwaitAtomic(ThreadContext *tc) 9015702Ssaidi@eecs.umich.edu { return cpu->mwaitAtomic(threadNumber, tc, cpu->dtb); } 9025702Ssaidi@eecs.umich.edu AddressMonitor *getAddrMonitor() 9035702Ssaidi@eecs.umich.edu { return cpu->getCpuAddrMonitor(threadNumber); } 9045702Ssaidi@eecs.umich.edu}; 9055702Ssaidi@eecs.umich.edu 9065702Ssaidi@eecs.umich.edutemplate<class Impl> 9075702Ssaidi@eecs.umich.eduFault 9085702Ssaidi@eecs.umich.eduBaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size, 9095702Ssaidi@eecs.umich.edu Request::Flags flags) 9106221Snate@binkert.org{ 9115702Ssaidi@eecs.umich.edu return cpu->pushRequest( 9125702Ssaidi@eecs.umich.edu dynamic_cast<typename DynInstPtr::PtrType>(this), 9135702Ssaidi@eecs.umich.edu /* ld */ true, nullptr, size, addr, flags, nullptr); 9145702Ssaidi@eecs.umich.edu} 9155702Ssaidi@eecs.umich.edu 9165702Ssaidi@eecs.umich.edutemplate<class Impl> 9175702Ssaidi@eecs.umich.eduFault 9185702Ssaidi@eecs.umich.eduBaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr, 9195702Ssaidi@eecs.umich.edu Request::Flags flags, uint64_t *res) 9205702Ssaidi@eecs.umich.edu{ 9215702Ssaidi@eecs.umich.edu return cpu->pushRequest( 9225702Ssaidi@eecs.umich.edu dynamic_cast<typename DynInstPtr::PtrType>(this), 9235702Ssaidi@eecs.umich.edu /* st */ false, data, size, addr, flags, res); 9245702Ssaidi@eecs.umich.edu} 9255702Ssaidi@eecs.umich.edu 9265702Ssaidi@eecs.umich.edutemplate<class Impl> 9275702Ssaidi@eecs.umich.eduFault 9285702Ssaidi@eecs.umich.eduBaseDynInst<Impl>::initiateMemAMO(Addr addr, unsigned size, 9295702Ssaidi@eecs.umich.edu Request::Flags flags, 9305702Ssaidi@eecs.umich.edu AtomicOpFunctor *amo_op) 9315702Ssaidi@eecs.umich.edu{ 9325702Ssaidi@eecs.umich.edu // atomic memory instructions do not have data to be written to memory yet 9335702Ssaidi@eecs.umich.edu // since the atomic operations will be executed directly in cache/memory. 9345702Ssaidi@eecs.umich.edu // Therefore, its `data` field is nullptr. 9355702Ssaidi@eecs.umich.edu // Atomic memory requests need to carry their `amo_op` fields to cache/ 9365595Sgblack@eecs.umich.edu // memory 9375595Sgblack@eecs.umich.edu return cpu->pushRequest( 9385595Sgblack@eecs.umich.edu dynamic_cast<typename DynInstPtr::PtrType>(this), 93911150Smitch.hayenga@arm.com /* atomic */ false, nullptr, size, addr, flags, nullptr, amo_op); 9405595Sgblack@eecs.umich.edu} 9415595Sgblack@eecs.umich.edu 9425595Sgblack@eecs.umich.edu#endif // __CPU_BASE_DYN_INST_HH__ 9435595Sgblack@eecs.umich.edu