base_dyn_inst.hh revision 13590
11060SN/A/* 213590Srekai.gonzalezalberquilla@arm.com * Copyright (c) 2011, 2013, 2016-2018 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47944SGiacomo.Gabrielli@arm.com * All rights reserved. 57944SGiacomo.Gabrielli@arm.com * 67944SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 77944SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 87944SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 97944SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 107944SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 117944SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 127944SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 137944SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 147944SGiacomo.Gabrielli@arm.com * 152702Sktlim@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 166973Stjones1@inf.ed.ac.uk * Copyright (c) 2009 The University of Edinburgh 171060SN/A * All rights reserved. 181060SN/A * 191060SN/A * Redistribution and use in source and binary forms, with or without 201060SN/A * modification, are permitted provided that the following conditions are 211060SN/A * met: redistributions of source code must retain the above copyright 221060SN/A * notice, this list of conditions and the following disclaimer; 231060SN/A * redistributions in binary form must reproduce the above copyright 241060SN/A * notice, this list of conditions and the following disclaimer in the 251060SN/A * documentation and/or other materials provided with the distribution; 261060SN/A * neither the name of the copyright holders nor the names of its 271060SN/A * contributors may be used to endorse or promote products derived from 281060SN/A * this software without specific prior written permission. 291060SN/A * 301060SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 311060SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 321060SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 331060SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 341060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 351060SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 361060SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 371060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 381060SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 391060SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 401060SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 412665Ssaidi@eecs.umich.edu * 422665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 436973Stjones1@inf.ed.ac.uk * Timothy M. Jones 441060SN/A */ 451060SN/A 461464SN/A#ifndef __CPU_BASE_DYN_INST_HH__ 471464SN/A#define __CPU_BASE_DYN_INST_HH__ 481060SN/A 4910835Sandreas.hansson@arm.com#include <array> 502731Sktlim@umich.edu#include <bitset> 5112109SRekai.GonzalezAlberquilla@arm.com#include <deque> 522292SN/A#include <list> 531464SN/A#include <string> 541060SN/A 5510687SAndreas.Sandberg@ARM.com#include "arch/generic/tlb.hh" 567720Sgblack@eecs.umich.edu#include "arch/utility.hh" 571060SN/A#include "base/trace.hh" 586658Snate@binkert.org#include "config/the_isa.hh" 598887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 6010319SAndreas.Sandberg@ARM.com#include "cpu/exec_context.hh" 611464SN/A#include "cpu/exetrace.hh" 6212107SRekai.GonzalezAlberquilla@arm.com#include "cpu/inst_res.hh" 631464SN/A#include "cpu/inst_seq.hh" 6412107SRekai.GonzalezAlberquilla@arm.com#include "cpu/o3/comm.hh" 652669Sktlim@umich.edu#include "cpu/op_class.hh" 661060SN/A#include "cpu/static_inst.hh" 676973Stjones1@inf.ed.ac.uk#include "cpu/translation.hh" 682669Sktlim@umich.edu#include "mem/packet.hh" 6911608Snikos.nikoleris@arm.com#include "mem/request.hh" 707678Sgblack@eecs.umich.edu#include "sim/byteswap.hh" 712292SN/A#include "sim/system.hh" 721060SN/A 731060SN/A/** 741060SN/A * @file 751060SN/A * Defines a dynamic instruction context. 761060SN/A */ 771060SN/A 781060SN/Atemplate <class Impl> 7910319SAndreas.Sandberg@ARM.comclass BaseDynInst : public ExecContext, public RefCounted 801060SN/A{ 811060SN/A public: 821060SN/A // Typedef for the CPU. 832733Sktlim@umich.edu typedef typename Impl::CPUType ImplCPU; 842733Sktlim@umich.edu typedef typename ImplCPU::ImplState ImplState; 8512109SRekai.GonzalezAlberquilla@arm.com using VecRegContainer = TheISA::VecRegContainer; 861060SN/A 8713590Srekai.gonzalezalberquilla@arm.com using LSQRequestPtr = typename Impl::CPUPol::LSQ::LSQRequest*; 8813590Srekai.gonzalezalberquilla@arm.com using LQIterator = typename Impl::CPUPol::LSQUnit::LQIterator; 8913590Srekai.gonzalezalberquilla@arm.com using SQIterator = typename Impl::CPUPol::LSQUnit::SQIterator; 9013590Srekai.gonzalezalberquilla@arm.com 912292SN/A // The DynInstPtr type. 922292SN/A typedef typename Impl::DynInstPtr DynInstPtr; 938486Sgblack@eecs.umich.edu typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr; 942292SN/A 952292SN/A // The list of instructions iterator type. 962292SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 972292SN/A 981060SN/A enum { 995543Ssaidi@eecs.umich.edu MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 1008902Sandreas.hansson@arm.com MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs 1011060SN/A }; 1021060SN/A 1039046SAli.Saidi@ARM.com protected: 1049046SAli.Saidi@ARM.com enum Status { 1059046SAli.Saidi@ARM.com IqEntry, /// Instruction is in the IQ 1069046SAli.Saidi@ARM.com RobEntry, /// Instruction is in the ROB 1079046SAli.Saidi@ARM.com LsqEntry, /// Instruction is in the LSQ 1089046SAli.Saidi@ARM.com Completed, /// Instruction has completed 1099046SAli.Saidi@ARM.com ResultReady, /// Instruction has its result 1109046SAli.Saidi@ARM.com CanIssue, /// Instruction can issue and execute 1119046SAli.Saidi@ARM.com Issued, /// Instruction has issued 1129046SAli.Saidi@ARM.com Executed, /// Instruction has executed 1139046SAli.Saidi@ARM.com CanCommit, /// Instruction can commit 1149046SAli.Saidi@ARM.com AtCommit, /// Instruction has reached commit 1159046SAli.Saidi@ARM.com Committed, /// Instruction has committed 1169046SAli.Saidi@ARM.com Squashed, /// Instruction is squashed 1179046SAli.Saidi@ARM.com SquashedInIQ, /// Instruction is squashed in the IQ 1189046SAli.Saidi@ARM.com SquashedInLSQ, /// Instruction is squashed in the LSQ 1199046SAli.Saidi@ARM.com SquashedInROB, /// Instruction is squashed in the ROB 1209046SAli.Saidi@ARM.com RecoverInst, /// Is a recover instruction 1219046SAli.Saidi@ARM.com BlockingInst, /// Is a blocking instruction 1229046SAli.Saidi@ARM.com ThreadsyncWait, /// Is a thread synchronization instruction 1239046SAli.Saidi@ARM.com SerializeBefore, /// Needs to serialize on 1249046SAli.Saidi@ARM.com /// instructions ahead of it 1259046SAli.Saidi@ARM.com SerializeAfter, /// Needs to serialize instructions behind it 1269046SAli.Saidi@ARM.com SerializeHandled, /// Serialization has been handled 1279046SAli.Saidi@ARM.com NumStatus 1289046SAli.Saidi@ARM.com }; 1299046SAli.Saidi@ARM.com 1309046SAli.Saidi@ARM.com enum Flags { 13112421Sgabeblack@google.com NotAnInst, 1329046SAli.Saidi@ARM.com TranslationStarted, 1339046SAli.Saidi@ARM.com TranslationCompleted, 1349046SAli.Saidi@ARM.com PossibleLoadViolation, 1359046SAli.Saidi@ARM.com HitExternalSnoop, 1369046SAli.Saidi@ARM.com EffAddrValid, 1379046SAli.Saidi@ARM.com RecordResult, 1389046SAli.Saidi@ARM.com Predicate, 1399046SAli.Saidi@ARM.com PredTaken, 14010824SAndreas.Sandberg@ARM.com IsStrictlyOrdered, 1419046SAli.Saidi@ARM.com ReqMade, 1429046SAli.Saidi@ARM.com MemOpDone, 1439046SAli.Saidi@ARM.com MaxFlags 1449046SAli.Saidi@ARM.com }; 1459046SAli.Saidi@ARM.com 1469046SAli.Saidi@ARM.com public: 1479046SAli.Saidi@ARM.com /** The sequence number of the instruction. */ 1489046SAli.Saidi@ARM.com InstSeqNum seqNum; 1499046SAli.Saidi@ARM.com 1502292SN/A /** The StaticInst used by this BaseDynInst. */ 15110417Sandreas.hansson@arm.com const StaticInstPtr staticInst; 1529046SAli.Saidi@ARM.com 1539046SAli.Saidi@ARM.com /** Pointer to the Impl's CPU object. */ 1549046SAli.Saidi@ARM.com ImplCPU *cpu; 1559046SAli.Saidi@ARM.com 15610030SAli.Saidi@ARM.com BaseCPU *getCpuPtr() { return cpu; } 15710030SAli.Saidi@ARM.com 1589046SAli.Saidi@ARM.com /** Pointer to the thread state. */ 1599046SAli.Saidi@ARM.com ImplState *thread; 1609046SAli.Saidi@ARM.com 1619046SAli.Saidi@ARM.com /** The kind of fault this instruction has generated. */ 1629046SAli.Saidi@ARM.com Fault fault; 1639046SAli.Saidi@ARM.com 1649046SAli.Saidi@ARM.com /** InstRecord that tracks this instructions. */ 1659046SAli.Saidi@ARM.com Trace::InstRecord *traceData; 1669046SAli.Saidi@ARM.com 1679046SAli.Saidi@ARM.com protected: 1689046SAli.Saidi@ARM.com /** The result of the instruction; assumes an instruction can have many 1699046SAli.Saidi@ARM.com * destination registers. 1709046SAli.Saidi@ARM.com */ 17112107SRekai.GonzalezAlberquilla@arm.com std::queue<InstResult> instResult; 1729046SAli.Saidi@ARM.com 1739046SAli.Saidi@ARM.com /** PC state for this instruction. */ 1749046SAli.Saidi@ARM.com TheISA::PCState pc; 1759046SAli.Saidi@ARM.com 1769046SAli.Saidi@ARM.com /* An amalgamation of a lot of boolean values into one */ 1779046SAli.Saidi@ARM.com std::bitset<MaxFlags> instFlags; 1789046SAli.Saidi@ARM.com 1799046SAli.Saidi@ARM.com /** The status of this BaseDynInst. Several bits can be set. */ 1809046SAli.Saidi@ARM.com std::bitset<NumStatus> status; 1819046SAli.Saidi@ARM.com 1829046SAli.Saidi@ARM.com /** Whether or not the source register is ready. 1839046SAli.Saidi@ARM.com * @todo: Not sure this should be here vs the derived class. 1849046SAli.Saidi@ARM.com */ 1859046SAli.Saidi@ARM.com std::bitset<MaxInstSrcRegs> _readySrcRegIdx; 1869046SAli.Saidi@ARM.com 1879046SAli.Saidi@ARM.com public: 1889046SAli.Saidi@ARM.com /** The thread this instruction is from. */ 1899046SAli.Saidi@ARM.com ThreadID threadNumber; 1909046SAli.Saidi@ARM.com 1919046SAli.Saidi@ARM.com /** Iterator pointing to this BaseDynInst in the list of all insts. */ 1929046SAli.Saidi@ARM.com ListIt instListIt; 1939046SAli.Saidi@ARM.com 1949046SAli.Saidi@ARM.com ////////////////////// Branch Data /////////////// 1959046SAli.Saidi@ARM.com /** Predicted PC state after this instruction. */ 1969046SAli.Saidi@ARM.com TheISA::PCState predPC; 1979046SAli.Saidi@ARM.com 1989046SAli.Saidi@ARM.com /** The Macroop if one exists */ 19910417Sandreas.hansson@arm.com const StaticInstPtr macroop; 2001060SN/A 2019046SAli.Saidi@ARM.com /** How many source registers are ready. */ 2029046SAli.Saidi@ARM.com uint8_t readyRegs; 2039046SAli.Saidi@ARM.com 2049046SAli.Saidi@ARM.com public: 2059046SAli.Saidi@ARM.com /////////////////////// Load Store Data ////////////////////// 2069046SAli.Saidi@ARM.com /** The effective virtual address (lds & stores only). */ 2079046SAli.Saidi@ARM.com Addr effAddr; 2089046SAli.Saidi@ARM.com 2099046SAli.Saidi@ARM.com /** The effective physical address. */ 21013590Srekai.gonzalezalberquilla@arm.com Addr physEffAddr; 2119046SAli.Saidi@ARM.com 2129046SAli.Saidi@ARM.com /** The memory request flags (from translation). */ 2139046SAli.Saidi@ARM.com unsigned memReqFlags; 2149046SAli.Saidi@ARM.com 2159046SAli.Saidi@ARM.com /** data address space ID, for loads & stores. */ 2169046SAli.Saidi@ARM.com short asid; 2179046SAli.Saidi@ARM.com 2189046SAli.Saidi@ARM.com /** The size of the request */ 2199046SAli.Saidi@ARM.com uint8_t effSize; 2209046SAli.Saidi@ARM.com 2219046SAli.Saidi@ARM.com /** Pointer to the data for the memory access. */ 2229046SAli.Saidi@ARM.com uint8_t *memData; 2239046SAli.Saidi@ARM.com 2249046SAli.Saidi@ARM.com /** Load queue index. */ 2259046SAli.Saidi@ARM.com int16_t lqIdx; 22613590Srekai.gonzalezalberquilla@arm.com LQIterator lqIt; 2279046SAli.Saidi@ARM.com 2289046SAli.Saidi@ARM.com /** Store queue index. */ 2299046SAli.Saidi@ARM.com int16_t sqIdx; 23013590Srekai.gonzalezalberquilla@arm.com SQIterator sqIt; 2319046SAli.Saidi@ARM.com 2329046SAli.Saidi@ARM.com 2339046SAli.Saidi@ARM.com /////////////////////// TLB Miss ////////////////////// 2349046SAli.Saidi@ARM.com /** 23513590Srekai.gonzalezalberquilla@arm.com * Saved memory request (needed when the DTB address translation is 2369046SAli.Saidi@ARM.com * delayed due to a hw page table walk). 2379046SAli.Saidi@ARM.com */ 23813590Srekai.gonzalezalberquilla@arm.com LSQRequestPtr savedReq; 2399046SAli.Saidi@ARM.com 2409046SAli.Saidi@ARM.com /////////////////////// Checker ////////////////////// 2419046SAli.Saidi@ARM.com // Need a copy of main request pointer to verify on writes. 2429046SAli.Saidi@ARM.com RequestPtr reqToVerify; 2439046SAli.Saidi@ARM.com 2449046SAli.Saidi@ARM.com protected: 2459046SAli.Saidi@ARM.com /** Flattened register index of the destination registers of this 2469046SAli.Saidi@ARM.com * instruction. 2479046SAli.Saidi@ARM.com */ 24812104Snathanael.premillieu@arm.com std::array<RegId, TheISA::MaxInstDestRegs> _flatDestRegIdx; 2499046SAli.Saidi@ARM.com 2509046SAli.Saidi@ARM.com /** Physical register index of the destination registers of this 2519046SAli.Saidi@ARM.com * instruction. 2529046SAli.Saidi@ARM.com */ 25312105Snathanael.premillieu@arm.com std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _destRegIdx; 2549046SAli.Saidi@ARM.com 2559046SAli.Saidi@ARM.com /** Physical register index of the source registers of this 2569046SAli.Saidi@ARM.com * instruction. 2579046SAli.Saidi@ARM.com */ 25812105Snathanael.premillieu@arm.com std::array<PhysRegIdPtr, TheISA::MaxInstSrcRegs> _srcRegIdx; 2599046SAli.Saidi@ARM.com 2609046SAli.Saidi@ARM.com /** Physical register index of the previous producers of the 2619046SAli.Saidi@ARM.com * architected destinations. 2629046SAli.Saidi@ARM.com */ 26312105Snathanael.premillieu@arm.com std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _prevDestRegIdx; 2649046SAli.Saidi@ARM.com 2659046SAli.Saidi@ARM.com 2669046SAli.Saidi@ARM.com public: 2679046SAli.Saidi@ARM.com /** Records changes to result? */ 2689046SAli.Saidi@ARM.com void recordResult(bool f) { instFlags[RecordResult] = f; } 2699046SAli.Saidi@ARM.com 2709046SAli.Saidi@ARM.com /** Is the effective virtual address valid. */ 2719046SAli.Saidi@ARM.com bool effAddrValid() const { return instFlags[EffAddrValid]; } 27213590Srekai.gonzalezalberquilla@arm.com void effAddrValid(bool b) { instFlags[EffAddrValid] = b; } 2739046SAli.Saidi@ARM.com 2749046SAli.Saidi@ARM.com /** Whether or not the memory operation is done. */ 2759046SAli.Saidi@ARM.com bool memOpDone() const { return instFlags[MemOpDone]; } 2769046SAli.Saidi@ARM.com void memOpDone(bool f) { instFlags[MemOpDone] = f; } 2779046SAli.Saidi@ARM.com 27812421Sgabeblack@google.com bool notAnInst() const { return instFlags[NotAnInst]; } 27912421Sgabeblack@google.com void setNotAnInst() { instFlags[NotAnInst] = true; } 28012421Sgabeblack@google.com 2819046SAli.Saidi@ARM.com 2821060SN/A //////////////////////////////////////////// 2831060SN/A // 2841060SN/A // INSTRUCTION EXECUTION 2851060SN/A // 2861060SN/A //////////////////////////////////////////// 2871060SN/A 2885358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 2895358Sgblack@eecs.umich.edu { 2905358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 2915358Sgblack@eecs.umich.edu } 2925358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 2935358Sgblack@eecs.umich.edu { 2945358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 2955358Sgblack@eecs.umich.edu } 2965358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 2975358Sgblack@eecs.umich.edu { 2985358Sgblack@eecs.umich.edu cpu->demapPage(vaddr, asn); 2995358Sgblack@eecs.umich.edu } 3005358Sgblack@eecs.umich.edu 30111608Snikos.nikoleris@arm.com Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags); 3027520Sgblack@eecs.umich.edu 30311608Snikos.nikoleris@arm.com Fault writeMem(uint8_t *data, unsigned size, Addr addr, 30411608Snikos.nikoleris@arm.com Request::Flags flags, uint64_t *res); 3057520Sgblack@eecs.umich.edu 3067944SGiacomo.Gabrielli@arm.com /** True if the DTB address translation has started. */ 3079046SAli.Saidi@ARM.com bool translationStarted() const { return instFlags[TranslationStarted]; } 3089046SAli.Saidi@ARM.com void translationStarted(bool f) { instFlags[TranslationStarted] = f; } 3097944SGiacomo.Gabrielli@arm.com 3107944SGiacomo.Gabrielli@arm.com /** True if the DTB address translation has completed. */ 3119046SAli.Saidi@ARM.com bool translationCompleted() const { return instFlags[TranslationCompleted]; } 3129046SAli.Saidi@ARM.com void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; } 3137944SGiacomo.Gabrielli@arm.com 3148545Ssaidi@eecs.umich.edu /** True if this address was found to match a previous load and they issued 3158545Ssaidi@eecs.umich.edu * out of order. If that happend, then it's only a problem if an incoming 3168545Ssaidi@eecs.umich.edu * snoop invalidate modifies the line, in which case we need to squash. 3178545Ssaidi@eecs.umich.edu * If nothing modified the line the order doesn't matter. 3188545Ssaidi@eecs.umich.edu */ 3199046SAli.Saidi@ARM.com bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; } 3209046SAli.Saidi@ARM.com void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; } 3218545Ssaidi@eecs.umich.edu 3228545Ssaidi@eecs.umich.edu /** True if the address hit a external snoop while sitting in the LSQ. 3238545Ssaidi@eecs.umich.edu * If this is true and a older instruction sees it, this instruction must 3248545Ssaidi@eecs.umich.edu * reexecute 3258545Ssaidi@eecs.umich.edu */ 3269046SAli.Saidi@ARM.com bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; } 3279046SAli.Saidi@ARM.com void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; } 3288545Ssaidi@eecs.umich.edu 3297944SGiacomo.Gabrielli@arm.com /** 3307944SGiacomo.Gabrielli@arm.com * Returns true if the DTB address translation is being delayed due to a hw 3317944SGiacomo.Gabrielli@arm.com * page table walk. 3327944SGiacomo.Gabrielli@arm.com */ 3337944SGiacomo.Gabrielli@arm.com bool isTranslationDelayed() const 3347944SGiacomo.Gabrielli@arm.com { 3359046SAli.Saidi@ARM.com return (translationStarted() && !translationCompleted()); 3367944SGiacomo.Gabrielli@arm.com } 3377944SGiacomo.Gabrielli@arm.com 3381060SN/A public: 3392292SN/A#ifdef DEBUG 3402292SN/A void dumpSNList(); 3412292SN/A#endif 3422292SN/A 3433770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th destination 3443770Sgblack@eecs.umich.edu * register. 3453770Sgblack@eecs.umich.edu */ 34612105Snathanael.premillieu@arm.com PhysRegIdPtr renamedDestRegIdx(int idx) const 3473770Sgblack@eecs.umich.edu { 3483770Sgblack@eecs.umich.edu return _destRegIdx[idx]; 3493770Sgblack@eecs.umich.edu } 3503770Sgblack@eecs.umich.edu 3513770Sgblack@eecs.umich.edu /** Returns the physical register index of the i'th source register. */ 35212105Snathanael.premillieu@arm.com PhysRegIdPtr renamedSrcRegIdx(int idx) const 3533770Sgblack@eecs.umich.edu { 3549046SAli.Saidi@ARM.com assert(TheISA::MaxInstSrcRegs > idx); 3553770Sgblack@eecs.umich.edu return _srcRegIdx[idx]; 3563770Sgblack@eecs.umich.edu } 3573770Sgblack@eecs.umich.edu 3583770Sgblack@eecs.umich.edu /** Returns the flattened register index of the i'th destination 3593770Sgblack@eecs.umich.edu * register. 3603770Sgblack@eecs.umich.edu */ 36112106SRekai.GonzalezAlberquilla@arm.com const RegId& flattenedDestRegIdx(int idx) const 3623770Sgblack@eecs.umich.edu { 3633770Sgblack@eecs.umich.edu return _flatDestRegIdx[idx]; 3643770Sgblack@eecs.umich.edu } 3653770Sgblack@eecs.umich.edu 3663770Sgblack@eecs.umich.edu /** Returns the physical register index of the previous physical register 3673770Sgblack@eecs.umich.edu * that remapped to the same logical register index. 3683770Sgblack@eecs.umich.edu */ 36912105Snathanael.premillieu@arm.com PhysRegIdPtr prevDestRegIdx(int idx) const 3703770Sgblack@eecs.umich.edu { 3713770Sgblack@eecs.umich.edu return _prevDestRegIdx[idx]; 3723770Sgblack@eecs.umich.edu } 3733770Sgblack@eecs.umich.edu 3743770Sgblack@eecs.umich.edu /** Renames a destination register to a physical register. Also records 3753770Sgblack@eecs.umich.edu * the previous physical register that the logical register mapped to. 3763770Sgblack@eecs.umich.edu */ 3773770Sgblack@eecs.umich.edu void renameDestReg(int idx, 37812105Snathanael.premillieu@arm.com PhysRegIdPtr renamed_dest, 37912105Snathanael.premillieu@arm.com PhysRegIdPtr previous_rename) 3803770Sgblack@eecs.umich.edu { 3813770Sgblack@eecs.umich.edu _destRegIdx[idx] = renamed_dest; 3823770Sgblack@eecs.umich.edu _prevDestRegIdx[idx] = previous_rename; 3833770Sgblack@eecs.umich.edu } 3843770Sgblack@eecs.umich.edu 3853770Sgblack@eecs.umich.edu /** Renames a source logical register to the physical register which 3863770Sgblack@eecs.umich.edu * has/will produce that logical register's result. 3873770Sgblack@eecs.umich.edu * @todo: add in whether or not the source register is ready. 3883770Sgblack@eecs.umich.edu */ 38912105Snathanael.premillieu@arm.com void renameSrcReg(int idx, PhysRegIdPtr renamed_src) 3903770Sgblack@eecs.umich.edu { 3913770Sgblack@eecs.umich.edu _srcRegIdx[idx] = renamed_src; 3923770Sgblack@eecs.umich.edu } 3933770Sgblack@eecs.umich.edu 3943770Sgblack@eecs.umich.edu /** Flattens a destination architectural register index into a logical 3953770Sgblack@eecs.umich.edu * index. 3963770Sgblack@eecs.umich.edu */ 39712106SRekai.GonzalezAlberquilla@arm.com void flattenDestReg(int idx, const RegId& flattened_dest) 3983770Sgblack@eecs.umich.edu { 3993770Sgblack@eecs.umich.edu _flatDestRegIdx[idx] = flattened_dest; 4003770Sgblack@eecs.umich.edu } 4014636Sgblack@eecs.umich.edu /** BaseDynInst constructor given a binary instruction. 4024636Sgblack@eecs.umich.edu * @param staticInst A StaticInstPtr to the underlying instruction. 4037720Sgblack@eecs.umich.edu * @param pc The PC state for the instruction. 4047720Sgblack@eecs.umich.edu * @param predPC The predicted next PC state for the instruction. 4054636Sgblack@eecs.umich.edu * @param seq_num The sequence number of the instruction. 4064636Sgblack@eecs.umich.edu * @param cpu Pointer to the instruction's CPU. 4074636Sgblack@eecs.umich.edu */ 40810417Sandreas.hansson@arm.com BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop, 4098502Sgblack@eecs.umich.edu TheISA::PCState pc, TheISA::PCState predPC, 4108502Sgblack@eecs.umich.edu InstSeqNum seq_num, ImplCPU *cpu); 4113770Sgblack@eecs.umich.edu 4122292SN/A /** BaseDynInst constructor given a StaticInst pointer. 4132292SN/A * @param _staticInst The StaticInst for this BaseDynInst. 4142292SN/A */ 41510417Sandreas.hansson@arm.com BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop); 4161060SN/A 4171060SN/A /** BaseDynInst destructor. */ 4181060SN/A ~BaseDynInst(); 4191060SN/A 4201464SN/A private: 4211684SN/A /** Function to initialize variables in the constructors. */ 4221464SN/A void initVars(); 4231060SN/A 4241464SN/A public: 4251060SN/A /** Dumps out contents of this BaseDynInst. */ 4261060SN/A void dump(); 4271060SN/A 4281060SN/A /** Dumps out contents of this BaseDynInst into given string. */ 4291060SN/A void dump(std::string &outstring); 4301060SN/A 4313326Sktlim@umich.edu /** Read this CPU's ID. */ 43210110Sandreas.hansson@arm.com int cpuId() const { return cpu->cpuId(); } 4333326Sktlim@umich.edu 43410190Sakash.bagdia@arm.com /** Read this CPU's Socket ID. */ 43510190Sakash.bagdia@arm.com uint32_t socketId() const { return cpu->socketId(); } 43610190Sakash.bagdia@arm.com 4378832SAli.Saidi@ARM.com /** Read this CPU's data requestor ID */ 43810110Sandreas.hansson@arm.com MasterID masterId() const { return cpu->dataMasterId(); } 4398832SAli.Saidi@ARM.com 4405714Shsul@eecs.umich.edu /** Read this context's system-wide ID **/ 44111005Sandreas.sandberg@arm.com ContextID contextId() const { return thread->contextId(); } 4425714Shsul@eecs.umich.edu 4431060SN/A /** Returns the fault type. */ 44410110Sandreas.hansson@arm.com Fault getFault() const { return fault; } 44513590Srekai.gonzalezalberquilla@arm.com /** TODO: This I added for the LSQRequest side to be able to modify the 44613590Srekai.gonzalezalberquilla@arm.com * fault. There should be a better mechanism in place. */ 44713590Srekai.gonzalezalberquilla@arm.com Fault& getFault() { return fault; } 4481060SN/A 4491060SN/A /** Checks whether or not this instruction has had its branch target 4501060SN/A * calculated yet. For now it is not utilized and is hacked to be 4511060SN/A * always false. 4522292SN/A * @todo: Actually use this instruction. 4531060SN/A */ 4541060SN/A bool doneTargCalc() { return false; } 4551060SN/A 4567720Sgblack@eecs.umich.edu /** Set the predicted target of this current instruction. */ 4577720Sgblack@eecs.umich.edu void setPredTarg(const TheISA::PCState &_predPC) 4583965Sgblack@eecs.umich.edu { 4597720Sgblack@eecs.umich.edu predPC = _predPC; 4603965Sgblack@eecs.umich.edu } 4612935Sksewell@umich.edu 4627720Sgblack@eecs.umich.edu const TheISA::PCState &readPredTarg() { return predPC; } 4631060SN/A 4643794Sgblack@eecs.umich.edu /** Returns the predicted PC immediately after the branch. */ 4657720Sgblack@eecs.umich.edu Addr predInstAddr() { return predPC.instAddr(); } 4663794Sgblack@eecs.umich.edu 4673794Sgblack@eecs.umich.edu /** Returns the predicted PC two instructions after the branch */ 4687720Sgblack@eecs.umich.edu Addr predNextInstAddr() { return predPC.nextInstAddr(); } 4691060SN/A 4704636Sgblack@eecs.umich.edu /** Returns the predicted micro PC after the branch */ 4717720Sgblack@eecs.umich.edu Addr predMicroPC() { return predPC.microPC(); } 4724636Sgblack@eecs.umich.edu 4731060SN/A /** Returns whether the instruction was predicted taken or not. */ 4743794Sgblack@eecs.umich.edu bool readPredTaken() 4753794Sgblack@eecs.umich.edu { 4769046SAli.Saidi@ARM.com return instFlags[PredTaken]; 4773794Sgblack@eecs.umich.edu } 4783794Sgblack@eecs.umich.edu 4793794Sgblack@eecs.umich.edu void setPredTaken(bool predicted_taken) 4803794Sgblack@eecs.umich.edu { 4819046SAli.Saidi@ARM.com instFlags[PredTaken] = predicted_taken; 4823794Sgblack@eecs.umich.edu } 4831060SN/A 4841060SN/A /** Returns whether the instruction mispredicted. */ 4852935Sksewell@umich.edu bool mispredicted() 4863794Sgblack@eecs.umich.edu { 4877720Sgblack@eecs.umich.edu TheISA::PCState tempPC = pc; 4887720Sgblack@eecs.umich.edu TheISA::advancePC(tempPC, staticInst); 4897720Sgblack@eecs.umich.edu return !(tempPC == predPC); 4903794Sgblack@eecs.umich.edu } 4913794Sgblack@eecs.umich.edu 4921060SN/A // 4931060SN/A // Instruction types. Forward checks to StaticInst object. 4941060SN/A // 4955543Ssaidi@eecs.umich.edu bool isNop() const { return staticInst->isNop(); } 4965543Ssaidi@eecs.umich.edu bool isMemRef() const { return staticInst->isMemRef(); } 4975543Ssaidi@eecs.umich.edu bool isLoad() const { return staticInst->isLoad(); } 4985543Ssaidi@eecs.umich.edu bool isStore() const { return staticInst->isStore(); } 49912768Sqtt2@cornell.edu bool isAtomic() const { return staticInst->isAtomic(); } 5002336SN/A bool isStoreConditional() const 5012336SN/A { return staticInst->isStoreConditional(); } 5021060SN/A bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 5031060SN/A bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 5045543Ssaidi@eecs.umich.edu bool isInteger() const { return staticInst->isInteger(); } 5055543Ssaidi@eecs.umich.edu bool isFloating() const { return staticInst->isFloating(); } 50612110SRekai.GonzalezAlberquilla@arm.com bool isVector() const { return staticInst->isVector(); } 5075543Ssaidi@eecs.umich.edu bool isControl() const { return staticInst->isControl(); } 5085543Ssaidi@eecs.umich.edu bool isCall() const { return staticInst->isCall(); } 5095543Ssaidi@eecs.umich.edu bool isReturn() const { return staticInst->isReturn(); } 5105543Ssaidi@eecs.umich.edu bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 5111060SN/A bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 5125543Ssaidi@eecs.umich.edu bool isCondCtrl() const { return staticInst->isCondCtrl(); } 5135543Ssaidi@eecs.umich.edu bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 5142935Sksewell@umich.edu bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 5151060SN/A bool isThreadSync() const { return staticInst->isThreadSync(); } 5161060SN/A bool isSerializing() const { return staticInst->isSerializing(); } 5172292SN/A bool isSerializeBefore() const 5182731Sktlim@umich.edu { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 5192292SN/A bool isSerializeAfter() const 5202731Sktlim@umich.edu { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 5217784SAli.Saidi@ARM.com bool isSquashAfter() const { return staticInst->isSquashAfter(); } 5221060SN/A bool isMemBarrier() const { return staticInst->isMemBarrier(); } 5231060SN/A bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 5241060SN/A bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 5252292SN/A bool isQuiesce() const { return staticInst->isQuiesce(); } 5262336SN/A bool isIprAccess() const { return staticInst->isIprAccess(); } 5272308SN/A bool isUnverifiable() const { return staticInst->isUnverifiable(); } 5284828Sgblack@eecs.umich.edu bool isSyscall() const { return staticInst->isSyscall(); } 5294654Sgblack@eecs.umich.edu bool isMacroop() const { return staticInst->isMacroop(); } 5304654Sgblack@eecs.umich.edu bool isMicroop() const { return staticInst->isMicroop(); } 5314636Sgblack@eecs.umich.edu bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 5324654Sgblack@eecs.umich.edu bool isLastMicroop() const { return staticInst->isLastMicroop(); } 5334654Sgblack@eecs.umich.edu bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 5344636Sgblack@eecs.umich.edu bool isMicroBranch() const { return staticInst->isMicroBranch(); } 5352292SN/A 5362292SN/A /** Temporarily sets this instruction as a serialize before instruction. */ 5372731Sktlim@umich.edu void setSerializeBefore() { status.set(SerializeBefore); } 5382292SN/A 5392292SN/A /** Clears the serializeBefore part of this instruction. */ 5402731Sktlim@umich.edu void clearSerializeBefore() { status.reset(SerializeBefore); } 5412292SN/A 5422292SN/A /** Checks if this serializeBefore is only temporarily set. */ 5432731Sktlim@umich.edu bool isTempSerializeBefore() { return status[SerializeBefore]; } 5442292SN/A 5452292SN/A /** Temporarily sets this instruction as a serialize after instruction. */ 5462731Sktlim@umich.edu void setSerializeAfter() { status.set(SerializeAfter); } 5472292SN/A 5482292SN/A /** Clears the serializeAfter part of this instruction.*/ 5492731Sktlim@umich.edu void clearSerializeAfter() { status.reset(SerializeAfter); } 5502292SN/A 5512292SN/A /** Checks if this serializeAfter is only temporarily set. */ 5522731Sktlim@umich.edu bool isTempSerializeAfter() { return status[SerializeAfter]; } 5532292SN/A 5542731Sktlim@umich.edu /** Sets the serialization part of this instruction as handled. */ 5552731Sktlim@umich.edu void setSerializeHandled() { status.set(SerializeHandled); } 5562292SN/A 5572292SN/A /** Checks if the serialization part of this instruction has been 5582292SN/A * handled. This does not apply to the temporary serializing 5592292SN/A * state; it only applies to this instruction's own permanent 5602292SN/A * serializing state. 5612292SN/A */ 5622731Sktlim@umich.edu bool isSerializeHandled() { return status[SerializeHandled]; } 5631060SN/A 5641464SN/A /** Returns the opclass of this instruction. */ 5651464SN/A OpClass opClass() const { return staticInst->opClass(); } 5661464SN/A 5671464SN/A /** Returns the branch target address. */ 5687720Sgblack@eecs.umich.edu TheISA::PCState branchTarget() const 5697720Sgblack@eecs.umich.edu { return staticInst->branchTarget(pc); } 5701464SN/A 5712292SN/A /** Returns the number of source registers. */ 5725543Ssaidi@eecs.umich.edu int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 5731684SN/A 5742292SN/A /** Returns the number of destination registers. */ 5751060SN/A int8_t numDestRegs() const { return staticInst->numDestRegs(); } 5761060SN/A 5771060SN/A // the following are used to track physical register usage 5781060SN/A // for machines with separate int & FP reg files 5791060SN/A int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 5801060SN/A int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 58110715SRekai.GonzalezAlberquilla@arm.com int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); } 58212109SRekai.GonzalezAlberquilla@arm.com int8_t numVecDestRegs() const { return staticInst->numVecDestRegs(); } 58313590Srekai.gonzalezalberquilla@arm.com int8_t numVecElemDestRegs() const 58413590Srekai.gonzalezalberquilla@arm.com { 58512109SRekai.GonzalezAlberquilla@arm.com return staticInst->numVecElemDestRegs(); 58612109SRekai.GonzalezAlberquilla@arm.com } 5871060SN/A 5881060SN/A /** Returns the logical register index of the i'th destination register. */ 58912106SRekai.GonzalezAlberquilla@arm.com const RegId& destRegIdx(int i) const { return staticInst->destRegIdx(i); } 5901060SN/A 5911060SN/A /** Returns the logical register index of the i'th source register. */ 59212106SRekai.GonzalezAlberquilla@arm.com const RegId& srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 5931060SN/A 59412107SRekai.GonzalezAlberquilla@arm.com /** Return the size of the instResult queue. */ 59512107SRekai.GonzalezAlberquilla@arm.com uint8_t resultSize() { return instResult.size(); } 59612107SRekai.GonzalezAlberquilla@arm.com 59712107SRekai.GonzalezAlberquilla@arm.com /** Pops a result off the instResult queue. 59812107SRekai.GonzalezAlberquilla@arm.com * If the result stack is empty, return the default value. 59912107SRekai.GonzalezAlberquilla@arm.com * */ 60012107SRekai.GonzalezAlberquilla@arm.com InstResult popResult(InstResult dflt = InstResult()) 6018733Sgeoffrey.blake@arm.com { 6028733Sgeoffrey.blake@arm.com if (!instResult.empty()) { 60312107SRekai.GonzalezAlberquilla@arm.com InstResult t = instResult.front(); 6048733Sgeoffrey.blake@arm.com instResult.pop(); 60512107SRekai.GonzalezAlberquilla@arm.com return t; 6068733Sgeoffrey.blake@arm.com } 60712107SRekai.GonzalezAlberquilla@arm.com return dflt; 6088733Sgeoffrey.blake@arm.com } 6091684SN/A 61012107SRekai.GonzalezAlberquilla@arm.com /** Pushes a result onto the instResult queue. */ 61112109SRekai.GonzalezAlberquilla@arm.com /** @{ */ 61212109SRekai.GonzalezAlberquilla@arm.com /** Scalar result. */ 61312107SRekai.GonzalezAlberquilla@arm.com template<typename T> 61412107SRekai.GonzalezAlberquilla@arm.com void setScalarResult(T&& t) 6158733Sgeoffrey.blake@arm.com { 6169046SAli.Saidi@ARM.com if (instFlags[RecordResult]) { 61712107SRekai.GonzalezAlberquilla@arm.com instResult.push(InstResult(std::forward<T>(t), 61812107SRekai.GonzalezAlberquilla@arm.com InstResult::ResultType::Scalar)); 6198733Sgeoffrey.blake@arm.com } 6208733Sgeoffrey.blake@arm.com } 6211060SN/A 62212109SRekai.GonzalezAlberquilla@arm.com /** Full vector result. */ 62312109SRekai.GonzalezAlberquilla@arm.com template<typename T> 62412109SRekai.GonzalezAlberquilla@arm.com void setVecResult(T&& t) 62512109SRekai.GonzalezAlberquilla@arm.com { 62612109SRekai.GonzalezAlberquilla@arm.com if (instFlags[RecordResult]) { 62712109SRekai.GonzalezAlberquilla@arm.com instResult.push(InstResult(std::forward<T>(t), 62812109SRekai.GonzalezAlberquilla@arm.com InstResult::ResultType::VecReg)); 62912109SRekai.GonzalezAlberquilla@arm.com } 63012109SRekai.GonzalezAlberquilla@arm.com } 63112109SRekai.GonzalezAlberquilla@arm.com 63212109SRekai.GonzalezAlberquilla@arm.com /** Vector element result. */ 63312109SRekai.GonzalezAlberquilla@arm.com template<typename T> 63412109SRekai.GonzalezAlberquilla@arm.com void setVecElemResult(T&& t) 63512109SRekai.GonzalezAlberquilla@arm.com { 63612109SRekai.GonzalezAlberquilla@arm.com if (instFlags[RecordResult]) { 63712109SRekai.GonzalezAlberquilla@arm.com instResult.push(InstResult(std::forward<T>(t), 63812109SRekai.GonzalezAlberquilla@arm.com InstResult::ResultType::VecElem)); 63912109SRekai.GonzalezAlberquilla@arm.com } 64012109SRekai.GonzalezAlberquilla@arm.com } 64112109SRekai.GonzalezAlberquilla@arm.com /** @} */ 64212109SRekai.GonzalezAlberquilla@arm.com 6432702Sktlim@umich.edu /** Records an integer register being set to a value. */ 64413557Sgabeblack@google.com void setIntRegOperand(const StaticInst *si, int idx, RegVal val) 6451060SN/A { 64612107SRekai.GonzalezAlberquilla@arm.com setScalarResult(val); 6471060SN/A } 6481060SN/A 6499920Syasuko.eckert@amd.com /** Records a CC register being set to a value. */ 65010319SAndreas.Sandberg@ARM.com void setCCRegOperand(const StaticInst *si, int idx, CCReg val) 6519920Syasuko.eckert@amd.com { 65212107SRekai.GonzalezAlberquilla@arm.com setScalarResult(val); 6539920Syasuko.eckert@amd.com } 6549920Syasuko.eckert@amd.com 65512109SRekai.GonzalezAlberquilla@arm.com /** Record a vector register being set to a value */ 65612109SRekai.GonzalezAlberquilla@arm.com void setVecRegOperand(const StaticInst *si, int idx, 65712109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& val) 65812109SRekai.GonzalezAlberquilla@arm.com { 65912109SRekai.GonzalezAlberquilla@arm.com setVecResult(val); 66012109SRekai.GonzalezAlberquilla@arm.com } 66112109SRekai.GonzalezAlberquilla@arm.com 6622702Sktlim@umich.edu /** Records an fp register being set to an integer value. */ 66312107SRekai.GonzalezAlberquilla@arm.com void 66413557Sgabeblack@google.com setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) 6652308SN/A { 66612107SRekai.GonzalezAlberquilla@arm.com setScalarResult(val); 6671060SN/A } 6681060SN/A 66912109SRekai.GonzalezAlberquilla@arm.com /** Record a vector register being set to a value */ 67012109SRekai.GonzalezAlberquilla@arm.com void setVecElemOperand(const StaticInst *si, int idx, const VecElem val) 67112109SRekai.GonzalezAlberquilla@arm.com { 67212109SRekai.GonzalezAlberquilla@arm.com setVecElemResult(val); 67312109SRekai.GonzalezAlberquilla@arm.com } 67412109SRekai.GonzalezAlberquilla@arm.com 6752190SN/A /** Records that one of the source registers is ready. */ 6762292SN/A void markSrcRegReady(); 6772190SN/A 6782331SN/A /** Marks a specific register as ready. */ 6792292SN/A void markSrcRegReady(RegIndex src_idx); 6802190SN/A 6811684SN/A /** Returns if a source register is ready. */ 6821464SN/A bool isReadySrcRegIdx(int idx) const 6831464SN/A { 6841464SN/A return this->_readySrcRegIdx[idx]; 6851464SN/A } 6861464SN/A 6871684SN/A /** Sets this instruction as completed. */ 6882731Sktlim@umich.edu void setCompleted() { status.set(Completed); } 6891464SN/A 6902292SN/A /** Returns whether or not this instruction is completed. */ 6912731Sktlim@umich.edu bool isCompleted() const { return status[Completed]; } 6921464SN/A 6932731Sktlim@umich.edu /** Marks the result as ready. */ 6942731Sktlim@umich.edu void setResultReady() { status.set(ResultReady); } 6952308SN/A 6962731Sktlim@umich.edu /** Returns whether or not the result is ready. */ 6972731Sktlim@umich.edu bool isResultReady() const { return status[ResultReady]; } 6982308SN/A 6991060SN/A /** Sets this instruction as ready to issue. */ 7002731Sktlim@umich.edu void setCanIssue() { status.set(CanIssue); } 7011060SN/A 7021060SN/A /** Returns whether or not this instruction is ready to issue. */ 7032731Sktlim@umich.edu bool readyToIssue() const { return status[CanIssue]; } 7041060SN/A 7054032Sktlim@umich.edu /** Clears this instruction being able to issue. */ 7064032Sktlim@umich.edu void clearCanIssue() { status.reset(CanIssue); } 7074032Sktlim@umich.edu 7081060SN/A /** Sets this instruction as issued from the IQ. */ 7092731Sktlim@umich.edu void setIssued() { status.set(Issued); } 7101060SN/A 7111060SN/A /** Returns whether or not this instruction has issued. */ 7122731Sktlim@umich.edu bool isIssued() const { return status[Issued]; } 7131060SN/A 7144032Sktlim@umich.edu /** Clears this instruction as being issued. */ 7154032Sktlim@umich.edu void clearIssued() { status.reset(Issued); } 7164032Sktlim@umich.edu 7171060SN/A /** Sets this instruction as executed. */ 7182731Sktlim@umich.edu void setExecuted() { status.set(Executed); } 7191060SN/A 7201060SN/A /** Returns whether or not this instruction has executed. */ 7212731Sktlim@umich.edu bool isExecuted() const { return status[Executed]; } 7221060SN/A 7231060SN/A /** Sets this instruction as ready to commit. */ 7242731Sktlim@umich.edu void setCanCommit() { status.set(CanCommit); } 7251060SN/A 7261061SN/A /** Clears this instruction as being ready to commit. */ 7272731Sktlim@umich.edu void clearCanCommit() { status.reset(CanCommit); } 7281061SN/A 7291060SN/A /** Returns whether or not this instruction is ready to commit. */ 7302731Sktlim@umich.edu bool readyToCommit() const { return status[CanCommit]; } 7312731Sktlim@umich.edu 7322731Sktlim@umich.edu void setAtCommit() { status.set(AtCommit); } 7332731Sktlim@umich.edu 7342731Sktlim@umich.edu bool isAtCommit() { return status[AtCommit]; } 7351060SN/A 7362292SN/A /** Sets this instruction as committed. */ 7372731Sktlim@umich.edu void setCommitted() { status.set(Committed); } 7382292SN/A 7392292SN/A /** Returns whether or not this instruction is committed. */ 7402731Sktlim@umich.edu bool isCommitted() const { return status[Committed]; } 7412292SN/A 7421060SN/A /** Sets this instruction as squashed. */ 7432731Sktlim@umich.edu void setSquashed() { status.set(Squashed); } 7441060SN/A 7451060SN/A /** Returns whether or not this instruction is squashed. */ 7462731Sktlim@umich.edu bool isSquashed() const { return status[Squashed]; } 7471060SN/A 7482292SN/A //Instruction Queue Entry 7492292SN/A //----------------------- 7502292SN/A /** Sets this instruction as a entry the IQ. */ 7512731Sktlim@umich.edu void setInIQ() { status.set(IqEntry); } 7522292SN/A 7532292SN/A /** Sets this instruction as a entry the IQ. */ 7542731Sktlim@umich.edu void clearInIQ() { status.reset(IqEntry); } 7552731Sktlim@umich.edu 7562731Sktlim@umich.edu /** Returns whether or not this instruction has issued. */ 7572731Sktlim@umich.edu bool isInIQ() const { return status[IqEntry]; } 7582292SN/A 7591060SN/A /** Sets this instruction as squashed in the IQ. */ 7602731Sktlim@umich.edu void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 7611060SN/A 7621060SN/A /** Returns whether or not this instruction is squashed in the IQ. */ 7632731Sktlim@umich.edu bool isSquashedInIQ() const { return status[SquashedInIQ]; } 7642292SN/A 7652292SN/A 7662292SN/A //Load / Store Queue Functions 7672292SN/A //----------------------- 7682292SN/A /** Sets this instruction as a entry the LSQ. */ 7692731Sktlim@umich.edu void setInLSQ() { status.set(LsqEntry); } 7702292SN/A 7712292SN/A /** Sets this instruction as a entry the LSQ. */ 7722731Sktlim@umich.edu void removeInLSQ() { status.reset(LsqEntry); } 7732731Sktlim@umich.edu 7742731Sktlim@umich.edu /** Returns whether or not this instruction is in the LSQ. */ 7752731Sktlim@umich.edu bool isInLSQ() const { return status[LsqEntry]; } 7762292SN/A 7772292SN/A /** Sets this instruction as squashed in the LSQ. */ 7782731Sktlim@umich.edu void setSquashedInLSQ() { status.set(SquashedInLSQ);} 7792292SN/A 7802292SN/A /** Returns whether or not this instruction is squashed in the LSQ. */ 7812731Sktlim@umich.edu bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 7822292SN/A 7832292SN/A 7842292SN/A //Reorder Buffer Functions 7852292SN/A //----------------------- 7862292SN/A /** Sets this instruction as a entry the ROB. */ 7872731Sktlim@umich.edu void setInROB() { status.set(RobEntry); } 7882292SN/A 7892292SN/A /** Sets this instruction as a entry the ROB. */ 7902731Sktlim@umich.edu void clearInROB() { status.reset(RobEntry); } 7912731Sktlim@umich.edu 7922731Sktlim@umich.edu /** Returns whether or not this instruction is in the ROB. */ 7932731Sktlim@umich.edu bool isInROB() const { return status[RobEntry]; } 7942292SN/A 7952292SN/A /** Sets this instruction as squashed in the ROB. */ 7962731Sktlim@umich.edu void setSquashedInROB() { status.set(SquashedInROB); } 7972292SN/A 7982292SN/A /** Returns whether or not this instruction is squashed in the ROB. */ 7992731Sktlim@umich.edu bool isSquashedInROB() const { return status[SquashedInROB]; } 8002292SN/A 8017720Sgblack@eecs.umich.edu /** Read the PC state of this instruction. */ 80210319SAndreas.Sandberg@ARM.com TheISA::PCState pcState() const { return pc; } 8037720Sgblack@eecs.umich.edu 8047720Sgblack@eecs.umich.edu /** Set the PC state of this instruction. */ 80510319SAndreas.Sandberg@ARM.com void pcState(const TheISA::PCState &val) { pc = val; } 8067720Sgblack@eecs.umich.edu 8071060SN/A /** Read the PC of this instruction. */ 80811294Sandreas.hansson@arm.com Addr instAddr() const { return pc.instAddr(); } 8097720Sgblack@eecs.umich.edu 8107720Sgblack@eecs.umich.edu /** Read the PC of the next instruction. */ 81111294Sandreas.hansson@arm.com Addr nextInstAddr() const { return pc.nextInstAddr(); } 8121060SN/A 8134636Sgblack@eecs.umich.edu /**Read the micro PC of this instruction. */ 81411294Sandreas.hansson@arm.com Addr microPC() const { return pc.microPC(); } 8154636Sgblack@eecs.umich.edu 81613429Srekai.gonzalezalberquilla@arm.com bool readPredicate() const 8177597Sminkyu.jeong@arm.com { 8189046SAli.Saidi@ARM.com return instFlags[Predicate]; 8197597Sminkyu.jeong@arm.com } 8207597Sminkyu.jeong@arm.com 8217597Sminkyu.jeong@arm.com void setPredicate(bool val) 8227597Sminkyu.jeong@arm.com { 8239046SAli.Saidi@ARM.com instFlags[Predicate] = val; 8247600Sminkyu.jeong@arm.com 8257600Sminkyu.jeong@arm.com if (traceData) { 8267600Sminkyu.jeong@arm.com traceData->setPredicate(val); 8277600Sminkyu.jeong@arm.com } 8287597Sminkyu.jeong@arm.com } 8297597Sminkyu.jeong@arm.com 8302702Sktlim@umich.edu /** Sets the ASID. */ 8312292SN/A void setASID(short addr_space_id) { asid = addr_space_id; } 83213590Srekai.gonzalezalberquilla@arm.com short getASID() { return asid; } 8332292SN/A 8342702Sktlim@umich.edu /** Sets the thread id. */ 8356221Snate@binkert.org void setTid(ThreadID tid) { threadNumber = tid; } 8362292SN/A 8372731Sktlim@umich.edu /** Sets the pointer to the thread state. */ 8382702Sktlim@umich.edu void setThreadState(ImplState *state) { thread = state; } 8391060SN/A 8402731Sktlim@umich.edu /** Returns the thread context. */ 8412680Sktlim@umich.edu ThreadContext *tcBase() { return thread->getTC(); } 8421464SN/A 8431464SN/A public: 8441684SN/A /** Returns whether or not the eff. addr. source registers are ready. */ 84513429Srekai.gonzalezalberquilla@arm.com bool eaSrcsReady() const; 8461681SN/A 84710824SAndreas.Sandberg@ARM.com /** Is this instruction's memory access strictly ordered? */ 84810824SAndreas.Sandberg@ARM.com bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; } 84913590Srekai.gonzalezalberquilla@arm.com void strictlyOrdered(bool so) { instFlags[IsStrictlyOrdered] = so; } 8504032Sktlim@umich.edu 8514032Sktlim@umich.edu /** Has this instruction generated a memory request. */ 85213429Srekai.gonzalezalberquilla@arm.com bool hasRequest() const { return instFlags[ReqMade]; } 85313590Srekai.gonzalezalberquilla@arm.com /** Assert this instruction has generated a memory request. */ 85413590Srekai.gonzalezalberquilla@arm.com void setRequest() { instFlags[ReqMade] = true; } 8552292SN/A 8562292SN/A /** Returns iterator to this instruction in the list of all insts. */ 8572292SN/A ListIt &getInstListIt() { return instListIt; } 8582292SN/A 8592292SN/A /** Sets iterator for this instruction in the list of all insts. */ 8602292SN/A void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 8613326Sktlim@umich.edu 8623326Sktlim@umich.edu public: 8633326Sktlim@umich.edu /** Returns the number of consecutive store conditional failures. */ 86410319SAndreas.Sandberg@ARM.com unsigned int readStCondFailures() const 8653326Sktlim@umich.edu { return thread->storeCondFailures; } 8663326Sktlim@umich.edu 8673326Sktlim@umich.edu /** Sets the number of consecutive store conditional failures. */ 86810319SAndreas.Sandberg@ARM.com void setStCondFailures(unsigned int sc_failures) 8693326Sktlim@umich.edu { thread->storeCondFailures = sc_failures; } 87010529Smorr@cs.wisc.edu 87110529Smorr@cs.wisc.edu public: 87210529Smorr@cs.wisc.edu // monitor/mwait funtions 87311148Smitch.hayenga@arm.com void armMonitor(Addr address) { cpu->armMonitor(threadNumber, address); } 87411148Smitch.hayenga@arm.com bool mwait(PacketPtr pkt) { return cpu->mwait(threadNumber, pkt); } 87510529Smorr@cs.wisc.edu void mwaitAtomic(ThreadContext *tc) 87611148Smitch.hayenga@arm.com { return cpu->mwaitAtomic(threadNumber, tc, cpu->dtb); } 87711148Smitch.hayenga@arm.com AddressMonitor *getAddrMonitor() 87811148Smitch.hayenga@arm.com { return cpu->getCpuAddrMonitor(threadNumber); } 8791060SN/A}; 8801060SN/A 8811060SN/Atemplate<class Impl> 8827520Sgblack@eecs.umich.eduFault 88311608Snikos.nikoleris@arm.comBaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size, 88411608Snikos.nikoleris@arm.com Request::Flags flags) 8851060SN/A{ 88613590Srekai.gonzalezalberquilla@arm.com return cpu->pushRequest( 88713590Srekai.gonzalezalberquilla@arm.com dynamic_cast<typename DynInstPtr::PtrType>(this), 88813590Srekai.gonzalezalberquilla@arm.com /* ld */ true, nullptr, size, addr, flags, nullptr); 8891060SN/A} 8901060SN/A 8911060SN/Atemplate<class Impl> 8927520Sgblack@eecs.umich.eduFault 89311608Snikos.nikoleris@arm.comBaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr, 89411608Snikos.nikoleris@arm.com Request::Flags flags, uint64_t *res) 8951060SN/A{ 89613590Srekai.gonzalezalberquilla@arm.com return cpu->pushRequest( 89713590Srekai.gonzalezalberquilla@arm.com dynamic_cast<typename DynInstPtr::PtrType>(this), 89813590Srekai.gonzalezalberquilla@arm.com /* st */ false, data, size, addr, flags, res); 8996973Stjones1@inf.ed.ac.uk} 9006973Stjones1@inf.ed.ac.uk 9011464SN/A#endif // __CPU_BASE_DYN_INST_HH__ 902